diff options
author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-21 16:36:57 +0000 |
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committer | GitHub <noreply@github.com> | 2019-06-21 16:36:57 +0000 |
commit | 0f5761d7d32edddf93f302f52b903e8acca08c5e (patch) | |
tree | 46ff4106f51fb6d5f682cf6af73ef1a4ab5f147e /bsp/coreip-u54-rtl/README.md | |
parent | eecf71d7cf0ec12997dbceffde190b1086595908 (diff) | |
parent | 713237cb963ebf81aca0715d8a770fdbe5d71cb9 (diff) |
Merge pull request #287 from sifive/remove-coreip-bsps
Remove all CoreIP BSPs
Diffstat (limited to 'bsp/coreip-u54-rtl/README.md')
-rw-r--r-- | bsp/coreip-u54-rtl/README.md | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/bsp/coreip-u54-rtl/README.md b/bsp/coreip-u54-rtl/README.md deleted file mode 100644 index cd34149..0000000 --- a/bsp/coreip-u54-rtl/README.md +++ /dev/null @@ -1,17 +0,0 @@ -The SiFive U54 Standard Core is a single-core instantiation of the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. - -The U54 is ideal for low-cost Linux applications such as IoT nodes and gateways, point-of-sale, and networking. - -This target features: - -- 1 RV64GC U54 Application Core -- 16KB L1 I-cache with ECC -- 16KB L1 D-cache with ECC -- 8 Region Physical Memory Protection -- 48 Local Interrupts per core -- Sv39 Virtual Memory support with 38 Physical Address bits -- Integrated 128KB L2 Cache with ECC -- Real-time capabilities -- CLINT for multi-core timer and software interrupts -- PLIC with support for up to 128 interrupts with 7 priority levels -- Debug with instruction trace |