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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-05-22 17:53:09 +0000
committerGitHub <noreply@github.com>2019-05-22 17:53:09 +0000
commit44deff8b8d615721c11ab5f408da73030b01d0f9 (patch)
tree34cd2bb52009a596dc8de95bf2b7262f5a6ce3f9 /bsp/coreip-u54-rtl/design.dts
parent9946f2062837098088e4c9701614a2eeffaa921b (diff)
parentc5dd42c68d030a356c85bb8d174296b4f2df615d (diff)
Merge pull request #254 from sifive/dts-pmpregions
Update to new-style riscv,pmpregions property
Diffstat (limited to 'bsp/coreip-u54-rtl/design.dts')
-rw-r--r--bsp/coreip-u54-rtl/design.dts5
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-u54-rtl/design.dts b/bsp/coreip-u54-rtl/design.dts
index b773072..154dc42 100644
--- a/bsp/coreip-u54-rtl/design.dts
+++ b/bsp/coreip-u54-rtl/design.dts
@@ -26,6 +26,7 @@
next-level-cache = <&L16>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L6>;
status = "okay";
timebase-frequency = <1000000>;
@@ -46,10 +47,6 @@
#size-cells = <2>;
compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L13: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;