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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-02 20:04:34 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-02 20:04:34 +0000 |
| commit | 139149a670354a74cb2a5693c270bb24ea39dc05 (patch) | |
| tree | 01ff5eda110417a43bcbff9c6b76fb62a6a5191d /bsp/coreip-u54-rtl | |
| parent | b178ea51465fdaf68e848dc8f55be03bd140013a (diff) | |
| parent | b555941a3d06c31e03ecf51eef608c7356bdb3b9 (diff) | |
Merge pull request #239 from sifive/bare-header
Update to use metal-platform.h (bare header)
Diffstat (limited to 'bsp/coreip-u54-rtl')
| -rw-r--r-- | bsp/coreip-u54-rtl/metal-platform.h | 38 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/metal.h | 16 |
2 files changed, 47 insertions, 7 deletions
diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h new file mode 100644 index 0000000..79432cd --- /dev/null +++ b/bsp/coreip-u54-rtl/metal-platform.h @@ -0,0 +1,38 @@ +#ifndef COREIP_U54_RTL__METAL_PLATFORM_H +#define COREIP_U54_RTL__METAL_PLATFORM_H + +/* From clint@2000000 */ +#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL +#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL + +#define METAL_RISCV_CLINT0 +#define METAL_RISCV_CLINT0_MSIP_BASE 0UL +#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL +#define METAL_RISCV_CLINT0_MTIME 49144UL + +/* From interrupt_controller@c000000 */ +#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL +#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL +#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL +#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 133UL + +#define METAL_RISCV_PLIC0 +#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL +#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL +#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL +#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL +#define METAL_RISCV_PLIC0_CLAIM 2097156UL + +/* From pmp@0 */ +#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL + +#define METAL_RISCV_PMP + +/* From teststatus@4000 */ +#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL +#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL + +#define METAL_SIFIVE_TEST0 +#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL + +#endif /* COREIP_U54_RTL__METAL_PLATFORM_H*/ diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h index 3955675..38e231f 100644 --- a/bsp/coreip-u54-rtl/metal.h +++ b/bsp/coreip-u54-rtl/metal.h @@ -3,6 +3,8 @@ #ifndef COREIP_U54_RTL__METAL_H #define COREIP_U54_RTL__METAL_H +#include <metal/machine/platform.h> + #ifdef __METAL_MACHINE_MACROS #define __METAL_CLINT_NUM_PARENTS 2 @@ -127,8 +129,8 @@ struct metal_memory __metal_dt_mem_memory_80000000 = { struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, - .control_base = 33554432UL, - .control_size = 65536UL, + .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS, + .control_size = METAL_RISCV_CLINT0_2000000_SIZE, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, @@ -162,16 +164,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .interrupt_lines[0] = 11, .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 9, - .control_base = 201326592UL, - .control_size = 67108864UL, - .max_priority = 7UL, - .num_interrupts = 133UL, + .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS, + .control_size = METAL_RISCV_PLIC0_C000000_SIZE, + .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY, + .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV, .interrupt_controller = 1, }; /* From pmp@0 */ struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = 8UL, + .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, }; /* From global_external_interrupts */ |