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authorBunnaroath Sou <bsou@sifive.com>2019-05-20 14:34:10 -0700
committerBunnaroath Sou <bsou@sifive.com>2019-05-20 14:34:10 -0700
commit6af51ca7b09c8e5b7e1933700b1d855893ca42b1 (patch)
tree8012100cd786c31074d8bef0a8c5e699c4f1e3e5 /bsp/coreip-u54-rtl
parent24d98e5a409131e8be1a17bcbc3cda31297afe7a (diff)
Update BSP files to pickup inline support
Diffstat (limited to 'bsp/coreip-u54-rtl')
-rw-r--r--bsp/coreip-u54-rtl/metal-inline.h162
-rw-r--r--bsp/coreip-u54-rtl/metal-platform.h28
-rw-r--r--bsp/coreip-u54-rtl/metal.default.lds18
-rw-r--r--bsp/coreip-u54-rtl/metal.h874
-rw-r--r--bsp/coreip-u54-rtl/metal.ramrodata.lds18
-rw-r--r--bsp/coreip-u54-rtl/metal.scratchpad.lds18
-rw-r--r--bsp/coreip-u54-rtl/settings.mk6
7 files changed, 876 insertions, 248 deletions
diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h
new file mode 100644
index 0000000..03d29e6
--- /dev/null
+++ b/bsp/coreip-u54-rtl/metal-inline.h
@@ -0,0 +1,162 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11 */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_U54_RTL__METAL_INLINE_H
+#define COREIP_U54_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_itim_1800000 = {
+ ._base_address = 25165824UL,
+ ._size = 16384UL,
+ ._attrs = {
+ .R = 1,
+ .W = 1,
+ .X = 1,
+ .C = 1,
+ .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+ ._base_address = 2147483648UL,
+ ._size = 536870912UL,
+ ._attrs = {
+ .R = 1,
+ .W = 1,
+ .X = 1,
+ .C = 1,
+ .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+ .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+ .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+ .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+ .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+ .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+ .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+ .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+ .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+ .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+ .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+ .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From cache_controller@2010000 */
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
+ .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
+};
+
+
+#endif /* COREIP_U54_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h
index 79432cd..562f263 100644
--- a/bsp/coreip-u54-rtl/metal-platform.h
+++ b/bsp/coreip-u54-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11 */
+/* ----------------------------------- */
+
#ifndef COREIP_U54_RTL__METAL_PLATFORM_H
#define COREIP_U54_RTL__METAL_PLATFORM_H
/* From clint@2000000 */
#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
#define METAL_RISCV_CLINT0
#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
/* From interrupt_controller@c000000 */
#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 133UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 133UL
#define METAL_RISCV_PLIC0
#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,25 @@
#define METAL_RISCV_PMP
+/* From cache_controller@2010000 */
+#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL
+#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL
+
+#define METAL_SIFIVE_FU540_C000_L2
+#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL
+#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL
+
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
/* From teststatus@4000 */
#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
#define METAL_SIFIVE_TEST0
#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds
index ae24b07..3a5705a 100644
--- a/bsp/coreip-u54-rtl/metal.default.lds
+++ b/bsp/coreip-u54-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11 */
+/* ----------------------------------- */
+
OUTPUT_ARCH("riscv")
ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
} >ram AT>ram :ram
@@ -169,12 +181,6 @@ SECTIONS
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.* .sdata2.*)
*(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
} >ram AT>ram :ram_init
diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h
index 38e231f..0621896 100644
--- a/bsp/coreip-u54-rtl/metal.h
+++ b/bsp/coreip-u54-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11 */
+/* ----------------------------------- */
-#ifndef COREIP_U54_RTL__METAL_H
-#define COREIP_U54_RTL__METAL_H
+#ifndef ASSEMBLY
#include <metal/machine/platform.h>
#ifdef __METAL_MACHINE_MACROS
+#ifndef MACROS_IF_COREIP_U54_RTL__METAL_H
+#define MACROS_IF_COREIP_U54_RTL__METAL_H
+
#define __METAL_CLINT_NUM_PARENTS 2
#ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
#define __METAL_CLIC_SUBINTERRUPTS 0
#endif
+#endif /* MACROS_IF_COREIP_U54_RTL__METAL_H*/
+
#else /* ! __METAL_MACHINE_MACROS */
+#ifndef MACROS_ELSE_COREIP_U54_RTL__METAL_H
+#define MACROS_ELSE_COREIP_U54_RTL__METAL_H
+
#define __METAL_CLINT_2000000_INTERRUPTS 2
#define METAL_MAX_CLINT_INTERRUPTS 2
@@ -66,266 +77,663 @@
#include <metal/drivers/sifive,test0.h>
#include <metal/drivers/sifive,fu540-c000,l2.h>
-asm (".weak __metal_dt_mem_itim_1800000");
struct metal_memory __metal_dt_mem_itim_1800000;
-asm (".weak __metal_dt_mem_memory_80000000");
struct metal_memory __metal_dt_mem_memory_80000000;
/* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
/* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
struct __metal_driver_cpu __metal_dt_cpu_0;
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
/* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
-asm (".weak __metal_dt_pmp_0");
struct metal_pmp __metal_dt_pmp_0;
/* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
/* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
/* From cache_controller@2010000 */
-asm (".weak __metal_dt_cache_controller_2010000");
struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
-struct metal_memory __metal_dt_mem_itim_1800000 = {
- ._base_address = 25165824UL,
- ._size = 16384UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
- ._base_address = 2147483648UL,
- ._size = 536870912UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
- .vtable = &__metal_driver_vtable_riscv_clint0,
- .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
- .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
- .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
- .init_done = 0,
- .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
- .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
- .interrupt_lines[0] = 3,
- .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
- .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+ return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+ return METAL_RISCV_CLINT0_2000000_SIZE;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+ return METAL_MAX_CLINT_INTERRUPTS;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+ if (idx == 0) {
+ return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+ }
+ else if (idx == 1) {
+ return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+ }
+ else {
+ return NULL;
+ }
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+ if (idx == 0) {
+ return 3;
+ }
+ else if (idx == 1) {
+ return 7;
+ }
+ else {
+ return 0;
+ }
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 1000000;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return &__metal_dt_cpu_0_interrupt_controller.controller;
+ }
+ else {
+ return NULL;
+ }
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+ return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+ return METAL_RISCV_PLIC0_C000000_SIZE;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+ return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+ return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+ if (idx == 0) {
+ return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+ }
+ else if (idx == 0) {
+ return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+ }
+ else if (idx == 1) {
+ return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+ }
+ else {
+ return NULL;
+ }
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+ if (idx == 0) {
+ return 11;
+ }
+ else if (idx == 0) {
+ return 11;
+ }
+ else if (idx == 1) {
+ return 9;
+ }
+ else {
+ return 0;
+ }
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+ return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+ return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+ }
+ else {
+ return NULL;
+ }
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+ if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+ return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+ }
+ else {
+ return 0;
+ }
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+ if (idx == 0) {
+ return 1;
+ }
+ else if (idx == 1) {
+ return 2;
+ }
+ else if (idx == 2) {
+ return 3;
+ }
+ else if (idx == 3) {
+ return 4;
+ }
+ else if (idx == 4) {
+ return 5;
+ }
+ else if (idx == 5) {
+ return 6;
+ }
+ else if (idx == 6) {
+ return 7;
+ }
+ else if (idx == 7) {
+ return 8;
+ }
+ else if (idx == 8) {
+ return 9;
+ }
+ else if (idx == 9) {
+ return 10;
+ }
+ else if (idx == 10) {
+ return 11;
+ }
+ else if (idx == 11) {
+ return 12;
+ }
+ else if (idx == 12) {
+ return 13;
+ }
+ else if (idx == 13) {
+ return 14;
+ }
+ else if (idx == 14) {
+ return 15;
+ }
+ else if (idx == 15) {
+ return 16;
+ }
+ else if (idx == 16) {
+ return 17;
+ }
+ else if (idx == 17) {
+ return 18;
+ }
+ else if (idx == 18) {
+ return 19;
+ }
+ else if (idx == 19) {
+ return 20;
+ }
+ else if (idx == 20) {
+ return 21;
+ }
+ else if (idx == 21) {
+ return 22;
+ }
+ else if (idx == 22) {
+ return 23;
+ }
+ else if (idx == 23) {
+ return 24;
+ }
+ else if (idx == 24) {
+ return 25;
+ }
+ else if (idx == 25) {
+ return 26;
+ }
+ else if (idx == 26) {
+ return 27;
+ }
+ else if (idx == 27) {
+ return 28;
+ }
+ else if (idx == 28) {
+ return 29;
+ }
+ else if (idx == 29) {
+ return 30;
+ }
+ else if (idx == 30) {
+ return 31;
+ }
+ else if (idx == 31) {
+ return 32;
+ }
+ else if (idx == 32) {
+ return 33;
+ }
+ else if (idx == 33) {
+ return 34;
+ }
+ else if (idx == 34) {
+ return 35;
+ }
+ else if (idx == 35) {
+ return 36;
+ }
+ else if (idx == 36) {
+ return 37;
+ }
+ else if (idx == 37) {
+ return 38;
+ }
+ else if (idx == 38) {
+ return 39;
+ }
+ else if (idx == 39) {
+ return 40;
+ }
+ else if (idx == 40) {
+ return 41;
+ }
+ else if (idx == 41) {
+ return 42;
+ }
+ else if (idx == 42) {
+ return 43;
+ }
+ else if (idx == 43) {
+ return 44;
+ }
+ else if (idx == 44) {
+ return 45;
+ }
+ else if (idx == 45) {
+ return 46;
+ }
+ else if (idx == 46) {
+ return 47;
+ }
+ else if (idx == 47) {
+ return 48;
+ }
+ else if (idx == 48) {
+ return 49;
+ }
+ else if (idx == 49) {
+ return 50;
+ }
+ else if (idx == 50) {
+ return 51;
+ }
+ else if (idx == 51) {
+ return 52;
+ }
+ else if (idx == 52) {
+ return 53;
+ }
+ else if (idx == 53) {
+ return 54;
+ }
+ else if (idx == 54) {
+ return 55;
+ }
+ else if (idx == 55) {
+ return 56;
+ }
+ else if (idx == 56) {
+ return 57;
+ }
+ else if (idx == 57) {
+ return 58;
+ }
+ else if (idx == 58) {
+ return 59;
+ }
+ else if (idx == 59) {
+ return 60;
+ }
+ else if (idx == 60) {
+ return 61;
+ }
+ else if (idx == 61) {
+ return 62;
+ }
+ else if (idx == 62) {
+ return 63;
+ }
+ else if (idx == 63) {
+ return 64;
+ }
+ else if (idx == 64) {
+ return 65;
+ }
+ else if (idx == 65) {
+ return 66;
+ }
+ else if (idx == 66) {
+ return 67;
+ }
+ else if (idx == 67) {
+ return 68;
+ }
+ else if (idx == 68) {
+ return 69;
+ }
+ else if (idx == 69) {
+ return 70;
+ }
+ else if (idx == 70) {
+ return 71;
+ }
+ else if (idx == 71) {
+ return 72;
+ }
+ else if (idx == 72) {
+ return 73;
+ }
+ else if (idx == 73) {
+ return 74;
+ }
+ else if (idx == 74) {
+ return 75;
+ }
+ else if (idx == 75) {
+ return 76;
+ }
+ else if (idx == 76) {
+ return 77;
+ }
+ else if (idx == 77) {
+ return 78;
+ }
+ else if (idx == 78) {
+ return 79;
+ }
+ else if (idx == 79) {
+ return 80;
+ }
+ else if (idx == 80) {
+ return 81;
+ }
+ else if (idx == 81) {
+ return 82;
+ }
+ else if (idx == 82) {
+ return 83;
+ }
+ else if (idx == 83) {
+ return 84;
+ }
+ else if (idx == 84) {
+ return 85;
+ }
+ else if (idx == 85) {
+ return 86;
+ }
+ else if (idx == 86) {
+ return 87;
+ }
+ else if (idx == 87) {
+ return 88;
+ }
+ else if (idx == 88) {
+ return 89;
+ }
+ else if (idx == 89) {
+ return 90;
+ }
+ else if (idx == 90) {
+ return 91;
+ }
+ else if (idx == 91) {
+ return 92;
+ }
+ else if (idx == 92) {
+ return 93;
+ }
+ else if (idx == 93) {
+ return 94;
+ }
+ else if (idx == 94) {
+ return 95;
+ }
+ else if (idx == 95) {
+ return 96;
+ }
+ else if (idx == 96) {
+ return 97;
+ }
+ else if (idx == 97) {
+ return 98;
+ }
+ else if (idx == 98) {
+ return 99;
+ }
+ else if (idx == 99) {
+ return 100;
+ }
+ else if (idx == 100) {
+ return 101;
+ }
+ else if (idx == 101) {
+ return 102;
+ }
+ else if (idx == 102) {
+ return 103;
+ }
+ else if (idx == 103) {
+ return 104;
+ }
+ else if (idx == 104) {
+ return 105;
+ }
+ else if (idx == 105) {
+ return 106;
+ }
+ else if (idx == 106) {
+ return 107;
+ }
+ else if (idx == 107) {
+ return 108;
+ }
+ else if (idx == 108) {
+ return 109;
+ }
+ else if (idx == 109) {
+ return 110;
+ }
+ else if (idx == 110) {
+ return 111;
+ }
+ else if (idx == 111) {
+ return 112;
+ }
+ else if (idx == 112) {
+ return 113;
+ }
+ else if (idx == 113) {
+ return 114;
+ }
+ else if (idx == 114) {
+ return 115;
+ }
+ else if (idx == 115) {
+ return 116;
+ }
+ else if (idx == 116) {
+ return 117;
+ }
+ else if (idx == 117) {
+ return 118;
+ }
+ else if (idx == 118) {
+ return 119;
+ }
+ else if (idx == 119) {
+ return 120;
+ }
+ else if (idx == 120) {
+ return 121;
+ }
+ else if (idx == 121) {
+ return 122;
+ }
+ else if (idx == 122) {
+ return 123;
+ }
+ else if (idx == 123) {
+ return 124;
+ }
+ else if (idx == 124) {
+ return 125;
+ }
+ else if (idx == 125) {
+ return 126;
+ }
+ else if (idx == 126) {
+ return 127;
+ }
+ else {
+ return 0;
+ }
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+ return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+ return 4096;
+}
+
+
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
- .vtable = &__metal_driver_vtable_cpu,
- .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
- .timebase = 1000000UL,
- .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
- .vtable = &__metal_driver_vtable_riscv_cpu_intc,
- .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
- .init_done = 0,
- .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
- .vtable = &__metal_driver_vtable_riscv_plic0,
- .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
- .init_done = 0,
- .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
- .interrupt_lines[0] = 11,
- .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
- .interrupt_lines[1] = 9,
- .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
- .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
- .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
- .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
- .interrupt_controller = 1,
-};
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
- .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
- .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
- .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
- .init_done = 0,
-/* From interrupt_controller@c000000 */
- .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
- .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
- .interrupt_lines[0] = 1,
- .interrupt_lines[1] = 2,
- .interrupt_lines[2] = 3,
- .interrupt_lines[3] = 4,
- .interrupt_lines[4] = 5,
- .interrupt_lines[5] = 6,
- .interrupt_lines[6] = 7,
- .interrupt_lines[7] = 8,
- .interrupt_lines[8] = 9,
- .interrupt_lines[9] = 10,
- .interrupt_lines[10] = 11,
- .interrupt_lines[11] = 12,
- .interrupt_lines[12] = 13,
- .interrupt_lines[13] = 14,
- .interrupt_lines[14] = 15,
- .interrupt_lines[15] = 16,
- .interrupt_lines[16] = 17,
- .interrupt_lines[17] = 18,
- .interrupt_lines[18] = 19,
- .interrupt_lines[19] = 20,
- .interrupt_lines[20] = 21,
- .interrupt_lines[21] = 22,
- .interrupt_lines[22] = 23,
- .interrupt_lines[23] = 24,
- .interrupt_lines[24] = 25,
- .interrupt_lines[25] = 26,
- .interrupt_lines[26] = 27,
- .interrupt_lines[27] = 28,
- .interrupt_lines[28] = 29,
- .interrupt_lines[29] = 30,
- .interrupt_lines[30] = 31,
- .interrupt_lines[31] = 32,
- .interrupt_lines[32] = 33,
- .interrupt_lines[33] = 34,
- .interrupt_lines[34] = 35,
- .interrupt_lines[35] = 36,
- .interrupt_lines[36] = 37,
- .interrupt_lines[37] = 38,
- .interrupt_lines[38] = 39,
- .interrupt_lines[39] = 40,
- .interrupt_lines[40] = 41,
- .interrupt_lines[41] = 42,
- .interrupt_lines[42] = 43,
- .interrupt_lines[43] = 44,
- .interrupt_lines[44] = 45,
- .interrupt_lines[45] = 46,
- .interrupt_lines[46] = 47,
- .interrupt_lines[47] = 48,
- .interrupt_lines[48] = 49,
- .interrupt_lines[49] = 50,
- .interrupt_lines[50] = 51,
- .interrupt_lines[51] = 52,
- .interrupt_lines[52] = 53,
- .interrupt_lines[53] = 54,
- .interrupt_lines[54] = 55,
- .interrupt_lines[55] = 56,
- .interrupt_lines[56] = 57,
- .interrupt_lines[57] = 58,
- .interrupt_lines[58] = 59,
- .interrupt_lines[59] = 60,
- .interrupt_lines[60] = 61,
- .interrupt_lines[61] = 62,
- .interrupt_lines[62] = 63,
- .interrupt_lines[63] = 64,
- .interrupt_lines[64] = 65,
- .interrupt_lines[65] = 66,
- .interrupt_lines[66] = 67,
- .interrupt_lines[67] = 68,
- .interrupt_lines[68] = 69,
- .interrupt_lines[69] = 70,
- .interrupt_lines[70] = 71,
- .interrupt_lines[71] = 72,
- .interrupt_lines[72] = 73,
- .interrupt_lines[73] = 74,
- .interrupt_lines[74] = 75,
- .interrupt_lines[75] = 76,
- .interrupt_lines[76] = 77,
- .interrupt_lines[77] = 78,
- .interrupt_lines[78] = 79,
- .interrupt_lines[79] = 80,
- .interrupt_lines[80] = 81,
- .interrupt_lines[81] = 82,
- .interrupt_lines[82] = 83,
- .interrupt_lines[83] = 84,
- .interrupt_lines[84] = 85,
- .interrupt_lines[85] = 86,
- .interrupt_lines[86] = 87,
- .interrupt_lines[87] = 88,
- .interrupt_lines[88] = 89,
- .interrupt_lines[89] = 90,
- .interrupt_lines[90] = 91,
- .interrupt_lines[91] = 92,
- .interrupt_lines[92] = 93,
- .interrupt_lines[93] = 94,
- .interrupt_lines[94] = 95,
- .interrupt_lines[95] = 96,
- .interrupt_lines[96] = 97,
- .interrupt_lines[97] = 98,
- .interrupt_lines[98] = 99,
- .interrupt_lines[99] = 100,
- .interrupt_lines[100] = 101,
- .interrupt_lines[101] = 102,
- .interrupt_lines[102] = 103,
- .interrupt_lines[103] = 104,
- .interrupt_lines[104] = 105,
- .interrupt_lines[105] = 106,
- .interrupt_lines[106] = 107,
- .interrupt_lines[107] = 108,
- .interrupt_lines[108] = 109,
- .interrupt_lines[109] = 110,
- .interrupt_lines[110] = 111,
- .interrupt_lines[111] = 112,
- .interrupt_lines[112] = 113,
- .interrupt_lines[113] = 114,
- .interrupt_lines[114] = 115,
- .interrupt_lines[115] = 116,
- .interrupt_lines[116] = 117,
- .interrupt_lines[117] = 118,
- .interrupt_lines[118] = 119,
- .interrupt_lines[119] = 120,
- .interrupt_lines[120] = 121,
- .interrupt_lines[121] = 122,
- .interrupt_lines[122] = 123,
- .interrupt_lines[123] = 124,
- .interrupt_lines[124] = 125,
- .interrupt_lines[125] = 126,
- .interrupt_lines[126] = 127,
-};
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
- .vtable = &__metal_driver_vtable_sifive_test0,
- .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
- .base = 16384UL,
- .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
- .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2,
- .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
#define __METAL_DT_MAX_MEMORIES 2
@@ -389,7 +797,13 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
+/* From cache_controller@2010000 */
+#define __METAL_DT_SIFIVE_FU540_C000_L2_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#define __METAL_DT_CACHE_CONTROLLER_2010000_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#endif /* MACROS_ELSE_COREIP_U54_RTL__METAL_H*/
#endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_U54_RTL__METAL_H*/
+
#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds
index 306ba19..2873493 100644
--- a/bsp/coreip-u54-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11 */
+/* ----------------------------------- */
+
OUTPUT_ARCH("riscv")
ENTRY(_enter)
@@ -160,18 +166,18 @@ SECTIONS
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.* .sdata2.*)
- *(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.* .sdata2.*)
+ *(.gnu.linkonce.s.*)
} >ram AT>ram :ram_init
diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds
index ae24b07..3a5705a 100644
--- a/bsp/coreip-u54-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11 */
+/* ----------------------------------- */
+
OUTPUT_ARCH("riscv")
ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
} >ram AT>ram :ram
@@ -169,12 +181,6 @@ SECTIONS
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.* .sdata2.*)
*(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
} >ram AT>ram :ram_init
diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk
index d6b3a83..6c25a1f 100644
--- a/bsp/coreip-u54-rtl/settings.mk
+++ b/bsp/coreip-u54-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-11 #
+# ----------------------------------- #
+
RISCV_ARCH=rv64imafdc
RISCV_ABI=lp64d
RISCV_CMODEL=medany