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author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-30 16:59:29 +0000 |
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committer | GitHub <noreply@github.com> | 2019-04-30 16:59:29 +0000 |
commit | 0c75c6a612a1620bf1ffe82cd5c77ef9a8369045 (patch) | |
tree | 1a11e4304b06fbee9c0e525d81c0789530dfba35 /bsp/coreip-u54mc-rtl/README.md | |
parent | a351dc8d6aaf1a10be9a08e66c78c37126833d6a (diff) | |
parent | 8cd756c200cb13c036115a4b851b94f686cf3a3a (diff) |
Merge pull request #235 from sifive/u54-rtl
Add Multicore Support
Diffstat (limited to 'bsp/coreip-u54mc-rtl/README.md')
-rw-r--r-- | bsp/coreip-u54mc-rtl/README.md | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/bsp/coreip-u54mc-rtl/README.md b/bsp/coreip-u54mc-rtl/README.md new file mode 100644 index 0000000..1d26288 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/README.md @@ -0,0 +1,23 @@ +The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. + +The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking. + +This target features: + +- 4x RV64GC U54 Application Cores + - 32KB L1 I-cache with ECC + - 32KB L1 D-cache with ECC + - 8 Region Physical Memory Protection + - 48 Local Interrupts per core + - Sv39 Virtual Memory support with 38 Physical Address bits +- 1x RV64IMAC S51 Monitor Core + - 16KB L1 I-Cache with ECC + - 8KB DTIM with ECC + - 8 Region Physical Memory Protection + - 48 Local Interrupts +- Fully Coherent TileLink Bus +- Integrated 2MB L2 Cache with ECC +- Real-time capabilities +- CLINT for multi-core timer and software interrupts +- PLIC with support for up to 511 interrupts with 7 priority levels +- Debug with instruction trace |