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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-19 15:26:20 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-19 15:27:52 -0700 |
| commit | 0d6aad1a8c3b806716add4b5bb6954984d508ab3 (patch) | |
| tree | 9c6ef58cd92036a9c9eb23713e8f646af43e456e /bsp/coreip-u54mc-rtl/README.md | |
| parent | 00a58b4a52a6a3678c1359d76a8647fd5f528b9b (diff) | |
Delete coreip BSPs
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-u54mc-rtl/README.md')
| -rw-r--r-- | bsp/coreip-u54mc-rtl/README.md | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/bsp/coreip-u54mc-rtl/README.md b/bsp/coreip-u54mc-rtl/README.md deleted file mode 100644 index 1d26288..0000000 --- a/bsp/coreip-u54mc-rtl/README.md +++ /dev/null @@ -1,23 +0,0 @@ -The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. - -The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking. - -This target features: - -- 4x RV64GC U54 Application Cores - - 32KB L1 I-cache with ECC - - 32KB L1 D-cache with ECC - - 8 Region Physical Memory Protection - - 48 Local Interrupts per core - - Sv39 Virtual Memory support with 38 Physical Address bits -- 1x RV64IMAC S51 Monitor Core - - 16KB L1 I-Cache with ECC - - 8KB DTIM with ECC - - 8 Region Physical Memory Protection - - 48 Local Interrupts -- Fully Coherent TileLink Bus -- Integrated 2MB L2 Cache with ECC -- Real-time capabilities -- CLINT for multi-core timer and software interrupts -- PLIC with support for up to 511 interrupts with 7 priority levels -- Debug with instruction trace |