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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-05 14:45:28 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-12 13:47:41 -0700 |
| commit | 2aa264a54b3aa1e3257805b55401718786939e47 (patch) | |
| tree | 0db2eb4c3ba2d10f8f8963e90efc7409dcc8a84d /bsp/coreip-u54mc-rtl/README.md | |
| parent | c75d52d67bfa1568d6ac490224bae44d808b7d52 (diff) | |
Add target files for U54 and U54MC
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-u54mc-rtl/README.md')
| -rw-r--r-- | bsp/coreip-u54mc-rtl/README.md | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/bsp/coreip-u54mc-rtl/README.md b/bsp/coreip-u54mc-rtl/README.md new file mode 100644 index 0000000..1d26288 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/README.md @@ -0,0 +1,23 @@ +The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. + +The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking. + +This target features: + +- 4x RV64GC U54 Application Cores + - 32KB L1 I-cache with ECC + - 32KB L1 D-cache with ECC + - 8 Region Physical Memory Protection + - 48 Local Interrupts per core + - Sv39 Virtual Memory support with 38 Physical Address bits +- 1x RV64IMAC S51 Monitor Core + - 16KB L1 I-Cache with ECC + - 8KB DTIM with ECC + - 8 Region Physical Memory Protection + - 48 Local Interrupts +- Fully Coherent TileLink Bus +- Integrated 2MB L2 Cache with ECC +- Real-time capabilities +- CLINT for multi-core timer and software interrupts +- PLIC with support for up to 511 interrupts with 7 priority levels +- Debug with instruction trace |