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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-05-20 14:39:42 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-20 14:39:42 -0700 |
| commit | 615a076df87a021c07e6e3bfecca3ad4f27a76bb (patch) | |
| tree | 8012100cd786c31074d8bef0a8c5e699c4f1e3e5 /bsp/coreip-u54mc-rtl/metal-platform.h | |
| parent | 44c4b9b6383f788fd29de5852cc645f0c76687a4 (diff) | |
| parent | 6af51ca7b09c8e5b7e1933700b1d855893ca42b1 (diff) | |
Merge pull request #240 from sifive/inline-fnvec
Updating BSP to pickup FDT inline support for generates metal files
Diffstat (limited to 'bsp/coreip-u54mc-rtl/metal-platform.h')
| -rw-r--r-- | bsp/coreip-u54mc-rtl/metal-platform.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h index a2ef2dc..6df003f 100644 --- a/bsp/coreip-u54mc-rtl/metal-platform.h +++ b/bsp/coreip-u54mc-rtl/metal-platform.h @@ -1,9 +1,17 @@ +/* Copyright 2019 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* ----------------------------------- */ +/* [XXXXX] 20-05-2019 14-26-11 */ +/* ----------------------------------- */ + #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H #define COREIP_U54MC_RTL__METAL_PLATFORM_H /* From clint@2000000 */ #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL +#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL +#define METAL_RISCV_CLINT0_0_SIZE 65536UL #define METAL_RISCV_CLINT0 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL @@ -12,9 +20,13 @@ /* From interrupt_controller@c000000 */ #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL +#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL +#define METAL_RISCV_PLIC0_0_SIZE 67108864UL #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL +#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 137UL +#define METAL_RISCV_PLIC0_0_RISCV_NDEV 137UL #define METAL_RISCV_PLIC0 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL @@ -28,9 +40,25 @@ #define METAL_RISCV_PMP +/* From cache_controller@2010000 */ +#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL +#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL +#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL +#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL + +#define METAL_SIFIVE_FU540_C000_L2 +#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL +#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL + +/* From global_external_interrupts */ + +#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 + /* From teststatus@4000 */ #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL +#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL +#define METAL_SIFIVE_TEST0_0_SIZE 4096UL #define METAL_SIFIVE_TEST0 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL |