Merge pull request #235 from sifive/u54-rtl

Add Multicore Support

7 files changed, 1601 insertions, 0 deletions

diff --git a/bsp/coreip-u54mc-rtl/README.md b/bsp/coreip-u54mc-rtl/README.md
new file mode 100644
index 0000000..1d26288
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/README.md
@@ -0,0 +1,23 @@
+The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.
+
+The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking.
+
+This target features:
+
+- 4x RV64GC U54 Application Cores
+    - 32KB L1 I-cache with ECC
+    - 32KB L1 D-cache with ECC
+    - 8 Region Physical Memory Protection
+    - 48 Local Interrupts per core
+    - Sv39 Virtual Memory support with 38 Physical Address bits
+- 1x RV64IMAC S51 Monitor Core
+    - 16KB L1 I-Cache with ECC
+    - 8KB DTIM with ECC
+    - 8 Region Physical Memory Protection
+    - 48 Local Interrupts
+- Fully Coherent TileLink Bus
+- Integrated 2MB L2 Cache with ECC
+- Real-time capabilities
+- CLINT for multi-core timer and software interrupts
+- PLIC with support for up to 511 interrupts with 7 priority levels
+- Debug with instruction trace
diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts
new file mode 100644
index 0000000..27a3c94
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/design.dts
@@ -0,0 +1,290 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev";
+	model = "SiFive,FU540G";
+	L36: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		L9: cpu@0 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			next-level-cache = <&L33>;
+			reg = <0x0>;
+			riscv,isa = "rv64imac";
+			sifive,dtim = <&L7>;
+			sifive,itim = <&L6>;
+			status = "okay";
+			timebase-frequency = <1000000>;
+			L5: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L13: cpu@1 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L33>;
+			reg = <0x1>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L11>;
+			status = "okay";
+			timebase-frequency = <1000000>;
+			tlb-split;
+			L10: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L17: cpu@2 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L33>;
+			reg = <0x2>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L15>;
+			status = "okay";
+			timebase-frequency = <1000000>;
+			tlb-split;
+			L14: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L21: cpu@3 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L33>;
+			reg = <0x3>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L19>;
+			status = "okay";
+			timebase-frequency = <1000000>;
+			tlb-split;
+			L18: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L25: cpu@4 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L33>;
+			reg = <0x4>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L23>;
+			status = "okay";
+			timebase-frequency = <1000000>;
+			tlb-split;
+			L22: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	L28: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x20000000>;
+	};
+	L35: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
+		ranges;
+		pmp: pmp@0 {
+			compatible = "riscv,pmp";
+			regions = <8>;
+		};
+		L30: axi4-periph-port@20000000 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			compatible = "sifive,axi4-periph-port", "sifive,axi4-port", "sifive,periph-port", "simple-bus";
+			ranges = <0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x1 0x0 0x1 0x0 0xf 0x0>;
+		};
+		L29: axi4-sys-port@40000000 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-bus";
+			ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x10 0x0 0x10 0x0 0x30 0x0>;
+		};
+		L8: bus-error-unit@1700000 {
+			compatible = "sifive,buserror0";
+			interrupt-parent = <&L2>;
+			interrupts = <132>;
+			reg = <0x0 0x1700000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L12: bus-error-unit@1701000 {
+			compatible = "sifive,buserror0";
+			interrupt-parent = <&L2>;
+			interrupts = <133>;
+			reg = <0x0 0x1701000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L16: bus-error-unit@1702000 {
+			compatible = "sifive,buserror0";
+			interrupt-parent = <&L2>;
+			interrupts = <134>;
+			reg = <0x0 0x1702000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L20: bus-error-unit@1703000 {
+			compatible = "sifive,buserror0";
+			interrupt-parent = <&L2>;
+			interrupts = <135>;
+			reg = <0x0 0x1703000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L24: bus-error-unit@1704000 {
+			compatible = "sifive,buserror0";
+			interrupt-parent = <&L2>;
+			interrupts = <136>;
+			reg = <0x0 0x1704000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L33: cache-controller@2010000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+			compatible = "sifive,ccache0", "cache";
+			interrupt-parent = <&L2>;
+			interrupts = <128 129 130 131>;
+			next-level-cache = <&L0 &L28>;
+			reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x200000>;
+			reg-names = "control", "sideband";
+			sifive,ecc-granularity = <8>;
+			sifive,mshr-count = <6>;
+		};
+		L3: clint@2000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <&L5 3 &L5 7 &L10 3 &L10 7 &L14 3 &L14 7 &L18 3 &L18 7 &L22 3 &L22 7>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			reg-names = "control";
+		};
+		L4: debug-controller@0 {
+			compatible = "sifive,debug-013", "riscv,debug-013";
+			interrupts-extended = <&L5 65535 &L10 65535 &L14 65535 &L18 65535 &L22 65535>;
+			reg = <0x0 0x0 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L7: dtim@1000000 {
+			compatible = "sifive,dtim0";
+			reg = <0x0 0x1000000 0x0 0x2000>;
+			reg-names = "mem";
+		};
+		L1: error-device@3000 {
+			compatible = "sifive,error0";
+			reg = <0x0 0x3000 0x0 0x1000>;
+		};
+		L27: global-external-interrupts {
+			compatible = "sifive,global-external-interrupts0";
+			interrupt-parent = <&L2>;
+			interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>;
+		};
+		L2: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "riscv,plic0";
+			interrupt-controller;
+			interrupts-extended = <&L5 11 &L10 11 &L10 9 &L14 11 &L14 9 &L18 11 &L18 9 &L22 11 &L22 9>;
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <136>;
+		};
+		L6: itim@1800000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1800000 0x0 0x4000>;
+			reg-names = "mem";
+		};
+		L11: itim@1808000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1808000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L15: itim@1810000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1810000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L19: itim@1818000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1818000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L23: itim@1820000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1820000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L0: rom@a000000 {
+			compatible = "ucbbar,cacheable-zero0";
+			reg = <0x0 0xa000000 0x0 0x2000000>;
+		};
+		L26: teststatus@4000 {
+			compatible = "sifive,test0";
+			reg = <0x0 0x4000 0x0 0x1000>;
+			reg-names = "control";
+		};
+	};
+};
diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds
new file mode 100644
index 0000000..0d12f67
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/metal.default.lds
@@ -0,0 +1,230 @@
+OUTPUT_ARCH("riscv")
+
+ENTRY(_enter)
+
+MEMORY
+{
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000
+	itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000
+}
+
+PHDRS
+{
+	flash PT_LOAD;
+	ram_init PT_LOAD;
+	itim_init PT_LOAD;
+	ram PT_LOAD;
+	itim PT_LOAD;
+}
+
+SECTIONS
+{
+	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
+	PROVIDE(__stack_size = __stack_size);
+	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+
+
+	.init 		:
+	{
+		KEEP (*(.text.metal.init.enter))
+		KEEP (*(SORT_NONE(.init)))
+		KEEP (*(.text.libgloss.start))
+	} >ram AT>ram :ram
+
+
+	.text 		:
+	{
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.*)
+		*(.gnu.linkonce.t.*)
+	} >ram AT>ram :ram
+
+
+	.fini 		:
+	{
+		KEEP (*(SORT_NONE(.fini)))
+	} >ram AT>ram :ram
+
+
+	PROVIDE (__etext = .);
+	PROVIDE (_etext = .);
+	PROVIDE (etext = .);
+
+
+	.rodata 		:
+	{
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+	} >ram AT>ram :ram
+
+
+	. = ALIGN(4);
+
+
+	.preinit_array 		:
+	{
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.init_array 		:
+	{
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+		PROVIDE_HIDDEN (__init_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.finit_array 		:
+	{
+		PROVIDE_HIDDEN (__finit_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+		PROVIDE_HIDDEN (__finit_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.ctors 		:
+	{
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >ram AT>ram :ram
+
+
+	.dtors 		:
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >ram AT>ram :ram
+
+
+	.litimalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_itim_source_start = . );
+	} >ram AT>ram :ram
+
+
+	.ditimalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_itim_target_start = . );
+	} >itim AT>ram :itim_init
+
+
+	.itim 		:
+	{
+		*(.itim .itim.*)
+	} >itim AT>ram :itim_init
+
+
+	. = ALIGN(8);
+	PROVIDE( metal_segment_itim_target_end = . );
+
+
+	.lalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( _data_lma = . );
+		PROVIDE( metal_segment_data_source_start = . );
+	} >ram AT>ram :ram
+
+
+	.dalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_data_target_start = . );
+	} >ram AT>ram :ram_init
+
+
+	.data 		:
+	{
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+	} >ram AT>ram :ram_init
+
+
+	. = ALIGN(4);
+	PROVIDE( _edata = . );
+	PROVIDE( edata = . );
+	PROVIDE( metal_segment_data_target_end = . );
+	PROVIDE( _fbss = . );
+	PROVIDE( __bss_start = . );
+	PROVIDE( metal_segment_bss_target_start = . );
+
+
+	.bss 		:
+	{
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(4);
+	} >ram AT>ram :ram
+
+
+	. = ALIGN(8);
+	PROVIDE( _end = . );
+	PROVIDE( end = . );
+	PROVIDE( metal_segment_bss_target_end = . );
+
+
+	.stack :
+	{
+		PROVIDE(metal_segment_stack_begin = .);
+		. = __stack_size;
+		PROVIDE( _sp = . );
+		. = __stack_size;
+		. = __stack_size;
+		. = __stack_size;
+		. = __stack_size;
+		PROVIDE(metal_segment_stack_end = .);
+	} >ram AT>ram :ram
+
+
+	.heap :
+	{
+		PROVIDE( metal_segment_heap_target_start = . );
+		. = __heap_size;
+		PROVIDE( metal_segment_heap_target_end = . );
+		PROVIDE( _heap_end = . );
+	} >ram AT>ram :ram
+
+
+}
+
diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h
new file mode 100644
index 0000000..380de59
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/metal.h
@@ -0,0 +1,594 @@
+#ifndef ASSEMBLY
+
+#ifndef COREIP_U54MC_RTL__METAL_H
+#define COREIP_U54MC_RTL__METAL_H
+
+#ifdef __METAL_MACHINE_MACROS
+
+#define __METAL_CLINT_NUM_PARENTS 10
+
+#ifndef __METAL_CLINT_NUM_PARENTS
+#define __METAL_CLINT_NUM_PARENTS 0
+#endif
+#define __METAL_PLIC_SUBINTERRUPTS 137
+
+#define __METAL_PLIC_NUM_PARENTS 9
+
+#ifndef __METAL_PLIC_SUBINTERRUPTS
+#define __METAL_PLIC_SUBINTERRUPTS 0
+#endif
+#ifndef __METAL_PLIC_NUM_PARENTS
+#define __METAL_PLIC_NUM_PARENTS 0
+#endif
+#ifndef __METAL_CLIC_SUBINTERRUPTS
+#define __METAL_CLIC_SUBINTERRUPTS 0
+#endif
+
+#else /* ! __METAL_MACHINE_MACROS */
+
+#define __METAL_CLINT_2000000_INTERRUPTS 10
+
+#define METAL_MAX_CLINT_INTERRUPTS 10
+
+#define __METAL_CLINT_NUM_PARENTS 10
+
+#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 9
+
+#define __METAL_PLIC_SUBINTERRUPTS 137
+
+#define METAL_MAX_PLIC_INTERRUPTS 9
+
+#define __METAL_PLIC_NUM_PARENTS 9
+
+#define __METAL_CLIC_SUBINTERRUPTS 0
+#define METAL_MAX_CLIC_INTERRUPTS 0
+
+#define METAL_MAX_LOCAL_EXT_INTERRUPTS 0
+
+#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 127
+
+#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 127
+
+#define METAL_MAX_GPIO_INTERRUPTS 0
+
+#define METAL_MAX_UART_INTERRUPTS 0
+
+
+#include <metal/drivers/fixed-clock.h>
+#include <metal/memory.h>
+#include <metal/drivers/riscv,clint0.h>
+#include <metal/drivers/riscv,cpu.h>
+#include <metal/drivers/riscv,plic0.h>
+#include <metal/pmp.h>
+#include <metal/drivers/sifive,global-external-interrupts0.h>
+#include <metal/drivers/sifive,test0.h>
+#include <metal/drivers/sifive,fu540-c000,l2.h>
+
+asm (".weak __metal_dt_mem_dtim_1000000");
+struct metal_memory __metal_dt_mem_dtim_1000000;
+
+asm (".weak __metal_dt_mem_itim_1800000");
+struct metal_memory __metal_dt_mem_itim_1800000;
+
+asm (".weak __metal_dt_mem_itim_1808000");
+struct metal_memory __metal_dt_mem_itim_1808000;
+
+asm (".weak __metal_dt_mem_itim_1810000");
+struct metal_memory __metal_dt_mem_itim_1810000;
+
+asm (".weak __metal_dt_mem_itim_1818000");
+struct metal_memory __metal_dt_mem_itim_1818000;
+
+asm (".weak __metal_dt_mem_itim_1820000");
+struct metal_memory __metal_dt_mem_itim_1820000;
+
+asm (".weak __metal_dt_mem_memory_80000000");
+struct metal_memory __metal_dt_mem_memory_80000000;
+
+/* From clint@2000000 */
+asm (".weak __metal_dt_clint_2000000");
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
+
+/* From cpu@0 */
+asm (".weak __metal_dt_cpu_0");
+struct __metal_driver_cpu __metal_dt_cpu_0;
+
+/* From cpu@1 */
+asm (".weak __metal_dt_cpu_1");
+struct __metal_driver_cpu __metal_dt_cpu_1;
+
+/* From cpu@2 */
+asm (".weak __metal_dt_cpu_2");
+struct __metal_driver_cpu __metal_dt_cpu_2;
+
+/* From cpu@3 */
+asm (".weak __metal_dt_cpu_3");
+struct __metal_driver_cpu __metal_dt_cpu_3;
+
+/* From cpu@4 */
+asm (".weak __metal_dt_cpu_4");
+struct __metal_driver_cpu __metal_dt_cpu_4;
+
+asm (".weak __metal_dt_cpu_0_interrupt_controller");
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
+
+asm (".weak __metal_dt_cpu_1_interrupt_controller");
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller;
+
+asm (".weak __metal_dt_cpu_2_interrupt_controller");
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller;
+
+asm (".weak __metal_dt_cpu_3_interrupt_controller");
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller;
+
+asm (".weak __metal_dt_cpu_4_interrupt_controller");
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller;
+
+/* From interrupt_controller@c000000 */
+asm (".weak __metal_dt_interrupt_controller_c000000");
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
+
+asm (".weak __metal_dt_pmp_0");
+struct metal_pmp __metal_dt_pmp_0;
+
+/* From global_external_interrupts */
+asm (".weak __metal_dt_global_external_interrupts");
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
+
+/* From teststatus@4000 */
+asm (".weak __metal_dt_teststatus_4000");
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
+
+/* From cache_controller@2010000 */
+asm (".weak __metal_dt_cache_controller_2010000");
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
+
+
+struct metal_memory __metal_dt_mem_dtim_1000000 = {
+    ._base_address = 16777216UL,
+    ._size = 8192UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1800000 = {
+    ._base_address = 25165824UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1808000 = {
+    ._base_address = 25198592UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1810000 = {
+    ._base_address = 25231360UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1818000 = {
+    ._base_address = 25264128UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1820000 = {
+    ._base_address = 25296896UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .vtable = &__metal_driver_vtable_riscv_clint0,
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .control_base = 33554432UL,
+    .control_size = 65536UL,
+    .init_done = 0,
+    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
+    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
+    .interrupt_lines[0] = 3,
+    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
+    .interrupt_lines[1] = 7,
+    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
+    .interrupt_lines[2] = 3,
+    .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller,
+    .interrupt_lines[3] = 7,
+    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
+    .interrupt_lines[4] = 3,
+    .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller,
+    .interrupt_lines[5] = 7,
+    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
+    .interrupt_lines[6] = 3,
+    .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller,
+    .interrupt_lines[7] = 7,
+    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
+    .interrupt_lines[8] = 3,
+    .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller,
+    .interrupt_lines[9] = 7,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .vtable = &__metal_driver_vtable_cpu,
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .timebase = 1000000UL,
+    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
+};
+
+/* From cpu@1 */
+struct __metal_driver_cpu __metal_dt_cpu_1 = {
+    .vtable = &__metal_driver_vtable_cpu,
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .timebase = 1000000UL,
+    .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller,
+};
+
+/* From cpu@2 */
+struct __metal_driver_cpu __metal_dt_cpu_2 = {
+    .vtable = &__metal_driver_vtable_cpu,
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .timebase = 1000000UL,
+    .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller,
+};
+
+/* From cpu@3 */
+struct __metal_driver_cpu __metal_dt_cpu_3 = {
+    .vtable = &__metal_driver_vtable_cpu,
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .timebase = 1000000UL,
+    .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller,
+};
+
+/* From cpu@4 */
+struct __metal_driver_cpu __metal_dt_cpu_4 = {
+    .vtable = &__metal_driver_vtable_cpu,
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+    .timebase = 1000000UL,
+    .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+    .interrupt_controller = 1,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
+    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+    .interrupt_controller = 1,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
+    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+    .interrupt_controller = 1,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
+    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+    .interrupt_controller = 1,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
+    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+    .interrupt_controller = 1,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .vtable = &__metal_driver_vtable_riscv_plic0,
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
+    .interrupt_lines[0] = 11,
+    .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller,
+    .interrupt_lines[1] = 11,
+    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
+    .interrupt_lines[2] = 9,
+    .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller,
+    .interrupt_lines[3] = 11,
+    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
+    .interrupt_lines[4] = 9,
+    .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller,
+    .interrupt_lines[5] = 11,
+    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
+    .interrupt_lines[6] = 9,
+    .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller,
+    .interrupt_lines[7] = 11,
+    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
+    .interrupt_lines[8] = 9,
+    .control_base = 201326592UL,
+    .control_size = 67108864UL,
+    .max_priority = 7UL,
+    .num_interrupts = 137UL,
+    .interrupt_controller = 1,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = 8UL,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+/* From interrupt_controller@c000000 */
+    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
+    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
+    .interrupt_lines[0] = 1,
+    .interrupt_lines[1] = 2,
+    .interrupt_lines[2] = 3,
+    .interrupt_lines[3] = 4,
+    .interrupt_lines[4] = 5,
+    .interrupt_lines[5] = 6,
+    .interrupt_lines[6] = 7,
+    .interrupt_lines[7] = 8,
+    .interrupt_lines[8] = 9,
+    .interrupt_lines[9] = 10,
+    .interrupt_lines[10] = 11,
+    .interrupt_lines[11] = 12,
+    .interrupt_lines[12] = 13,
+    .interrupt_lines[13] = 14,
+    .interrupt_lines[14] = 15,
+    .interrupt_lines[15] = 16,
+    .interrupt_lines[16] = 17,
+    .interrupt_lines[17] = 18,
+    .interrupt_lines[18] = 19,
+    .interrupt_lines[19] = 20,
+    .interrupt_lines[20] = 21,
+    .interrupt_lines[21] = 22,
+    .interrupt_lines[22] = 23,
+    .interrupt_lines[23] = 24,
+    .interrupt_lines[24] = 25,
+    .interrupt_lines[25] = 26,
+    .interrupt_lines[26] = 27,
+    .interrupt_lines[27] = 28,
+    .interrupt_lines[28] = 29,
+    .interrupt_lines[29] = 30,
+    .interrupt_lines[30] = 31,
+    .interrupt_lines[31] = 32,
+    .interrupt_lines[32] = 33,
+    .interrupt_lines[33] = 34,
+    .interrupt_lines[34] = 35,
+    .interrupt_lines[35] = 36,
+    .interrupt_lines[36] = 37,
+    .interrupt_lines[37] = 38,
+    .interrupt_lines[38] = 39,
+    .interrupt_lines[39] = 40,
+    .interrupt_lines[40] = 41,
+    .interrupt_lines[41] = 42,
+    .interrupt_lines[42] = 43,
+    .interrupt_lines[43] = 44,
+    .interrupt_lines[44] = 45,
+    .interrupt_lines[45] = 46,
+    .interrupt_lines[46] = 47,
+    .interrupt_lines[47] = 48,
+    .interrupt_lines[48] = 49,
+    .interrupt_lines[49] = 50,
+    .interrupt_lines[50] = 51,
+    .interrupt_lines[51] = 52,
+    .interrupt_lines[52] = 53,
+    .interrupt_lines[53] = 54,
+    .interrupt_lines[54] = 55,
+    .interrupt_lines[55] = 56,
+    .interrupt_lines[56] = 57,
+    .interrupt_lines[57] = 58,
+    .interrupt_lines[58] = 59,
+    .interrupt_lines[59] = 60,
+    .interrupt_lines[60] = 61,
+    .interrupt_lines[61] = 62,
+    .interrupt_lines[62] = 63,
+    .interrupt_lines[63] = 64,
+    .interrupt_lines[64] = 65,
+    .interrupt_lines[65] = 66,
+    .interrupt_lines[66] = 67,
+    .interrupt_lines[67] = 68,
+    .interrupt_lines[68] = 69,
+    .interrupt_lines[69] = 70,
+    .interrupt_lines[70] = 71,
+    .interrupt_lines[71] = 72,
+    .interrupt_lines[72] = 73,
+    .interrupt_lines[73] = 74,
+    .interrupt_lines[74] = 75,
+    .interrupt_lines[75] = 76,
+    .interrupt_lines[76] = 77,
+    .interrupt_lines[77] = 78,
+    .interrupt_lines[78] = 79,
+    .interrupt_lines[79] = 80,
+    .interrupt_lines[80] = 81,
+    .interrupt_lines[81] = 82,
+    .interrupt_lines[82] = 83,
+    .interrupt_lines[83] = 84,
+    .interrupt_lines[84] = 85,
+    .interrupt_lines[85] = 86,
+    .interrupt_lines[86] = 87,
+    .interrupt_lines[87] = 88,
+    .interrupt_lines[88] = 89,
+    .interrupt_lines[89] = 90,
+    .interrupt_lines[90] = 91,
+    .interrupt_lines[91] = 92,
+    .interrupt_lines[92] = 93,
+    .interrupt_lines[93] = 94,
+    .interrupt_lines[94] = 95,
+    .interrupt_lines[95] = 96,
+    .interrupt_lines[96] = 97,
+    .interrupt_lines[97] = 98,
+    .interrupt_lines[98] = 99,
+    .interrupt_lines[99] = 100,
+    .interrupt_lines[100] = 101,
+    .interrupt_lines[101] = 102,
+    .interrupt_lines[102] = 103,
+    .interrupt_lines[103] = 104,
+    .interrupt_lines[104] = 105,
+    .interrupt_lines[105] = 106,
+    .interrupt_lines[106] = 107,
+    .interrupt_lines[107] = 108,
+    .interrupt_lines[108] = 109,
+    .interrupt_lines[109] = 110,
+    .interrupt_lines[110] = 111,
+    .interrupt_lines[111] = 112,
+    .interrupt_lines[112] = 113,
+    .interrupt_lines[113] = 114,
+    .interrupt_lines[114] = 115,
+    .interrupt_lines[115] = 116,
+    .interrupt_lines[116] = 117,
+    .interrupt_lines[117] = 118,
+    .interrupt_lines[118] = 119,
+    .interrupt_lines[119] = 120,
+    .interrupt_lines[120] = 121,
+    .interrupt_lines[121] = 122,
+    .interrupt_lines[122] = 123,
+    .interrupt_lines[123] = 124,
+    .interrupt_lines[124] = 125,
+    .interrupt_lines[125] = 126,
+    .interrupt_lines[126] = 127,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .vtable = &__metal_driver_vtable_sifive_test0,
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+    .base = 16384UL,
+    .size = 4096UL,
+};
+
+/* From cache_controller@2010000 */
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
+    .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2,
+    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
+};
+
+
+#define __METAL_DT_MAX_MEMORIES 7
+
+asm (".weak __metal_memory_table");
+struct metal_memory *__metal_memory_table[] = {
+					&__metal_dt_mem_dtim_1000000,
+					&__metal_dt_mem_itim_1800000,
+					&__metal_dt_mem_itim_1808000,
+					&__metal_dt_mem_itim_1810000,
+					&__metal_dt_mem_itim_1818000,
+					&__metal_dt_mem_itim_1820000,
+					&__metal_dt_mem_memory_80000000};
+
+/* From clint@2000000 */
+#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller)
+
+#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller)
+
+#define __METAL_DT_MAX_HARTS 5
+
+asm (".weak __metal_cpu_table");
+struct __metal_driver_cpu *__metal_cpu_table[] = {
+					&__metal_dt_cpu_0,
+					&__metal_dt_cpu_1,
+					&__metal_dt_cpu_2,
+					&__metal_dt_cpu_3,
+					&__metal_dt_cpu_4};
+
+/* From interrupt_controller@c000000 */
+#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
+
+#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
+
+/* From pmp@0 */
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+
+/* From global_external_interrupts */
+#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc)
+
+#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc)
+
+#define __MEE_DT_MAX_GPIOS 0
+
+asm (".weak __metal_gpio_table");
+struct __metal_driver_sifive_gpio0 *__metal_gpio_table[] = {
+					NULL };
+#define __METAL_DT_MAX_BUTTONS 0
+
+asm (".weak __metal_button_table");
+struct __metal_driver_sifive_gpio_button *__metal_button_table[] = {
+					NULL };
+#define __METAL_DT_MAX_LEDS 0
+
+asm (".weak __metal_led_table");
+struct __metal_driver_sifive_gpio_led *__metal_led_table[] = {
+					NULL };
+#define __METAL_DT_MAX_SWITCHES 0
+
+asm (".weak __metal_switch_table");
+struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = {
+					NULL };
+#define __METAL_DT_MAX_SPIS 0
+
+asm (".weak __metal_spi_table");
+struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
+					NULL };
+/* From teststatus@4000 */
+#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown)
+
+#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
+
+
+#endif /* ! __METAL_MACHINE_MACROS */
+#endif /* COREIP_U54MC_RTL__METAL_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
new file mode 100644
index 0000000..7b1cf8e
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
@@ -0,0 +1,227 @@
+OUTPUT_ARCH("riscv")
+
+ENTRY(_enter)
+
+MEMORY
+{
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000
+	itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000
+}
+
+PHDRS
+{
+	flash PT_LOAD;
+	ram_init PT_LOAD;
+	itim_init PT_LOAD;
+	ram PT_LOAD;
+	itim PT_LOAD;
+}
+
+SECTIONS
+{
+	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
+	PROVIDE(__stack_size = __stack_size);
+	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+
+
+	.init 		:
+	{
+		KEEP (*(.text.metal.init.enter))
+		KEEP (*(SORT_NONE(.init)))
+		KEEP (*(.text.libgloss.start))
+	} >ram AT>ram :ram
+
+
+
+
+	.fini 		:
+	{
+		KEEP (*(SORT_NONE(.fini)))
+	} >ram AT>ram :ram
+
+
+	PROVIDE (__etext = .);
+	PROVIDE (_etext = .);
+	PROVIDE (etext = .);
+
+
+
+
+	. = ALIGN(4);
+
+
+	.preinit_array 		:
+	{
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.init_array 		:
+	{
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+		PROVIDE_HIDDEN (__init_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.finit_array 		:
+	{
+		PROVIDE_HIDDEN (__finit_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+		PROVIDE_HIDDEN (__finit_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.ctors 		:
+	{
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >ram AT>ram :ram
+
+
+	.dtors 		:
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >ram AT>ram :ram
+
+
+	.litimalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_itim_source_start = . );
+	} >ram AT>ram :ram
+
+
+	.ditimalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_itim_target_start = . );
+	} >itim AT>ram :itim_init
+
+
+	.itim 		:
+	{
+		*(.itim .itim.*)
+	} >itim AT>ram :itim_init
+
+
+	. = ALIGN(8);
+	PROVIDE( metal_segment_itim_target_end = . );
+	.text 		:
+	{
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.*)
+		*(.gnu.linkonce.t.*)
+	} >ram AT>ram :ram
+
+
+	.lalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( _data_lma = . );
+		PROVIDE( metal_segment_data_source_start = . );
+	} >ram AT>ram :ram
+
+
+	.dalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_data_target_start = . );
+	} >ram AT>ram :ram_init
+
+
+	.data 		:
+	{
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+	} >ram AT>ram :ram_init
+
+
+	. = ALIGN(4);
+	PROVIDE( _edata = . );
+	PROVIDE( edata = . );
+	PROVIDE( metal_segment_data_target_end = . );
+	PROVIDE( _fbss = . );
+	PROVIDE( __bss_start = . );
+	PROVIDE( metal_segment_bss_target_start = . );
+
+
+	.bss 		:
+	{
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(4);
+	} >ram AT>ram :ram
+
+
+	. = ALIGN(8);
+	PROVIDE( _end = . );
+	PROVIDE( end = . );
+	PROVIDE( metal_segment_bss_target_end = . );
+
+
+	.stack :
+	{
+		PROVIDE(metal_segment_stack_begin = .);
+		. = __stack_size;
+		PROVIDE( _sp = . );
+		. = __stack_size;
+		. = __stack_size;
+		. = __stack_size;
+		. = __stack_size;
+		PROVIDE(metal_segment_stack_end = .);
+	} >ram AT>ram :ram
+
+
+	.heap :
+	{
+		PROVIDE( metal_segment_heap_target_start = . );
+		. = __heap_size;
+		PROVIDE( metal_segment_heap_target_end = . );
+		PROVIDE( _heap_end = . );
+	} >ram AT>ram :ram
+
+
+}
+
diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
new file mode 100644
index 0000000..0d12f67
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
@@ -0,0 +1,230 @@
+OUTPUT_ARCH("riscv")
+
+ENTRY(_enter)
+
+MEMORY
+{
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000
+	itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000
+}
+
+PHDRS
+{
+	flash PT_LOAD;
+	ram_init PT_LOAD;
+	itim_init PT_LOAD;
+	ram PT_LOAD;
+	itim PT_LOAD;
+}
+
+SECTIONS
+{
+	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
+	PROVIDE(__stack_size = __stack_size);
+	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+
+
+	.init 		:
+	{
+		KEEP (*(.text.metal.init.enter))
+		KEEP (*(SORT_NONE(.init)))
+		KEEP (*(.text.libgloss.start))
+	} >ram AT>ram :ram
+
+
+	.text 		:
+	{
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.*)
+		*(.gnu.linkonce.t.*)
+	} >ram AT>ram :ram
+
+
+	.fini 		:
+	{
+		KEEP (*(SORT_NONE(.fini)))
+	} >ram AT>ram :ram
+
+
+	PROVIDE (__etext = .);
+	PROVIDE (_etext = .);
+	PROVIDE (etext = .);
+
+
+	.rodata 		:
+	{
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+	} >ram AT>ram :ram
+
+
+	. = ALIGN(4);
+
+
+	.preinit_array 		:
+	{
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.init_array 		:
+	{
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+		PROVIDE_HIDDEN (__init_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.finit_array 		:
+	{
+		PROVIDE_HIDDEN (__finit_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+		PROVIDE_HIDDEN (__finit_array_end = .);
+	} >ram AT>ram :ram
+
+
+	.ctors 		:
+	{
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >ram AT>ram :ram
+
+
+	.dtors 		:
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >ram AT>ram :ram
+
+
+	.litimalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_itim_source_start = . );
+	} >ram AT>ram :ram
+
+
+	.ditimalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_itim_target_start = . );
+	} >itim AT>ram :itim_init
+
+
+	.itim 		:
+	{
+		*(.itim .itim.*)
+	} >itim AT>ram :itim_init
+
+
+	. = ALIGN(8);
+	PROVIDE( metal_segment_itim_target_end = . );
+
+
+	.lalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( _data_lma = . );
+		PROVIDE( metal_segment_data_source_start = . );
+	} >ram AT>ram :ram
+
+
+	.dalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( metal_segment_data_target_start = . );
+	} >ram AT>ram :ram_init
+
+
+	.data 		:
+	{
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+	} >ram AT>ram :ram_init
+
+
+	. = ALIGN(4);
+	PROVIDE( _edata = . );
+	PROVIDE( edata = . );
+	PROVIDE( metal_segment_data_target_end = . );
+	PROVIDE( _fbss = . );
+	PROVIDE( __bss_start = . );
+	PROVIDE( metal_segment_bss_target_start = . );
+
+
+	.bss 		:
+	{
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(4);
+	} >ram AT>ram :ram
+
+
+	. = ALIGN(8);
+	PROVIDE( _end = . );
+	PROVIDE( end = . );
+	PROVIDE( metal_segment_bss_target_end = . );
+
+
+	.stack :
+	{
+		PROVIDE(metal_segment_stack_begin = .);
+		. = __stack_size;
+		PROVIDE( _sp = . );
+		. = __stack_size;
+		. = __stack_size;
+		. = __stack_size;
+		. = __stack_size;
+		PROVIDE(metal_segment_stack_end = .);
+	} >ram AT>ram :ram
+
+
+	.heap :
+	{
+		PROVIDE( metal_segment_heap_target_start = . );
+		. = __heap_size;
+		PROVIDE( metal_segment_heap_target_end = . );
+		PROVIDE( _heap_end = . );
+	} >ram AT>ram :ram
+
+
+}
+
diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk
new file mode 100644
index 0000000..0fe5f84
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/settings.mk
@@ -0,0 +1,7 @@
+RISCV_ARCH=rv64imac
+RISCV_ABI=lp64
+RISCV_CMODEL=medany
+
+COREIP_MEM_WIDTH=128
+
+TARGET_TAGS=rtl