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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-28 13:44:19 -0700
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-03-29 10:42:08 -0700
commitc8c61bea228977ca652f831b774169814ce2a553 (patch)
tree6258b8190e53aa8c99363f124c655c470297cd01 /bsp/env/coreplexip-e21-arty/dhrystone.lds
parente582766d596dcaa303634c121638b8f614ffd4c7 (diff)
Update Metal to v201903
- Enable RX on the sifive,uart0 driver - Enable FP support in crt0.S - Mark the FE310 PLL config table const Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/env/coreplexip-e21-arty/dhrystone.lds')
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