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| author | Megan Wachs <megan@sifive.com> | 2017-05-04 05:46:05 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-05-04 05:46:05 -0700 |
| commit | 4d5cbec9118cbedf2d4ae5b54acaa22862245a4c (patch) | |
| tree | bb197ca9ef8f9265a79485f3a13e4e921a0ff93b /bsp/env/coreplexip-e31-arty/openocd.cfg | |
| parent | 3a01ac1b7c0e72c04679f0cd6552c4ff0b308863 (diff) | |
Update SDK For E31/E51 Coreplex IP Evaluation
Diffstat (limited to 'bsp/env/coreplexip-e31-arty/openocd.cfg')
| -rw-r--r-- | bsp/env/coreplexip-e31-arty/openocd.cfg | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/bsp/env/coreplexip-e31-arty/openocd.cfg b/bsp/env/coreplexip-e31-arty/openocd.cfg new file mode 100644 index 0000000..0481a72 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off +echo "Ready for Remote Connections" |