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| author | Scott Johnson <scottj@sifive.com> | 2016-12-06 11:00:55 -0800 |
|---|---|---|
| committer | Scott Johnson <scottj@sifive.com> | 2016-12-06 11:00:55 -0800 |
| commit | 697fadd2946dafaf84bc70413ba26116e872bc5f (patch) | |
| tree | 23c461dc86a5bec284d0b12b27e7b7704c288355 /bsp/env/coreplexip-e51-arty/dhrystone.lds | |
| parent | 66c882e380656d45dec9019255d7a1106bb1f5ff (diff) | |
Enable FPU in MSTATUS CSR during init
This way, chips with FPU can run FPU instructions without taking
exceptions.
I've confirmed that dhrystone still runs successfully even on chips
with no FPU.
Diffstat (limited to 'bsp/env/coreplexip-e51-arty/dhrystone.lds')
0 files changed, 0 insertions, 0 deletions