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authorMegan Wachs <megan@sifive.com>2017-05-04 05:50:00 -0700
committerGitHub <noreply@github.com>2017-05-04 05:49:59 -0700
commit5b2498467020616de013fd557b6a1e685544ee18 (patch)
treebb197ca9ef8f9265a79485f3a13e4e921a0ff93b /bsp/env/freedom-e300-hifive1
parent3a01ac1b7c0e72c04679f0cd6552c4ff0b308863 (diff)
parent4d5cbec9118cbedf2d4ae5b54acaa22862245a4c (diff)
Merge pull request #54 from sifive/tag_v20170504
Update SDK For E31/E51 Coreplex IP Evaluation
Diffstat (limited to 'bsp/env/freedom-e300-hifive1')
-rw-r--r--bsp/env/freedom-e300-hifive1/init.c4
-rw-r--r--bsp/env/freedom-e300-hifive1/platform.h66
-rw-r--r--bsp/env/freedom-e300-hifive1/settings.mk3
3 files changed, 38 insertions, 35 deletions
diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c
index de046cc..621a6e2 100644
--- a/bsp/env/freedom-e300-hifive1/init.c
+++ b/bsp/env/freedom-e300-hifive1/init.c
@@ -10,14 +10,14 @@ extern void trap_entry();
static unsigned long mtime_lo(void)
{
- return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME);
+ return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
}
#ifdef __riscv32
static uint32_t mtime_hi(void)
{
- return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4);
+ return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
}
uint64_t get_timer_value()
diff --git a/bsp/env/freedom-e300-hifive1/platform.h b/bsp/env/freedom-e300-hifive1/platform.h
index 63efc9e..806fcfc 100644
--- a/bsp/env/freedom-e300-hifive1/platform.h
+++ b/bsp/env/freedom-e300-hifive1/platform.h
@@ -23,25 +23,25 @@
*****************************************************************************/
// Memory map
-#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
-#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
-#define OTP_MMAP_ADDR _AC(0x00020000,UL)
-#define CLINT_BASE_ADDR _AC(0x02000000,UL)
-#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
-#define AON_BASE_ADDR _AC(0x10000000,UL)
-#define PRCI_BASE_ADDR _AC(0x10008000,UL)
-#define OTP_BASE_ADDR _AC(0x10010000,UL)
-#define GPIO_BASE_ADDR _AC(0x10012000,UL)
-#define UART0_BASE_ADDR _AC(0x10013000,UL)
-#define SPI0_BASE_ADDR _AC(0x10014000,UL)
-#define PWM0_BASE_ADDR _AC(0x10015000,UL)
-#define UART1_BASE_ADDR _AC(0x10023000,UL)
-#define SPI1_BASE_ADDR _AC(0x10024000,UL)
-#define PWM1_BASE_ADDR _AC(0x10025000,UL)
-#define SPI2_BASE_ADDR _AC(0x10034000,UL)
-#define PWM2_BASE_ADDR _AC(0x10035000,UL)
-#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
-#define MEM_BASE_ADDR _AC(0x80000000,UL)
+#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
+#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
+#define OTP_MEM_ADDR _AC(0x00020000,UL)
+#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
+#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
+#define AON_CTRL_ADDR _AC(0x10000000,UL)
+#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
+#define OTP_CTRL_ADDR _AC(0x10010000,UL)
+#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
+#define UART0_CTRL_ADDR _AC(0x10013000,UL)
+#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
+#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
+#define UART1_CTRL_ADDR _AC(0x10023000,UL)
+#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
+#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
+#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
+#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
+#define SPI0_MEM_ADDR _AC(0x20000000,UL)
+#define MEM_CTRL_ADDR _AC(0x80000000,UL)
// IOF masks
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
@@ -100,20 +100,20 @@
// Helper functions
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
-#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
-#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
-#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
-#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
-#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
-#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
-#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
-#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
+#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
+#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
+#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
+#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
+#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
+#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
+#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
+#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
// Misc
diff --git a/bsp/env/freedom-e300-hifive1/settings.mk b/bsp/env/freedom-e300-hifive1/settings.mk
new file mode 100644
index 0000000..230fccc
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/settings.mk
@@ -0,0 +1,3 @@
+# Describes the CPU on this board to the rest of the SDK.
+RISCV_ARCH := rv32imac
+RISCV_ABI := ilp32