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authorPalmer Dabbelt <palmer@dabbelt.com>2017-06-13 15:14:38 -0700
committerPalmer Dabbelt <palmer@dabbelt.com>2017-06-14 08:53:39 -0700
commitb22853b2f4bdd1ed31d601ebd331083d67d40f11 (patch)
treeb93f00a0566675d6c38152d5097acf30381a3e04 /bsp/env
parentc08ce47e3829d8070ba7b4813cfc7a9a48c35a3c (diff)
Add a SMP example
This just prints "hello world" on two cores. It contains an example of how to initialize a multi-core system using IPIs, and a simple spin lock.
Diffstat (limited to 'bsp/env')
-rw-r--r--bsp/env/start.S51
1 files changed, 50 insertions, 1 deletions
diff --git a/bsp/env/start.S b/bsp/env/start.S
index e86105b..4e9f665 100644
--- a/bsp/env/start.S
+++ b/bsp/env/start.S
@@ -1,18 +1,27 @@
// See LICENSE for license details.
+#include <sifive/smp.h>
-// See LICENSE for license details.
+/* This is defined in sifive/platform.h, but that can't be included from
+ * assembly. */
+#define CLINT_CTRL_ADDR 0x02000000
.section .init
.globl _start
.type _start,@function
_start:
+ .cfi_startproc
+ .cfi_undefined ra
.option push
.option norelax
la gp, __global_pointer$
.option pop
la sp, _sp
+#if defined(ENABLE_SMP)
+ smp_pause(t0, t1)
+#endif
+
/* Load data section */
la a0, _data_lma
la a1, _data
@@ -52,11 +61,51 @@ _start:
1:
#endif
+#if defined(ENABLE_SMP)
+ smp_resume(t0, t1)
+
+ csrr a0, mhartid
+ bnez a0, 2f
+#endif
+
+ auipc ra, 0
+ addi sp, sp, -16
+#if __riscv_xlen == 32
+ sw ra, 8(sp)
+#else
+ sd ra, 8(sp)
+#endif
+
/* argc = argv = 0 */
li a0, 0
li a1, 0
call main
tail exit
+1:
+ j 1b
+
+#if defined(ENABLE_SMP)
+2:
+ la t0, trap_entry
+ csrw mtvec, t0
+
+ csrr a0, mhartid
+ la t1, _sp
+ slli t0, a0, 10
+ sub sp, t1, t0
+
+ auipc ra, 0
+ addi sp, sp, -16
+#if __riscv_xlen == 32
+ sw ra, 8(sp)
+#else
+ sd ra, 8(sp)
+#endif
+
+ call secondary_main
+ tail exit
1:
j 1b
+#endif
+ .cfi_endproc