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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-07 09:27:31 -0800
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-03-07 09:27:31 -0800
commitf695df295da82c8ef801906ad8b00b0e8afa7502 (patch)
treecb0a9be10abe32a014baf2fa7903b9070461a7ad /bsp/env
parent90ab2c8561eb532b382206c8bf3ec1af74f18257 (diff)
Remove legacy BSP
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/env')
-rw-r--r--bsp/env/common.mk56
-rw-r--r--bsp/env/coreip-e2-arty/flash.lds161
-rw-r--r--bsp/env/coreip-e2-arty/init.c98
l---------bsp/env/coreip-e2-arty/openocd.cfg1
-rw-r--r--bsp/env/coreip-e2-arty/platform.h98
l---------bsp/env/coreip-e2-arty/settings.mk1
-rw-r--r--bsp/env/coreip-e2-arty/tim-split.lds157
-rw-r--r--bsp/env/coreip-e2-arty/tim.lds161
-rw-r--r--bsp/env/coreplexip-arty.h102
-rw-r--r--bsp/env/coreplexip-e31-arty/dhrystone.lds157
-rw-r--r--bsp/env/coreplexip-e31-arty/flash.lds161
-rw-r--r--bsp/env/coreplexip-e31-arty/init.c122
-rw-r--r--bsp/env/coreplexip-e31-arty/openocd.cfg31
-rw-r--r--bsp/env/coreplexip-e31-arty/platform.h100
-rw-r--r--bsp/env/coreplexip-e31-arty/scratchpad.lds161
-rw-r--r--bsp/env/coreplexip-e31-arty/settings.mk3
l---------bsp/env/coreplexip-e51-arty/dhrystone.lds1
l---------bsp/env/coreplexip-e51-arty/flash.lds1
l---------bsp/env/coreplexip-e51-arty/init.c1
l---------bsp/env/coreplexip-e51-arty/openocd.cfg1
l---------bsp/env/coreplexip-e51-arty/platform.h1
l---------bsp/env/coreplexip-e51-arty/scratchpad.lds1
-rw-r--r--bsp/env/coreplexip-e51-arty/settings.mk3
-rw-r--r--bsp/env/encoding.h1313
-rw-r--r--bsp/env/entry.S98
l---------bsp/env/freedom-e300-arty/flash.lds1
-rw-r--r--bsp/env/freedom-e300-arty/init.c87
-rw-r--r--bsp/env/freedom-e300-arty/openocd.cfg30
-rw-r--r--bsp/env/freedom-e300-arty/platform.h124
-rw-r--r--bsp/env/freedom-e300-arty/settings.mk3
-rw-r--r--bsp/env/freedom-e300-hifive1/dhrystone.lds157
-rw-r--r--bsp/env/freedom-e300-hifive1/flash.lds161
-rw-r--r--bsp/env/freedom-e300-hifive1/init.c238
-rw-r--r--bsp/env/freedom-e300-hifive1/openocd.cfg34
-rw-r--r--bsp/env/freedom-e300-hifive1/platform.h133
-rw-r--r--bsp/env/freedom-e300-hifive1/settings.mk3
-rw-r--r--bsp/env/hifive1.h81
-rw-r--r--bsp/env/start.S112
-rw-r--r--bsp/env/ventry.S288
39 files changed, 0 insertions, 4442 deletions
diff --git a/bsp/env/common.mk b/bsp/env/common.mk
deleted file mode 100644
index 74939a5..0000000
--- a/bsp/env/common.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-# See LICENSE for license details.
-
-ifndef _SIFIVE_MK_COMMON
-_SIFIVE_MK_COMMON := # defined
-
-.PHONY: all
-all: $(TARGET)
-
-include $(BSP_BASE)/libwrap/libwrap.mk
-
-ENV_DIR = $(BSP_BASE)/env
-PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
-
-ASM_SRCS += $(ENV_DIR)/start.S
-ASM_SRCS += $(ENV_DIR)/entry.S
-C_SRCS += $(PLATFORM_DIR)/init.c
-
-LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds
-
-INCLUDES += -I$(BSP_BASE)/include
-INCLUDES += -I$(BSP_BASE)/drivers/
-INCLUDES += -I$(ENV_DIR)
-INCLUDES += -I$(PLATFORM_DIR)
-
-TOOL_DIR = $(BSP_BASE)/../toolchain/bin
-
-LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles
-LDFLAGS += -L$(ENV_DIR) --specs=nano.specs
-
-ASM_OBJS := $(ASM_SRCS:.S=.o)
-C_OBJS := $(C_SRCS:.c=.o)
-
-LINK_OBJS += $(ASM_OBJS) $(C_OBJS)
-LINK_DEPS += $(LINKER_SCRIPT)
-
-CLEAN_OBJS += $(TARGET) $(LINK_OBJS)
-
-CFLAGS += -g
-CFLAGS += -march=$(RISCV_ARCH)
-CFLAGS += -mabi=$(RISCV_ABI)
-CFLAGS += -mcmodel=medany
-
-$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
- $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS)
-
-$(ASM_OBJS): %.o: %.S $(HEADERS)
- $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
-
-$(C_OBJS): %.o: %.c $(HEADERS)
- $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $<
-
-.PHONY: clean
-clean:
- rm -f $(CLEAN_OBJS)
-
-endif # _SIFIVE_MK_COMMON
diff --git a/bsp/env/coreip-e2-arty/flash.lds b/bsp/env/coreip-e2-arty/flash.lds
deleted file mode 100644
index 2d5eb01..0000000
--- a/bsp/env/coreip-e2-arty/flash.lds
+++ /dev/null
@@ -1,161 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash :flash
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >flash AT>flash :flash
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash :flash
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- } >flash AT>flash :flash
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash :flash
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash :flash
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash :flash
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >flash AT>flash :flash
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >flash AT>flash :flash
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >flash AT>flash :flash
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>flash :ram_init
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>flash :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/coreip-e2-arty/init.c b/bsp/env/coreip-e2-arty/init.c
deleted file mode 100644
index 3a4c77c..0000000
--- a/bsp/env/coreip-e2-arty/init.c
+++ /dev/null
@@ -1,98 +0,0 @@
-//See LICENSE for license details.
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "platform.h"
-#include "encoding.h"
-
-#define CPU_FREQ 32000000
-#define XSTR(x) #x
-#define STR(x) XSTR(x)
-
-extern int main(int argc, char** argv);
-
-unsigned long get_cpu_freq()
-{
- return CPU_FREQ;
-}
-
-unsigned long get_timer_freq()
-{
- return get_cpu_freq();
-}
-
-uint64_t get_timer_value()
-{
-#if __riscv_xlen == 32
- while (1) {
- uint32_t hi = read_csr(mcycleh);
- uint32_t lo = read_csr(mcycle);
- if (hi == read_csr(mcycleh))
- return ((uint64_t)hi << 32) | lo;
- }
-#else
- return read_csr(mcycle);
-#endif
-}
-
-static void uart_init(size_t baud_rate)
-{
- UART0_REG(UART_REG_DIV) = (get_cpu_freq() ) / baud_rate - 1;
- UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-
-typedef void (*interrupt_function_ptr_t) (void);
-interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64)));
-
-
-void trap_entry(void) __attribute__((interrupt, aligned(64)));
-void trap_entry(void)
-{
- unsigned long mcause = read_csr(mcause);
- unsigned long mepc = read_csr(mepc);
- if (mcause & MCAUSE_INT) {
- localISR[mcause & MCAUSE_CAUSE] ();
- } else {
- while(1);
- }
-}
-
-#ifdef CLIC_DIRECT
-#else
-void default_handler(void)__attribute__((interrupt));;
-#endif
-void default_handler(void)
-{
- puts("default handler\n");
- while(1);
-}
-
-void _init()
-{
-#ifndef NO_INIT
- uart_init(115200);
-
- puts("core freq at " STR(CPU_FREQ) " Hz\n");
-
-//initialize vector table
- int i=0;
- while(i<CLIC_NUM_INTERRUPTS) {
- localISR[i++] = default_handler;
- }
-
- write_csr(mtvt, localISR);
-
-#ifdef CLIC_DIRECT
- write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
-#else
- write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC_VECT));
-#endif
-
-#endif
-}
-
-void _fini()
-{
-}
diff --git a/bsp/env/coreip-e2-arty/openocd.cfg b/bsp/env/coreip-e2-arty/openocd.cfg
deleted file mode 120000
index 2f4de8d..0000000
--- a/bsp/env/coreip-e2-arty/openocd.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/openocd.cfg \ No newline at end of file
diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
deleted file mode 100644
index 0ce0484..0000000
--- a/bsp/env/coreip-e2-arty/platform.h
+++ /dev/null
@@ -1,98 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-// Some things missing from the official encoding.h
-
-#if __riscv_xlen == 32
-#define MCAUSE_INT 0x80000000UL
-#define MCAUSE_CAUSE 0x000003FFUL
-#else
-#define MCAUSE_INT 0x8000000000000000UL
-#define MCAUSE_CAUSE 0x00000000000003FFUL
-#endif
-
-#define MTVEC_DIRECT 0X00
-#define MTVEC_VECTORED 0x01
-#define MTVEC_CLIC 0x02
-#define MTVEC_CLIC_VECT 0X03
-
-
-#include "sifive/const.h"
-#include "sifive/devices/gpio.h"
-#include "sifive/devices/clint.h"
-#include "sifive/devices/clic.h"
-#include "sifive/devices/pwm.h"
-#include "sifive/devices/spi.h"
-#include "sifive/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// Memory map
-#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define CLIC_HART0_ADDR _AC(0x02800000,UL)
-#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
-#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
-#define RAM_MEM_ADDR _AC(0x80000000,UL)
-#define RAM_MEM_SIZE _AC(0x10000,UL)
-#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
-#define SPI0_MEM_ADDR _AC(0x40000000,UL)
-#define SPI0_MEM_SIZE _AC(0x20000000,UL)
-#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
-#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
-//#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
-#define UART0_CTRL_ADDR _AC(0x20000000,UL)
-
-// IOF masks
-
-// Interrupt numbers
-#define RESERVED_INT_BASE 0
-#define UART0_INT_BASE 1
-#define EXTERNAL_INT_BASE 2
-#define SPI0_INT_BASE 6
-#define GPIO_INT_BASE 7
-#define PWM0_INT_BASE 23
-
-// Helper functions
-#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
-#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
-#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
-#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define CLIC0_REG(offset) _REG32(CLIC_HART0_ADDR, offset)
-#define CLIC0_REG8(offset) (*(volatile uint8_t *)((CLIC_HART0_ADDR) + (offset)))
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define CLIC0_REG64(offset) _REG64(CLIC_HART0_ADDR, offset)
-#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
-#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
-#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
-#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
-
-// Misc
-
-#define NUM_GPIO 16
-
-#define CLIC_NUM_INTERRUPTS 28 + 16
-
-#ifdef E20
- #define CLIC_CONFIG_BITS 2
-#else
- #define CLIC_CONFIG_BITS 4
-#endif
-
-#define HAS_BOARD_BUTTONS
-
-#include "coreplexip-arty.h"
-
-unsigned long get_cpu_freq(void);
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/coreip-e2-arty/settings.mk b/bsp/env/coreip-e2-arty/settings.mk
deleted file mode 120000
index 2b2a962..0000000
--- a/bsp/env/coreip-e2-arty/settings.mk
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/settings.mk \ No newline at end of file
diff --git a/bsp/env/coreip-e2-arty/tim-split.lds b/bsp/env/coreip-e2-arty/tim-split.lds
deleted file mode 100644
index eab4bd3..0000000
--- a/bsp/env/coreip-e2-arty/tim-split.lds
+++ /dev/null
@@ -1,157 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- flash (rxai!w) : ORIGIN = 0x80008000, LENGTH = 32K
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32K
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash :flash
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >flash AT>flash :flash
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash :flash
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash :flash
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash :flash
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash :flash
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >flash AT>flash :flash
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >flash AT>flash :flash
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >flash AT>flash :flash
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>flash :ram_init
-
- .data :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>flash :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/coreip-e2-arty/tim.lds b/bsp/env/coreip-e2-arty/tim.lds
deleted file mode 100644
index 7dfb36b..0000000
--- a/bsp/env/coreip-e2-arty/tim.lds
+++ /dev/null
@@ -1,161 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
-}
-
-PHDRS
-{
- ram PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >ram AT>ram :ram
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >ram AT>ram :ram
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >ram AT>ram :ram
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- } >ram AT>ram :ram
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >ram AT>ram :ram
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >ram AT>ram :ram
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >ram AT>ram :ram
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >ram AT>ram :ram
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >ram AT>ram :ram
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >ram AT>ram :ram
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>ram :ram_init
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>ram :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack :
- {
- . = ALIGN(8);
- . += __stack_size;
- PROVIDE( _sp = . );
- PROVIDE( _heap_end = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/coreplexip-arty.h b/bsp/env/coreplexip-arty.h
deleted file mode 100644
index eedcaa5..0000000
--- a/bsp/env/coreplexip-arty.h
+++ /dev/null
@@ -1,102 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_COREPLEXIP_ARTY_H
-#define _SIFIVE_COREPLEXIP_ARTY_H
-
-#include <stdint.h>
-
-/****************************************************************************
- * GPIO Connections
- *****************************************************************************/
-
-// These are the GPIO bit offsets for the directly driven
-// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit.
-// Additional RGB LEDs are driven by the 3 PWM outputs.
-
-#define RED_LED_OFFSET 0
-#define GREEN_LED_OFFSET 1
-#define BLUE_LED_OFFSET 2
-
-// Switch 3 is used as a GPIO input. (Switch 0 is used to set
-// the reset vector, the other switches are unused).
-
-#define SW_3_OFFSET 3
-
-// These are the buttons which are mapped as inputs.
-
-#define HAS_BOARD_BUTTONS
-
-#define BUTTON_0_OFFSET 4
-#define BUTTON_1_OFFSET 5
-#define BUTTON_2_OFFSET 6
-#define BUTTON_3_OFFSET 7
-
-// These are the bit offsets for the different GPIO pins
-// mapped onto the PMOD A header.
-
-#define JA_0_OFFSET 8
-#define JA_1_OFFSET 9
-#define JA_2_OFFSET 10
-#define JA_3_OFFSET 11
-#define JA_4_OFFSET 12
-#define JA_5_OFFSET 13
-#define JA_6_OFFSET 14
-#define JA_7_OFFSET 15
-
-// The below gives a mapping between global interrupt
-// sources and their number. Note that on the coreplex
-// deliverable, the io_global_interrupts go directly into
-// the PLIC. The evaluation image on the FPGA mimics a
-// system with peripheral devices which are driving the
-// global interrupt lines.
-// So, on this image, in order to get an interrupt from
-// e.g. pressing BUTTON_0:
-// 1) Steps which are external to the delivery coreplex:
-// a) The corresponding GPIO pin must be configured as in input
-// b) The "interrupt on fall" bit must be set for the GPIO pin
-// 2) Steps which would also need to be performed for the delivery coreplex:
-// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC.
-// b) The external interrupt bit must be enabled in MSTATUS
-// c) Interrupts must be enabled globally in the core.
-
-// Any of the above GPIO pins can be used as global interrupt
-// sources by adding their offset to the INT_GPIO_BASE.
-// For example, the buttons are shown here:
-
-#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET)
-#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET)
-#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET)
-#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET)
-
-// In addition, the Switches are mapped directly to
-// the PLIC (without going through the GPIO Peripheral).
-
-#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0)
-#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1)
-#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2)
-#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3)
-
-// This gives the mapping from inputs to LOCAL interrupts.
-
-#define LOCAL_INT_SW_0 0
-#define LOCAL_INT_SW_1 1
-#define LOCAL_INT_SW_2 2
-#define LOCAL_INT_SW_3 3
-#define LOCAL_INT_BTN_0 4
-#define LOCAL_INT_BTN_1 5
-#define LOCAL_INT_BTN_2 6
-#define LOCAL_INT_BTN_3 7
-#define LOCAL_INT_JA_0 8
-#define LOCAL_INT_JA_1 9
-#define LOCAL_INT_JA_2 10
-#define LOCAL_INT_JA_3 11
-#define LOCAL_INT_JA_4 12
-#define LOCAL_INT_JA_5 13
-#define LOCAL_INT_JA_6 14
-#define LOCAL_INT_JA_7 15
-
-#define RTC_FREQ 32768
-
-void write_hex(int fd, unsigned long int hex);
-
-#endif /* _SIFIVE_COREPLEXIP_ARTY_H */
diff --git a/bsp/env/coreplexip-e31-arty/dhrystone.lds b/bsp/env/coreplexip-e31-arty/dhrystone.lds
deleted file mode 100644
index 8f6527b..0000000
--- a/bsp/env/coreplexip-e31-arty/dhrystone.lds
+++ /dev/null
@@ -1,157 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash :flash
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >flash AT>flash :flash
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash :flash
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash :flash
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash :flash
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash :flash
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >flash AT>flash :flash
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >flash AT>flash :flash
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >flash AT>flash :flash
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>flash :ram_init
-
- .data :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>flash :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/coreplexip-e31-arty/flash.lds b/bsp/env/coreplexip-e31-arty/flash.lds
deleted file mode 100644
index 590c5b6..0000000
--- a/bsp/env/coreplexip-e31-arty/flash.lds
+++ /dev/null
@@ -1,161 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash :flash
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >flash AT>flash :flash
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash :flash
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- } >flash AT>flash :flash
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash :flash
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash :flash
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash :flash
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >flash AT>flash :flash
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >flash AT>flash :flash
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >flash AT>flash :flash
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>flash :ram_init
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>flash :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/coreplexip-e31-arty/init.c b/bsp/env/coreplexip-e31-arty/init.c
deleted file mode 100644
index 1f8b679..0000000
--- a/bsp/env/coreplexip-e31-arty/init.c
+++ /dev/null
@@ -1,122 +0,0 @@
-//See LICENSE for license details.
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "platform.h"
-#include "encoding.h"
-
-#define CPU_FREQ 65000000
-#define XSTR(x) #x
-#define STR(x) XSTR(x)
-
-#ifndef VECT_IRQ
- #define TRAP_ENTRY trap_entry
-#else
- #define TRAP_ENTRY vtrap_entry
-#endif
-
-extern int main(int argc, char** argv);
-extern void TRAP_ENTRY();
-
-unsigned long get_cpu_freq()
-{
- return CPU_FREQ;
-}
-
-unsigned long get_timer_freq()
-{
- return get_cpu_freq();
-}
-
-uint64_t get_timer_value()
-{
-#if __riscv_xlen == 32
- while (1) {
- uint32_t hi = read_csr(mcycleh);
- uint32_t lo = read_csr(mcycle);
- if (hi == read_csr(mcycleh))
- return ((uint64_t)hi << 32) | lo;
- }
-#else
- return read_csr(mcycle);
-#endif
-}
-
-static void uart_init(size_t baud_rate)
-{
- UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1;
- UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-#ifdef USE_LOCAL_ISR
-typedef void (*my_interrupt_function_ptr_t) (void);
-extern my_interrupt_function_ptr_t localISR[];
-#endif
-
-#ifndef VECT_IRQ
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline));
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
- if (0){
-#ifdef USE_PLIC
- // External Machine-Level interrupt from PLIC
- } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
- handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
- // External Machine-Level interrupt from PLIC
- } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
- handle_m_time_interrupt();
-#endif
-#ifdef USE_LOCAL_ISR
- } else if (mcause & MCAUSE_INT) {
- localISR[mcause & MCAUSE_CAUSE] ();
-#endif
- }
- else {
- write(1, "Unhandled Trap:\n", 16);
- _exit(1 + mcause);
- }
- return epc;
-}
-#endif
-
-#ifdef USE_CLIC
-void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
-void trap_entry(void)
-{
- unsigned long mcause = read_csr(mcause);
- unsigned long mepc = read_csr(mepc);
- handle_trap(mcause, mepc);
-}
-#endif
-
-void _init()
-{
- #ifndef NO_INIT
- uart_init(115200);
-
- puts("core freq at " STR(CPU_FREQ) " Hz\n");
-
-#ifdef USE_CLIC
- write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
-#else
- write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED));
-#endif
-
- #endif
-}
-
-void _fini()
-{
-}
diff --git a/bsp/env/coreplexip-e31-arty/openocd.cfg b/bsp/env/coreplexip-e31-arty/openocd.cfg
deleted file mode 100644
index 0481a72..0000000
--- a/bsp/env/coreplexip-e31-arty/openocd.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-#flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/bsp/env/coreplexip-e31-arty/platform.h b/bsp/env/coreplexip-e31-arty/platform.h
deleted file mode 100644
index 6fa79ea..0000000
--- a/bsp/env/coreplexip-e31-arty/platform.h
+++ /dev/null
@@ -1,100 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-// Some things missing from the official encoding.h
-
-#if __riscv_xlen == 32
-#define MCAUSE_INT 0x80000000UL
-#define MCAUSE_CAUSE 0x000003FFUL
-#else
-#define MCAUSE_INT 0x8000000000000000UL
-#define MCAUSE_CAUSE 0x00000000000003FFUL
-#endif
-
-#ifdef VECT_IRQ
- #define MTVEC_VECTORED 0x01
-#else
- #define MTVEC_VECTORED 0x00
-#endif
-#define MTVEC_CLIC 0x02
-#define IRQ_M_LOCAL 16
-#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x))
-
-#include "sifive/const.h"
-#include "sifive/devices/clint.h"
-#include "sifive/devices/gpio.h"
-#include "sifive/devices/plic.h"
-#include "sifive/devices/pwm.h"
-#include "sifive/devices/spi.h"
-#include "sifive/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// Memory map
-#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
-#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
-#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
-#define RAM_MEM_ADDR _AC(0x80000000,UL)
-#define RAM_MEM_SIZE _AC(0x10000,UL)
-#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
-#define SPI0_MEM_ADDR _AC(0x40000000,UL)
-#define SPI0_MEM_SIZE _AC(0x20000000,UL)
-#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
-#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
-#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
-#define UART0_CTRL_ADDR _AC(0x20000000,UL)
-
-// IOF masks
-
-// Interrupt numbers
-#define RESERVED_INT_BASE 0
-#define UART0_INT_BASE 1
-#define EXTERNAL_INT_BASE 2
-#define SPI0_INT_BASE 6
-#define GPIO_INT_BASE 7
-#define PWM0_INT_BASE 23
-
-// Helper functions
-#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
-#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
-#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
-// Bulk set bits in `reg` to either 0 or 1.
-// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
-// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
-#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
-#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
-#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
-#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
-#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
-#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
-#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
-#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset)
-#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
-
-// Misc
-
-#define NUM_GPIO 16
-
-#define PLIC_NUM_INTERRUPTS 28
-#define PLIC_NUM_PRIORITIES 7
-
-#define HAS_BOARD_BUTTONS
-
-#include "coreplexip-arty.h"
-
-unsigned long get_cpu_freq(void);
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/coreplexip-e31-arty/scratchpad.lds b/bsp/env/coreplexip-e31-arty/scratchpad.lds
deleted file mode 100644
index 7887c13..0000000
--- a/bsp/env/coreplexip-e31-arty/scratchpad.lds
+++ /dev/null
@@ -1,161 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
-}
-
-PHDRS
-{
- ram PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >ram AT>ram :ram
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >ram AT>ram :ram
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >ram AT>ram :ram
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- } >ram AT>ram :ram
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >ram AT>ram :ram
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >ram AT>ram :ram
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >ram AT>ram :ram
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >ram AT>ram :ram
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >ram AT>ram :ram
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >ram AT>ram :ram
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>ram :ram_init
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>ram :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack :
- {
- . = ALIGN(8);
- . += __stack_size;
- PROVIDE( _sp = . );
- PROVIDE( _heap_end = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/coreplexip-e31-arty/settings.mk b/bsp/env/coreplexip-e31-arty/settings.mk
deleted file mode 100644
index 230fccc..0000000
--- a/bsp/env/coreplexip-e31-arty/settings.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-# Describes the CPU on this board to the rest of the SDK.
-RISCV_ARCH := rv32imac
-RISCV_ABI := ilp32
diff --git a/bsp/env/coreplexip-e51-arty/dhrystone.lds b/bsp/env/coreplexip-e51-arty/dhrystone.lds
deleted file mode 120000
index 8459e13..0000000
--- a/bsp/env/coreplexip-e51-arty/dhrystone.lds
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/dhrystone.lds \ No newline at end of file
diff --git a/bsp/env/coreplexip-e51-arty/flash.lds b/bsp/env/coreplexip-e51-arty/flash.lds
deleted file mode 120000
index 54c1026..0000000
--- a/bsp/env/coreplexip-e51-arty/flash.lds
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/flash.lds \ No newline at end of file
diff --git a/bsp/env/coreplexip-e51-arty/init.c b/bsp/env/coreplexip-e51-arty/init.c
deleted file mode 120000
index de048a9..0000000
--- a/bsp/env/coreplexip-e51-arty/init.c
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/init.c \ No newline at end of file
diff --git a/bsp/env/coreplexip-e51-arty/openocd.cfg b/bsp/env/coreplexip-e51-arty/openocd.cfg
deleted file mode 120000
index 2f4de8d..0000000
--- a/bsp/env/coreplexip-e51-arty/openocd.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/openocd.cfg \ No newline at end of file
diff --git a/bsp/env/coreplexip-e51-arty/platform.h b/bsp/env/coreplexip-e51-arty/platform.h
deleted file mode 120000
index 311ca36..0000000
--- a/bsp/env/coreplexip-e51-arty/platform.h
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/platform.h \ No newline at end of file
diff --git a/bsp/env/coreplexip-e51-arty/scratchpad.lds b/bsp/env/coreplexip-e51-arty/scratchpad.lds
deleted file mode 120000
index 7fbe10a..0000000
--- a/bsp/env/coreplexip-e51-arty/scratchpad.lds
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/scratchpad.lds \ No newline at end of file
diff --git a/bsp/env/coreplexip-e51-arty/settings.mk b/bsp/env/coreplexip-e51-arty/settings.mk
deleted file mode 100644
index 96aea84..0000000
--- a/bsp/env/coreplexip-e51-arty/settings.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-# Describes the CPU on this board to the rest of the SDK.
-RISCV_ARCH := rv64imac
-RISCV_ABI := lp64
diff --git a/bsp/env/encoding.h b/bsp/env/encoding.h
deleted file mode 100644
index 35e0f9f..0000000
--- a/bsp/env/encoding.h
+++ /dev/null
@@ -1,1313 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef RISCV_CSR_ENCODING_H
-#define RISCV_CSR_ENCODING_H
-
-#define MSTATUS_UIE 0x00000001
-#define MSTATUS_SIE 0x00000002
-#define MSTATUS_HIE 0x00000004
-#define MSTATUS_MIE 0x00000008
-#define MSTATUS_UPIE 0x00000010
-#define MSTATUS_SPIE 0x00000020
-#define MSTATUS_HPIE 0x00000040
-#define MSTATUS_MPIE 0x00000080
-#define MSTATUS_SPP 0x00000100
-#define MSTATUS_HPP 0x00000600
-#define MSTATUS_MPP 0x00001800
-#define MSTATUS_FS 0x00006000
-#define MSTATUS_XS 0x00018000
-#define MSTATUS_MPRV 0x00020000
-#define MSTATUS_PUM 0x00040000
-#define MSTATUS_MXR 0x00080000
-#define MSTATUS_VM 0x1F000000
-#define MSTATUS32_SD 0x80000000
-#define MSTATUS64_SD 0x8000000000000000
-
-#define SSTATUS_UIE 0x00000001
-#define SSTATUS_SIE 0x00000002
-#define SSTATUS_UPIE 0x00000010
-#define SSTATUS_SPIE 0x00000020
-#define SSTATUS_SPP 0x00000100
-#define SSTATUS_FS 0x00006000
-#define SSTATUS_XS 0x00018000
-#define SSTATUS_PUM 0x00040000
-#define SSTATUS32_SD 0x80000000
-#define SSTATUS64_SD 0x8000000000000000
-
-#define DCSR_XDEBUGVER (3U<<30)
-#define DCSR_NDRESET (1<<29)
-#define DCSR_FULLRESET (1<<28)
-#define DCSR_EBREAKM (1<<15)
-#define DCSR_EBREAKH (1<<14)
-#define DCSR_EBREAKS (1<<13)
-#define DCSR_EBREAKU (1<<12)
-#define DCSR_STOPCYCLE (1<<10)
-#define DCSR_STOPTIME (1<<9)
-#define DCSR_CAUSE (7<<6)
-#define DCSR_DEBUGINT (1<<5)
-#define DCSR_HALT (1<<3)
-#define DCSR_STEP (1<<2)
-#define DCSR_PRV (3<<0)
-
-#define DCSR_CAUSE_NONE 0
-#define DCSR_CAUSE_SWBP 1
-#define DCSR_CAUSE_HWBP 2
-#define DCSR_CAUSE_DEBUGINT 3
-#define DCSR_CAUSE_STEP 4
-#define DCSR_CAUSE_HALT 5
-
-#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
-#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
-#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
-
-#define MCONTROL_SELECT (1<<19)
-#define MCONTROL_TIMING (1<<18)
-#define MCONTROL_ACTION (0x3f<<12)
-#define MCONTROL_CHAIN (1<<11)
-#define MCONTROL_MATCH (0xf<<7)
-#define MCONTROL_M (1<<6)
-#define MCONTROL_H (1<<5)
-#define MCONTROL_S (1<<4)
-#define MCONTROL_U (1<<3)
-#define MCONTROL_EXECUTE (1<<2)
-#define MCONTROL_STORE (1<<1)
-#define MCONTROL_LOAD (1<<0)
-
-#define MCONTROL_TYPE_NONE 0
-#define MCONTROL_TYPE_MATCH 2
-
-#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
-#define MCONTROL_ACTION_DEBUG_MODE 1
-#define MCONTROL_ACTION_TRACE_START 2
-#define MCONTROL_ACTION_TRACE_STOP 3
-#define MCONTROL_ACTION_TRACE_EMIT 4
-
-#define MCONTROL_MATCH_EQUAL 0
-#define MCONTROL_MATCH_NAPOT 1
-#define MCONTROL_MATCH_GE 2
-#define MCONTROL_MATCH_LT 3
-#define MCONTROL_MATCH_MASK_LOW 4
-#define MCONTROL_MATCH_MASK_HIGH 5
-
-#define MIP_SSIP (1 << IRQ_S_SOFT)
-#define MIP_HSIP (1 << IRQ_H_SOFT)
-#define MIP_MSIP (1 << IRQ_M_SOFT)
-#define MIP_STIP (1 << IRQ_S_TIMER)
-#define MIP_HTIP (1 << IRQ_H_TIMER)
-#define MIP_MTIP (1 << IRQ_M_TIMER)
-#define MIP_SEIP (1 << IRQ_S_EXT)
-#define MIP_HEIP (1 << IRQ_H_EXT)
-#define MIP_MEIP (1 << IRQ_M_EXT)
-
-#define SIP_SSIP MIP_SSIP
-#define SIP_STIP MIP_STIP
-
-#define PRV_U 0
-#define PRV_S 1
-#define PRV_H 2
-#define PRV_M 3
-
-#define VM_MBARE 0
-#define VM_MBB 1
-#define VM_MBBID 2
-#define VM_SV32 8
-#define VM_SV39 9
-#define VM_SV48 10
-
-#define IRQ_S_SOFT 1
-#define IRQ_H_SOFT 2
-#define IRQ_M_SOFT 3
-#define IRQ_S_TIMER 5
-#define IRQ_H_TIMER 6
-#define IRQ_M_TIMER 7
-#define IRQ_S_EXT 9
-#define IRQ_H_EXT 10
-#define IRQ_M_EXT 11
-#define IRQ_COP 12
-#define IRQ_HOST 13
-
-#define DEFAULT_RSTVEC 0x00001000
-#define DEFAULT_NMIVEC 0x00001004
-#define DEFAULT_MTVEC 0x00001010
-#define CONFIG_STRING_ADDR 0x0000100C
-#define EXT_IO_BASE 0x40000000
-#define DRAM_BASE 0x80000000
-
-// page table entry (PTE) fields
-#define PTE_V 0x001 // Valid
-#define PTE_R 0x002 // Read
-#define PTE_W 0x004 // Write
-#define PTE_X 0x008 // Execute
-#define PTE_U 0x010 // User
-#define PTE_G 0x020 // Global
-#define PTE_A 0x040 // Accessed
-#define PTE_D 0x080 // Dirty
-#define PTE_SOFT 0x300 // Reserved for Software
-
-#define PTE_PPN_SHIFT 10
-
-#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
-
-#ifdef __riscv
-
-#ifdef __riscv64
-# define MSTATUS_SD MSTATUS64_SD
-# define SSTATUS_SD SSTATUS64_SD
-# define RISCV_PGLEVEL_BITS 9
-#else
-# define MSTATUS_SD MSTATUS32_SD
-# define SSTATUS_SD SSTATUS32_SD
-# define RISCV_PGLEVEL_BITS 10
-#endif
-#define RISCV_PGSHIFT 12
-#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
-
-#ifndef __ASSEMBLER__
-
-#ifdef __GNUC__
-
-#define read_csr(reg) ({ unsigned long __tmp; \
- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
- __tmp; })
-
-#define write_csr(reg, val) ({ \
- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
- asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
- else \
- asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
-
-#define swap_csr(reg, val) ({ unsigned long __tmp; \
- if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
- else \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
- __tmp; })
-
-#define set_csr(reg, bit) ({ unsigned long __tmp; \
- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
- else \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
- __tmp; })
-
-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
- if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
- else \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
- __tmp; })
-
-#define rdtime() read_csr(time)
-#define rdcycle() read_csr(cycle)
-#define rdinstret() read_csr(instret)
-
-#endif
-
-#endif
-
-#endif
-
-#endif
-/* Automatically generated by parse-opcodes */
-#ifndef RISCV_ENCODING_H
-#define RISCV_ENCODING_H
-#define MATCH_BEQ 0x63
-#define MASK_BEQ 0x707f
-#define MATCH_BNE 0x1063
-#define MASK_BNE 0x707f
-#define MATCH_BLT 0x4063
-#define MASK_BLT 0x707f
-#define MATCH_BGE 0x5063
-#define MASK_BGE 0x707f
-#define MATCH_BLTU 0x6063
-#define MASK_BLTU 0x707f
-#define MATCH_BGEU 0x7063
-#define MASK_BGEU 0x707f
-#define MATCH_JALR 0x67
-#define MASK_JALR 0x707f
-#define MATCH_JAL 0x6f
-#define MASK_JAL 0x7f
-#define MATCH_LUI 0x37
-#define MASK_LUI 0x7f
-#define MATCH_AUIPC 0x17
-#define MASK_AUIPC 0x7f
-#define MATCH_ADDI 0x13
-#define MASK_ADDI 0x707f
-#define MATCH_SLLI 0x1013
-#define MASK_SLLI 0xfc00707f
-#define MATCH_SLTI 0x2013
-#define MASK_SLTI 0x707f
-#define MATCH_SLTIU 0x3013
-#define MASK_SLTIU 0x707f
-#define MATCH_XORI 0x4013
-#define MASK_XORI 0x707f
-#define MATCH_SRLI 0x5013
-#define MASK_SRLI 0xfc00707f
-#define MATCH_SRAI 0x40005013
-#define MASK_SRAI 0xfc00707f
-#define MATCH_ORI 0x6013
-#define MASK_ORI 0x707f
-#define MATCH_ANDI 0x7013
-#define MASK_ANDI 0x707f
-#define MATCH_ADD 0x33
-#define MASK_ADD 0xfe00707f
-#define MATCH_SUB 0x40000033
-#define MASK_SUB 0xfe00707f
-#define MATCH_SLL 0x1033
-#define MASK_SLL 0xfe00707f
-#define MATCH_SLT 0x2033
-#define MASK_SLT 0xfe00707f
-#define MATCH_SLTU 0x3033
-#define MASK_SLTU 0xfe00707f
-#define MATCH_XOR 0x4033
-#define MASK_XOR 0xfe00707f
-#define MATCH_SRL 0x5033
-#define MASK_SRL 0xfe00707f
-#define MATCH_SRA 0x40005033
-#define MASK_SRA 0xfe00707f
-#define MATCH_OR 0x6033
-#define MASK_OR 0xfe00707f
-#define MATCH_AND 0x7033
-#define MASK_AND 0xfe00707f
-#define MATCH_ADDIW 0x1b
-#define MASK_ADDIW 0x707f
-#define MATCH_SLLIW 0x101b
-#define MASK_SLLIW 0xfe00707f
-#define MATCH_SRLIW 0x501b
-#define MASK_SRLIW 0xfe00707f
-#define MATCH_SRAIW 0x4000501b
-#define MASK_SRAIW 0xfe00707f
-#define MATCH_ADDW 0x3b
-#define MASK_ADDW 0xfe00707f
-#define MATCH_SUBW 0x4000003b
-#define MASK_SUBW 0xfe00707f
-#define MATCH_SLLW 0x103b
-#define MASK_SLLW 0xfe00707f
-#define MATCH_SRLW 0x503b
-#define MASK_SRLW 0xfe00707f
-#define MATCH_SRAW 0x4000503b
-#define MASK_SRAW 0xfe00707f
-#define MATCH_LB 0x3
-#define MASK_LB 0x707f
-#define MATCH_LH 0x1003
-#define MASK_LH 0x707f
-#define MATCH_LW 0x2003
-#define MASK_LW 0x707f
-#define MATCH_LD 0x3003
-#define MASK_LD 0x707f
-#define MATCH_LBU 0x4003
-#define MASK_LBU 0x707f
-#define MATCH_LHU 0x5003
-#define MASK_LHU 0x707f
-#define MATCH_LWU 0x6003
-#define MASK_LWU 0x707f
-#define MATCH_SB 0x23
-#define MASK_SB 0x707f
-#define MATCH_SH 0x1023
-#define MASK_SH 0x707f
-#define MATCH_SW 0x2023
-#define MASK_SW 0x707f
-#define MATCH_SD 0x3023
-#define MASK_SD 0x707f
-#define MATCH_FENCE 0xf
-#define MASK_FENCE 0x707f
-#define MATCH_FENCE_I 0x100f
-#define MASK_FENCE_I 0x707f
-#define MATCH_MUL 0x2000033
-#define MASK_MUL 0xfe00707f
-#define MATCH_MULH 0x2001033
-#define MASK_MULH 0xfe00707f
-#define MATCH_MULHSU 0x2002033
-#define MASK_MULHSU 0xfe00707f
-#define MATCH_MULHU 0x2003033
-#define MASK_MULHU 0xfe00707f
-#define MATCH_DIV 0x2004033
-#define MASK_DIV 0xfe00707f
-#define MATCH_DIVU 0x2005033
-#define MASK_DIVU 0xfe00707f
-#define MATCH_REM 0x2006033
-#define MASK_REM 0xfe00707f
-#define MATCH_REMU 0x2007033
-#define MASK_REMU 0xfe00707f
-#define MATCH_MULW 0x200003b
-#define MASK_MULW 0xfe00707f
-#define MATCH_DIVW 0x200403b
-#define MASK_DIVW 0xfe00707f
-#define MATCH_DIVUW 0x200503b
-#define MASK_DIVUW 0xfe00707f
-#define MATCH_REMW 0x200603b
-#define MASK_REMW 0xfe00707f
-#define MATCH_REMUW 0x200703b
-#define MASK_REMUW 0xfe00707f
-#define MATCH_AMOADD_W 0x202f
-#define MASK_AMOADD_W 0xf800707f
-#define MATCH_AMOXOR_W 0x2000202f
-#define MASK_AMOXOR_W 0xf800707f
-#define MATCH_AMOOR_W 0x4000202f
-#define MASK_AMOOR_W 0xf800707f
-#define MATCH_AMOAND_W 0x6000202f
-#define MASK_AMOAND_W 0xf800707f
-#define MATCH_AMOMIN_W 0x8000202f
-#define MASK_AMOMIN_W 0xf800707f
-#define MATCH_AMOMAX_W 0xa000202f
-#define MASK_AMOMAX_W 0xf800707f
-#define MATCH_AMOMINU_W 0xc000202f
-#define MASK_AMOMINU_W 0xf800707f
-#define MATCH_AMOMAXU_W 0xe000202f
-#define MASK_AMOMAXU_W 0xf800707f
-#define MATCH_AMOSWAP_W 0x800202f
-#define MASK_AMOSWAP_W 0xf800707f
-#define MATCH_LR_W 0x1000202f
-#define MASK_LR_W 0xf9f0707f
-#define MATCH_SC_W 0x1800202f
-#define MASK_SC_W 0xf800707f
-#define MATCH_AMOADD_D 0x302f
-#define MASK_AMOADD_D 0xf800707f
-#define MATCH_AMOXOR_D 0x2000302f
-#define MASK_AMOXOR_D 0xf800707f
-#define MATCH_AMOOR_D 0x4000302f
-#define MASK_AMOOR_D 0xf800707f
-#define MATCH_AMOAND_D 0x6000302f
-#define MASK_AMOAND_D 0xf800707f
-#define MATCH_AMOMIN_D 0x8000302f
-#define MASK_AMOMIN_D 0xf800707f
-#define MATCH_AMOMAX_D 0xa000302f
-#define MASK_AMOMAX_D 0xf800707f
-#define MATCH_AMOMINU_D 0xc000302f
-#define MASK_AMOMINU_D 0xf800707f
-#define MATCH_AMOMAXU_D 0xe000302f
-#define MASK_AMOMAXU_D 0xf800707f
-#define MATCH_AMOSWAP_D 0x800302f
-#define MASK_AMOSWAP_D 0xf800707f
-#define MATCH_LR_D 0x1000302f
-#define MASK_LR_D 0xf9f0707f
-#define MATCH_SC_D 0x1800302f
-#define MASK_SC_D 0xf800707f
-#define MATCH_ECALL 0x73
-#define MASK_ECALL 0xffffffff
-#define MATCH_EBREAK 0x100073
-#define MASK_EBREAK 0xffffffff
-#define MATCH_URET 0x200073
-#define MASK_URET 0xffffffff
-#define MATCH_SRET 0x10200073
-#define MASK_SRET 0xffffffff
-#define MATCH_HRET 0x20200073
-#define MASK_HRET 0xffffffff
-#define MATCH_MRET 0x30200073
-#define MASK_MRET 0xffffffff
-#define MATCH_DRET 0x7b200073
-#define MASK_DRET 0xffffffff
-#define MATCH_SFENCE_VM 0x10400073
-#define MASK_SFENCE_VM 0xfff07fff
-#define MATCH_WFI 0x10500073
-#define MASK_WFI 0xffffffff
-#define MATCH_CSRRW 0x1073
-#define MASK_CSRRW 0x707f
-#define MATCH_CSRRS 0x2073
-#define MASK_CSRRS 0x707f
-#define MATCH_CSRRC 0x3073
-#define MASK_CSRRC 0x707f
-#define MATCH_CSRRWI 0x5073
-#define MASK_CSRRWI 0x707f
-#define MATCH_CSRRSI 0x6073
-#define MASK_CSRRSI 0x707f
-#define MATCH_CSRRCI 0x7073
-#define MASK_CSRRCI 0x707f
-#define MATCH_FADD_S 0x53
-#define MASK_FADD_S 0xfe00007f
-#define MATCH_FSUB_S 0x8000053
-#define MASK_FSUB_S 0xfe00007f
-#define MATCH_FMUL_S 0x10000053
-#define MASK_FMUL_S 0xfe00007f
-#define MATCH_FDIV_S 0x18000053
-#define MASK_FDIV_S 0xfe00007f
-#define MATCH_FSGNJ_S 0x20000053
-#define MASK_FSGNJ_S 0xfe00707f
-#define MATCH_FSGNJN_S 0x20001053
-#define MASK_FSGNJN_S 0xfe00707f
-#define MATCH_FSGNJX_S 0x20002053
-#define MASK_FSGNJX_S 0xfe00707f
-#define MATCH_FMIN_S 0x28000053
-#define MASK_FMIN_S 0xfe00707f
-#define MATCH_FMAX_S 0x28001053
-#define MASK_FMAX_S 0xfe00707f
-#define MATCH_FSQRT_S 0x58000053
-#define MASK_FSQRT_S 0xfff0007f
-#define MATCH_FADD_D 0x2000053
-#define MASK_FADD_D 0xfe00007f
-#define MATCH_FSUB_D 0xa000053
-#define MASK_FSUB_D 0xfe00007f
-#define MATCH_FMUL_D 0x12000053
-#define MASK_FMUL_D 0xfe00007f
-#define MATCH_FDIV_D 0x1a000053
-#define MASK_FDIV_D 0xfe00007f
-#define MATCH_FSGNJ_D 0x22000053
-#define MASK_FSGNJ_D 0xfe00707f
-#define MATCH_FSGNJN_D 0x22001053
-#define MASK_FSGNJN_D 0xfe00707f
-#define MATCH_FSGNJX_D 0x22002053
-#define MASK_FSGNJX_D 0xfe00707f
-#define MATCH_FMIN_D 0x2a000053
-#define MASK_FMIN_D 0xfe00707f
-#define MATCH_FMAX_D 0x2a001053
-#define MASK_FMAX_D 0xfe00707f
-#define MATCH_FCVT_S_D 0x40100053
-#define MASK_FCVT_S_D 0xfff0007f
-#define MATCH_FCVT_D_S 0x42000053
-#define MASK_FCVT_D_S 0xfff0007f
-#define MATCH_FSQRT_D 0x5a000053
-#define MASK_FSQRT_D 0xfff0007f
-#define MATCH_FLE_S 0xa0000053
-#define MASK_FLE_S 0xfe00707f
-#define MATCH_FLT_S 0xa0001053
-#define MASK_FLT_S 0xfe00707f
-#define MATCH_FEQ_S 0xa0002053
-#define MASK_FEQ_S 0xfe00707f
-#define MATCH_FLE_D 0xa2000053
-#define MASK_FLE_D 0xfe00707f
-#define MATCH_FLT_D 0xa2001053
-#define MASK_FLT_D 0xfe00707f
-#define MATCH_FEQ_D 0xa2002053
-#define MASK_FEQ_D 0xfe00707f
-#define MATCH_FCVT_W_S 0xc0000053
-#define MASK_FCVT_W_S 0xfff0007f
-#define MATCH_FCVT_WU_S 0xc0100053
-#define MASK_FCVT_WU_S 0xfff0007f
-#define MATCH_FCVT_L_S 0xc0200053
-#define MASK_FCVT_L_S 0xfff0007f
-#define MATCH_FCVT_LU_S 0xc0300053
-#define MASK_FCVT_LU_S 0xfff0007f
-#define MATCH_FMV_X_S 0xe0000053
-#define MASK_FMV_X_S 0xfff0707f
-#define MATCH_FCLASS_S 0xe0001053
-#define MASK_FCLASS_S 0xfff0707f
-#define MATCH_FCVT_W_D 0xc2000053
-#define MASK_FCVT_W_D 0xfff0007f
-#define MATCH_FCVT_WU_D 0xc2100053
-#define MASK_FCVT_WU_D 0xfff0007f
-#define MATCH_FCVT_L_D 0xc2200053
-#define MASK_FCVT_L_D 0xfff0007f
-#define MATCH_FCVT_LU_D 0xc2300053
-#define MASK_FCVT_LU_D 0xfff0007f
-#define MATCH_FMV_X_D 0xe2000053
-#define MASK_FMV_X_D 0xfff0707f
-#define MATCH_FCLASS_D 0xe2001053
-#define MASK_FCLASS_D 0xfff0707f
-#define MATCH_FCVT_S_W 0xd0000053
-#define MASK_FCVT_S_W 0xfff0007f
-#define MATCH_FCVT_S_WU 0xd0100053
-#define MASK_FCVT_S_WU 0xfff0007f
-#define MATCH_FCVT_S_L 0xd0200053
-#define MASK_FCVT_S_L 0xfff0007f
-#define MATCH_FCVT_S_LU 0xd0300053
-#define MASK_FCVT_S_LU 0xfff0007f
-#define MATCH_FMV_S_X 0xf0000053
-#define MASK_FMV_S_X 0xfff0707f
-#define MATCH_FCVT_D_W 0xd2000053
-#define MASK_FCVT_D_W 0xfff0007f
-#define MATCH_FCVT_D_WU 0xd2100053
-#define MASK_FCVT_D_WU 0xfff0007f
-#define MATCH_FCVT_D_L 0xd2200053
-#define MASK_FCVT_D_L 0xfff0007f
-#define MATCH_FCVT_D_LU 0xd2300053
-#define MASK_FCVT_D_LU 0xfff0007f
-#define MATCH_FMV_D_X 0xf2000053
-#define MASK_FMV_D_X 0xfff0707f
-#define MATCH_FLW 0x2007
-#define MASK_FLW 0x707f
-#define MATCH_FLD 0x3007
-#define MASK_FLD 0x707f
-#define MATCH_FSW 0x2027
-#define MASK_FSW 0x707f
-#define MATCH_FSD 0x3027
-#define MASK_FSD 0x707f
-#define MATCH_FMADD_S 0x43
-#define MASK_FMADD_S 0x600007f
-#define MATCH_FMSUB_S 0x47
-#define MASK_FMSUB_S 0x600007f
-#define MATCH_FNMSUB_S 0x4b
-#define MASK_FNMSUB_S 0x600007f
-#define MATCH_FNMADD_S 0x4f
-#define MASK_FNMADD_S 0x600007f
-#define MATCH_FMADD_D 0x2000043
-#define MASK_FMADD_D 0x600007f
-#define MATCH_FMSUB_D 0x2000047
-#define MASK_FMSUB_D 0x600007f
-#define MATCH_FNMSUB_D 0x200004b
-#define MASK_FNMSUB_D 0x600007f
-#define MATCH_FNMADD_D 0x200004f
-#define MASK_FNMADD_D 0x600007f
-#define MATCH_C_NOP 0x1
-#define MASK_C_NOP 0xffff
-#define MATCH_C_ADDI16SP 0x6101
-#define MASK_C_ADDI16SP 0xef83
-#define MATCH_C_JR 0x8002
-#define MASK_C_JR 0xf07f
-#define MATCH_C_JALR 0x9002
-#define MASK_C_JALR 0xf07f
-#define MATCH_C_EBREAK 0x9002
-#define MASK_C_EBREAK 0xffff
-#define MATCH_C_LD 0x6000
-#define MASK_C_LD 0xe003
-#define MATCH_C_SD 0xe000
-#define MASK_C_SD 0xe003
-#define MATCH_C_ADDIW 0x2001
-#define MASK_C_ADDIW 0xe003
-#define MATCH_C_LDSP 0x6002
-#define MASK_C_LDSP 0xe003
-#define MATCH_C_SDSP 0xe002
-#define MASK_C_SDSP 0xe003
-#define MATCH_C_ADDI4SPN 0x0
-#define MASK_C_ADDI4SPN 0xe003
-#define MATCH_C_FLD 0x2000
-#define MASK_C_FLD 0xe003
-#define MATCH_C_LW 0x4000
-#define MASK_C_LW 0xe003
-#define MATCH_C_FLW 0x6000
-#define MASK_C_FLW 0xe003
-#define MATCH_C_FSD 0xa000
-#define MASK_C_FSD 0xe003
-#define MATCH_C_SW 0xc000
-#define MASK_C_SW 0xe003
-#define MATCH_C_FSW 0xe000
-#define MASK_C_FSW 0xe003
-#define MATCH_C_ADDI 0x1
-#define MASK_C_ADDI 0xe003
-#define MATCH_C_JAL 0x2001
-#define MASK_C_JAL 0xe003
-#define MATCH_C_LI 0x4001
-#define MASK_C_LI 0xe003
-#define MATCH_C_LUI 0x6001
-#define MASK_C_LUI 0xe003
-#define MATCH_C_SRLI 0x8001
-#define MASK_C_SRLI 0xec03
-#define MATCH_C_SRAI 0x8401
-#define MASK_C_SRAI 0xec03
-#define MATCH_C_ANDI 0x8801
-#define MASK_C_ANDI 0xec03
-#define MATCH_C_SUB 0x8c01
-#define MASK_C_SUB 0xfc63
-#define MATCH_C_XOR 0x8c21
-#define MASK_C_XOR 0xfc63
-#define MATCH_C_OR 0x8c41
-#define MASK_C_OR 0xfc63
-#define MATCH_C_AND 0x8c61
-#define MASK_C_AND 0xfc63
-#define MATCH_C_SUBW 0x9c01
-#define MASK_C_SUBW 0xfc63
-#define MATCH_C_ADDW 0x9c21
-#define MASK_C_ADDW 0xfc63
-#define MATCH_C_J 0xa001
-#define MASK_C_J 0xe003
-#define MATCH_C_BEQZ 0xc001
-#define MASK_C_BEQZ 0xe003
-#define MATCH_C_BNEZ 0xe001
-#define MASK_C_BNEZ 0xe003
-#define MATCH_C_SLLI 0x2
-#define MASK_C_SLLI 0xe003
-#define MATCH_C_FLDSP 0x2002
-#define MASK_C_FLDSP 0xe003
-#define MATCH_C_LWSP 0x4002
-#define MASK_C_LWSP 0xe003
-#define MATCH_C_FLWSP 0x6002
-#define MASK_C_FLWSP 0xe003
-#define MATCH_C_MV 0x8002
-#define MASK_C_MV 0xf003
-#define MATCH_C_ADD 0x9002
-#define MASK_C_ADD 0xf003
-#define MATCH_C_FSDSP 0xa002
-#define MASK_C_FSDSP 0xe003
-#define MATCH_C_SWSP 0xc002
-#define MASK_C_SWSP 0xe003
-#define MATCH_C_FSWSP 0xe002
-#define MASK_C_FSWSP 0xe003
-#define MATCH_CUSTOM0 0xb
-#define MASK_CUSTOM0 0x707f
-#define MATCH_CUSTOM0_RS1 0x200b
-#define MASK_CUSTOM0_RS1 0x707f
-#define MATCH_CUSTOM0_RS1_RS2 0x300b
-#define MASK_CUSTOM0_RS1_RS2 0x707f
-#define MATCH_CUSTOM0_RD 0x400b
-#define MASK_CUSTOM0_RD 0x707f
-#define MATCH_CUSTOM0_RD_RS1 0x600b
-#define MASK_CUSTOM0_RD_RS1 0x707f
-#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
-#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM1 0x2b
-#define MASK_CUSTOM1 0x707f
-#define MATCH_CUSTOM1_RS1 0x202b
-#define MASK_CUSTOM1_RS1 0x707f
-#define MATCH_CUSTOM1_RS1_RS2 0x302b
-#define MASK_CUSTOM1_RS1_RS2 0x707f
-#define MATCH_CUSTOM1_RD 0x402b
-#define MASK_CUSTOM1_RD 0x707f
-#define MATCH_CUSTOM1_RD_RS1 0x602b
-#define MASK_CUSTOM1_RD_RS1 0x707f
-#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
-#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM2 0x5b
-#define MASK_CUSTOM2 0x707f
-#define MATCH_CUSTOM2_RS1 0x205b
-#define MASK_CUSTOM2_RS1 0x707f
-#define MATCH_CUSTOM2_RS1_RS2 0x305b
-#define MASK_CUSTOM2_RS1_RS2 0x707f
-#define MATCH_CUSTOM2_RD 0x405b
-#define MASK_CUSTOM2_RD 0x707f
-#define MATCH_CUSTOM2_RD_RS1 0x605b
-#define MASK_CUSTOM2_RD_RS1 0x707f
-#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
-#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
-#define MATCH_CUSTOM3 0x7b
-#define MASK_CUSTOM3 0x707f
-#define MATCH_CUSTOM3_RS1 0x207b
-#define MASK_CUSTOM3_RS1 0x707f
-#define MATCH_CUSTOM3_RS1_RS2 0x307b
-#define MASK_CUSTOM3_RS1_RS2 0x707f
-#define MATCH_CUSTOM3_RD 0x407b
-#define MASK_CUSTOM3_RD 0x707f
-#define MATCH_CUSTOM3_RD_RS1 0x607b
-#define MASK_CUSTOM3_RD_RS1 0x707f
-#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
-#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
-#define CSR_FFLAGS 0x1
-#define CSR_FRM 0x2
-#define CSR_FCSR 0x3
-#define CSR_CYCLE 0xc00
-#define CSR_TIME 0xc01
-#define CSR_INSTRET 0xc02
-#define CSR_HPMCOUNTER3 0xc03
-#define CSR_HPMCOUNTER4 0xc04
-#define CSR_HPMCOUNTER5 0xc05
-#define CSR_HPMCOUNTER6 0xc06
-#define CSR_HPMCOUNTER7 0xc07
-#define CSR_HPMCOUNTER8 0xc08
-#define CSR_HPMCOUNTER9 0xc09
-#define CSR_HPMCOUNTER10 0xc0a
-#define CSR_HPMCOUNTER11 0xc0b
-#define CSR_HPMCOUNTER12 0xc0c
-#define CSR_HPMCOUNTER13 0xc0d
-#define CSR_HPMCOUNTER14 0xc0e
-#define CSR_HPMCOUNTER15 0xc0f
-#define CSR_HPMCOUNTER16 0xc10
-#define CSR_HPMCOUNTER17 0xc11
-#define CSR_HPMCOUNTER18 0xc12
-#define CSR_HPMCOUNTER19 0xc13
-#define CSR_HPMCOUNTER20 0xc14
-#define CSR_HPMCOUNTER21 0xc15
-#define CSR_HPMCOUNTER22 0xc16
-#define CSR_HPMCOUNTER23 0xc17
-#define CSR_HPMCOUNTER24 0xc18
-#define CSR_HPMCOUNTER25 0xc19
-#define CSR_HPMCOUNTER26 0xc1a
-#define CSR_HPMCOUNTER27 0xc1b
-#define CSR_HPMCOUNTER28 0xc1c
-#define CSR_HPMCOUNTER29 0xc1d
-#define CSR_HPMCOUNTER30 0xc1e
-#define CSR_HPMCOUNTER31 0xc1f
-#define CSR_SSTATUS 0x100
-#define CSR_SIE 0x104
-#define CSR_STVEC 0x105
-#define CSR_SSCRATCH 0x140
-#define CSR_SEPC 0x141
-#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
-#define CSR_SIP 0x144
-#define CSR_SPTBR 0x180
-#define CSR_MSTATUS 0x300
-#define CSR_MISA 0x301
-#define CSR_MEDELEG 0x302
-#define CSR_MIDELEG 0x303
-#define CSR_MIE 0x304
-#define CSR_MTVEC 0x305
-#define CSR_MSCRATCH 0x340
-#define CSR_MEPC 0x341
-#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
-#define CSR_MIP 0x344
-#define CSR_TSELECT 0x7a0
-#define CSR_TDATA1 0x7a1
-#define CSR_TDATA2 0x7a2
-#define CSR_TDATA3 0x7a3
-#define CSR_DCSR 0x7b0
-#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
-#define CSR_MCYCLE 0xb00
-#define CSR_MINSTRET 0xb02
-#define CSR_MHPMCOUNTER3 0xb03
-#define CSR_MHPMCOUNTER4 0xb04
-#define CSR_MHPMCOUNTER5 0xb05
-#define CSR_MHPMCOUNTER6 0xb06
-#define CSR_MHPMCOUNTER7 0xb07
-#define CSR_MHPMCOUNTER8 0xb08
-#define CSR_MHPMCOUNTER9 0xb09
-#define CSR_MHPMCOUNTER10 0xb0a
-#define CSR_MHPMCOUNTER11 0xb0b
-#define CSR_MHPMCOUNTER12 0xb0c
-#define CSR_MHPMCOUNTER13 0xb0d
-#define CSR_MHPMCOUNTER14 0xb0e
-#define CSR_MHPMCOUNTER15 0xb0f
-#define CSR_MHPMCOUNTER16 0xb10
-#define CSR_MHPMCOUNTER17 0xb11
-#define CSR_MHPMCOUNTER18 0xb12
-#define CSR_MHPMCOUNTER19 0xb13
-#define CSR_MHPMCOUNTER20 0xb14
-#define CSR_MHPMCOUNTER21 0xb15
-#define CSR_MHPMCOUNTER22 0xb16
-#define CSR_MHPMCOUNTER23 0xb17
-#define CSR_MHPMCOUNTER24 0xb18
-#define CSR_MHPMCOUNTER25 0xb19
-#define CSR_MHPMCOUNTER26 0xb1a
-#define CSR_MHPMCOUNTER27 0xb1b
-#define CSR_MHPMCOUNTER28 0xb1c
-#define CSR_MHPMCOUNTER29 0xb1d
-#define CSR_MHPMCOUNTER30 0xb1e
-#define CSR_MHPMCOUNTER31 0xb1f
-#define CSR_MUCOUNTEREN 0x320
-#define CSR_MSCOUNTEREN 0x321
-#define CSR_MHPMEVENT3 0x323
-#define CSR_MHPMEVENT4 0x324
-#define CSR_MHPMEVENT5 0x325
-#define CSR_MHPMEVENT6 0x326
-#define CSR_MHPMEVENT7 0x327
-#define CSR_MHPMEVENT8 0x328
-#define CSR_MHPMEVENT9 0x329
-#define CSR_MHPMEVENT10 0x32a
-#define CSR_MHPMEVENT11 0x32b
-#define CSR_MHPMEVENT12 0x32c
-#define CSR_MHPMEVENT13 0x32d
-#define CSR_MHPMEVENT14 0x32e
-#define CSR_MHPMEVENT15 0x32f
-#define CSR_MHPMEVENT16 0x330
-#define CSR_MHPMEVENT17 0x331
-#define CSR_MHPMEVENT18 0x332
-#define CSR_MHPMEVENT19 0x333
-#define CSR_MHPMEVENT20 0x334
-#define CSR_MHPMEVENT21 0x335
-#define CSR_MHPMEVENT22 0x336
-#define CSR_MHPMEVENT23 0x337
-#define CSR_MHPMEVENT24 0x338
-#define CSR_MHPMEVENT25 0x339
-#define CSR_MHPMEVENT26 0x33a
-#define CSR_MHPMEVENT27 0x33b
-#define CSR_MHPMEVENT28 0x33c
-#define CSR_MHPMEVENT29 0x33d
-#define CSR_MHPMEVENT30 0x33e
-#define CSR_MHPMEVENT31 0x33f
-#define CSR_MVENDORID 0xf11
-#define CSR_MARCHID 0xf12
-#define CSR_MIMPID 0xf13
-#define CSR_MHARTID 0xf14
-#define CSR_CYCLEH 0xc80
-#define CSR_TIMEH 0xc81
-#define CSR_INSTRETH 0xc82
-#define CSR_HPMCOUNTER3H 0xc83
-#define CSR_HPMCOUNTER4H 0xc84
-#define CSR_HPMCOUNTER5H 0xc85
-#define CSR_HPMCOUNTER6H 0xc86
-#define CSR_HPMCOUNTER7H 0xc87
-#define CSR_HPMCOUNTER8H 0xc88
-#define CSR_HPMCOUNTER9H 0xc89
-#define CSR_HPMCOUNTER10H 0xc8a
-#define CSR_HPMCOUNTER11H 0xc8b
-#define CSR_HPMCOUNTER12H 0xc8c
-#define CSR_HPMCOUNTER13H 0xc8d
-#define CSR_HPMCOUNTER14H 0xc8e
-#define CSR_HPMCOUNTER15H 0xc8f
-#define CSR_HPMCOUNTER16H 0xc90
-#define CSR_HPMCOUNTER17H 0xc91
-#define CSR_HPMCOUNTER18H 0xc92
-#define CSR_HPMCOUNTER19H 0xc93
-#define CSR_HPMCOUNTER20H 0xc94
-#define CSR_HPMCOUNTER21H 0xc95
-#define CSR_HPMCOUNTER22H 0xc96
-#define CSR_HPMCOUNTER23H 0xc97
-#define CSR_HPMCOUNTER24H 0xc98
-#define CSR_HPMCOUNTER25H 0xc99
-#define CSR_HPMCOUNTER26H 0xc9a
-#define CSR_HPMCOUNTER27H 0xc9b
-#define CSR_HPMCOUNTER28H 0xc9c
-#define CSR_HPMCOUNTER29H 0xc9d
-#define CSR_HPMCOUNTER30H 0xc9e
-#define CSR_HPMCOUNTER31H 0xc9f
-#define CSR_MCYCLEH 0xb80
-#define CSR_MINSTRETH 0xb82
-#define CSR_MHPMCOUNTER3H 0xb83
-#define CSR_MHPMCOUNTER4H 0xb84
-#define CSR_MHPMCOUNTER5H 0xb85
-#define CSR_MHPMCOUNTER6H 0xb86
-#define CSR_MHPMCOUNTER7H 0xb87
-#define CSR_MHPMCOUNTER8H 0xb88
-#define CSR_MHPMCOUNTER9H 0xb89
-#define CSR_MHPMCOUNTER10H 0xb8a
-#define CSR_MHPMCOUNTER11H 0xb8b
-#define CSR_MHPMCOUNTER12H 0xb8c
-#define CSR_MHPMCOUNTER13H 0xb8d
-#define CSR_MHPMCOUNTER14H 0xb8e
-#define CSR_MHPMCOUNTER15H 0xb8f
-#define CSR_MHPMCOUNTER16H 0xb90
-#define CSR_MHPMCOUNTER17H 0xb91
-#define CSR_MHPMCOUNTER18H 0xb92
-#define CSR_MHPMCOUNTER19H 0xb93
-#define CSR_MHPMCOUNTER20H 0xb94
-#define CSR_MHPMCOUNTER21H 0xb95
-#define CSR_MHPMCOUNTER22H 0xb96
-#define CSR_MHPMCOUNTER23H 0xb97
-#define CSR_MHPMCOUNTER24H 0xb98
-#define CSR_MHPMCOUNTER25H 0xb99
-#define CSR_MHPMCOUNTER26H 0xb9a
-#define CSR_MHPMCOUNTER27H 0xb9b
-#define CSR_MHPMCOUNTER28H 0xb9c
-#define CSR_MHPMCOUNTER29H 0xb9d
-#define CSR_MHPMCOUNTER30H 0xb9e
-#define CSR_MHPMCOUNTER31H 0xb9f
-#define CAUSE_MISALIGNED_FETCH 0x0
-#define CAUSE_FAULT_FETCH 0x1
-#define CAUSE_ILLEGAL_INSTRUCTION 0x2
-#define CAUSE_BREAKPOINT 0x3
-#define CAUSE_MISALIGNED_LOAD 0x4
-#define CAUSE_FAULT_LOAD 0x5
-#define CAUSE_MISALIGNED_STORE 0x6
-#define CAUSE_FAULT_STORE 0x7
-#define CAUSE_USER_ECALL 0x8
-#define CAUSE_SUPERVISOR_ECALL 0x9
-#define CAUSE_HYPERVISOR_ECALL 0xa
-#define CAUSE_MACHINE_ECALL 0xb
-#endif
-#ifdef DECLARE_INSN
-DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
-DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
-DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
-DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
-DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
-DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
-DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
-DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
-DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
-DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
-DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
-DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
-DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
-DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
-DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
-DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
-DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
-DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
-DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
-DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
-DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
-DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
-DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
-DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
-DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
-DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
-DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
-DECLARE_INSN(or, MATCH_OR, MASK_OR)
-DECLARE_INSN(and, MATCH_AND, MASK_AND)
-DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
-DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
-DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
-DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
-DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
-DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
-DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
-DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
-DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
-DECLARE_INSN(lb, MATCH_LB, MASK_LB)
-DECLARE_INSN(lh, MATCH_LH, MASK_LH)
-DECLARE_INSN(lw, MATCH_LW, MASK_LW)
-DECLARE_INSN(ld, MATCH_LD, MASK_LD)
-DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
-DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
-DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
-DECLARE_INSN(sb, MATCH_SB, MASK_SB)
-DECLARE_INSN(sh, MATCH_SH, MASK_SH)
-DECLARE_INSN(sw, MATCH_SW, MASK_SW)
-DECLARE_INSN(sd, MATCH_SD, MASK_SD)
-DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
-DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
-DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
-DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
-DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
-DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
-DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
-DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
-DECLARE_INSN(rem, MATCH_REM, MASK_REM)
-DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
-DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
-DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
-DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
-DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
-DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
-DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
-DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
-DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
-DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
-DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
-DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
-DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
-DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
-DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
-DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
-DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
-DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
-DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
-DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
-DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
-DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
-DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
-DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
-DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
-DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
-DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
-DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
-DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
-DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
-DECLARE_INSN(uret, MATCH_URET, MASK_URET)
-DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
-DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
-DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
-DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
-DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
-DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
-DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
-DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
-DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
-DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
-DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
-DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
-DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
-DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
-DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
-DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
-DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
-DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
-DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
-DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
-DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
-DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
-DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
-DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
-DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
-DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
-DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
-DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
-DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
-DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
-DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
-DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
-DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
-DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
-DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
-DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
-DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
-DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
-DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
-DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
-DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
-DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
-DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
-DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
-DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
-DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
-DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
-DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
-DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
-DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
-DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
-DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
-DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
-DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
-DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
-DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
-DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
-DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
-DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
-DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
-DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
-DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
-DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
-DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
-DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
-DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
-DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
-DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
-DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
-DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
-DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
-DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
-DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
-DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
-DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
-DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
-DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
-DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
-DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
-DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
-DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
-DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
-DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
-DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
-DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
-DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
-DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
-DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
-DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
-DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
-DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
-DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
-DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
-DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
-DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
-DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
-DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
-DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
-DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
-DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
-DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
-DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
-DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
-DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
-DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
-DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
-DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
-DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
-DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
-DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
-DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
-DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
-DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
-DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
-DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
-DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
-DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
-DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
-DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
-DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
-DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
-DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
-DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
-DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
-DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
-DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
-DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
-DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
-DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
-DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
-DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
-DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
-DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
-DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
-DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
-DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
-DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
-DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
-DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
-DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
-#endif
-#ifdef DECLARE_CSR
-DECLARE_CSR(fflags, CSR_FFLAGS)
-DECLARE_CSR(frm, CSR_FRM)
-DECLARE_CSR(fcsr, CSR_FCSR)
-DECLARE_CSR(cycle, CSR_CYCLE)
-DECLARE_CSR(time, CSR_TIME)
-DECLARE_CSR(instret, CSR_INSTRET)
-DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
-DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
-DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
-DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
-DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
-DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
-DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
-DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
-DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
-DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
-DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
-DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
-DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
-DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
-DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
-DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
-DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
-DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
-DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
-DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
-DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
-DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
-DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
-DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
-DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
-DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
-DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
-DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
-DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
-DECLARE_CSR(sstatus, CSR_SSTATUS)
-DECLARE_CSR(sie, CSR_SIE)
-DECLARE_CSR(stvec, CSR_STVEC)
-DECLARE_CSR(sscratch, CSR_SSCRATCH)
-DECLARE_CSR(sepc, CSR_SEPC)
-DECLARE_CSR(scause, CSR_SCAUSE)
-DECLARE_CSR(sbadaddr, CSR_SBADADDR)
-DECLARE_CSR(sip, CSR_SIP)
-DECLARE_CSR(sptbr, CSR_SPTBR)
-DECLARE_CSR(mstatus, CSR_MSTATUS)
-DECLARE_CSR(misa, CSR_MISA)
-DECLARE_CSR(medeleg, CSR_MEDELEG)
-DECLARE_CSR(mideleg, CSR_MIDELEG)
-DECLARE_CSR(mie, CSR_MIE)
-DECLARE_CSR(mtvec, CSR_MTVEC)
-DECLARE_CSR(mscratch, CSR_MSCRATCH)
-DECLARE_CSR(mepc, CSR_MEPC)
-DECLARE_CSR(mcause, CSR_MCAUSE)
-DECLARE_CSR(mbadaddr, CSR_MBADADDR)
-DECLARE_CSR(mip, CSR_MIP)
-DECLARE_CSR(tselect, CSR_TSELECT)
-DECLARE_CSR(tdata1, CSR_TDATA1)
-DECLARE_CSR(tdata2, CSR_TDATA2)
-DECLARE_CSR(tdata3, CSR_TDATA3)
-DECLARE_CSR(dcsr, CSR_DCSR)
-DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
-DECLARE_CSR(mcycle, CSR_MCYCLE)
-DECLARE_CSR(minstret, CSR_MINSTRET)
-DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
-DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
-DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
-DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
-DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
-DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
-DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
-DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
-DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
-DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
-DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
-DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
-DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
-DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
-DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
-DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
-DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
-DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
-DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
-DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
-DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
-DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
-DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
-DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
-DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
-DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
-DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
-DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
-DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
-DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
-DECLARE_CSR(mvendorid, CSR_MVENDORID)
-DECLARE_CSR(marchid, CSR_MARCHID)
-DECLARE_CSR(mimpid, CSR_MIMPID)
-DECLARE_CSR(mhartid, CSR_MHARTID)
-DECLARE_CSR(cycleh, CSR_CYCLEH)
-DECLARE_CSR(timeh, CSR_TIMEH)
-DECLARE_CSR(instreth, CSR_INSTRETH)
-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
-DECLARE_CSR(mcycleh, CSR_MCYCLEH)
-DECLARE_CSR(minstreth, CSR_MINSTRETH)
-DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
-DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
-DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
-DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
-DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
-DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
-DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
-DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
-DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
-DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
-DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
-DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
-DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
-DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
-DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
-DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
-DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
-DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
-DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
-DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
-DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
-DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
-DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
-DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
-DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
-DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
-DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
-DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
-DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
-#endif
-#ifdef DECLARE_CAUSE
-DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
-DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
-DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
-DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
-DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
-DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
-DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
-DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
-DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
-DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
-DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
-DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
-#endif
diff --git a/bsp/env/entry.S b/bsp/env/entry.S
deleted file mode 100644
index 261b2a4..0000000
--- a/bsp/env/entry.S
+++ /dev/null
@@ -1,98 +0,0 @@
-// See LICENSE for license details
-
-#ifndef ENTRY_S
-#define ENTRY_S
-
-#include "encoding.h"
-#include "sifive/bits.h"
-
- .section .text.entry
- .align 2
- .weak trap_entry
- .global trap_entry
-trap_entry:
- addi sp, sp, -32*REGBYTES
-
- STORE x1, 1*REGBYTES(sp)
- STORE x2, 2*REGBYTES(sp)
- STORE x3, 3*REGBYTES(sp)
- STORE x4, 4*REGBYTES(sp)
- STORE x5, 5*REGBYTES(sp)
- STORE x6, 6*REGBYTES(sp)
- STORE x7, 7*REGBYTES(sp)
- STORE x8, 8*REGBYTES(sp)
- STORE x9, 9*REGBYTES(sp)
- STORE x10, 10*REGBYTES(sp)
- STORE x11, 11*REGBYTES(sp)
- STORE x12, 12*REGBYTES(sp)
- STORE x13, 13*REGBYTES(sp)
- STORE x14, 14*REGBYTES(sp)
- STORE x15, 15*REGBYTES(sp)
- STORE x16, 16*REGBYTES(sp)
- STORE x17, 17*REGBYTES(sp)
- STORE x18, 18*REGBYTES(sp)
- STORE x19, 19*REGBYTES(sp)
- STORE x20, 20*REGBYTES(sp)
- STORE x21, 21*REGBYTES(sp)
- STORE x22, 22*REGBYTES(sp)
- STORE x23, 23*REGBYTES(sp)
- STORE x24, 24*REGBYTES(sp)
- STORE x25, 25*REGBYTES(sp)
- STORE x26, 26*REGBYTES(sp)
- STORE x27, 27*REGBYTES(sp)
- STORE x28, 28*REGBYTES(sp)
- STORE x29, 29*REGBYTES(sp)
- STORE x30, 30*REGBYTES(sp)
- STORE x31, 31*REGBYTES(sp)
-
- csrr a0, mcause
- csrr a1, mepc
- mv a2, sp
- call handle_trap
- csrw mepc, a0
-
- # Remain in M-mode after mret
- li t0, MSTATUS_MPP
- csrs mstatus, t0
-
- LOAD x1, 1*REGBYTES(sp)
- LOAD x2, 2*REGBYTES(sp)
- LOAD x3, 3*REGBYTES(sp)
- LOAD x4, 4*REGBYTES(sp)
- LOAD x5, 5*REGBYTES(sp)
- LOAD x6, 6*REGBYTES(sp)
- LOAD x7, 7*REGBYTES(sp)
- LOAD x8, 8*REGBYTES(sp)
- LOAD x9, 9*REGBYTES(sp)
- LOAD x10, 10*REGBYTES(sp)
- LOAD x11, 11*REGBYTES(sp)
- LOAD x12, 12*REGBYTES(sp)
- LOAD x13, 13*REGBYTES(sp)
- LOAD x14, 14*REGBYTES(sp)
- LOAD x15, 15*REGBYTES(sp)
- LOAD x16, 16*REGBYTES(sp)
- LOAD x17, 17*REGBYTES(sp)
- LOAD x18, 18*REGBYTES(sp)
- LOAD x19, 19*REGBYTES(sp)
- LOAD x20, 20*REGBYTES(sp)
- LOAD x21, 21*REGBYTES(sp)
- LOAD x22, 22*REGBYTES(sp)
- LOAD x23, 23*REGBYTES(sp)
- LOAD x24, 24*REGBYTES(sp)
- LOAD x25, 25*REGBYTES(sp)
- LOAD x26, 26*REGBYTES(sp)
- LOAD x27, 27*REGBYTES(sp)
- LOAD x28, 28*REGBYTES(sp)
- LOAD x29, 29*REGBYTES(sp)
- LOAD x30, 30*REGBYTES(sp)
- LOAD x31, 31*REGBYTES(sp)
-
- addi sp, sp, 32*REGBYTES
- mret
-
-.weak handle_trap
-handle_trap:
-1:
- j 1b
-
-#endif
diff --git a/bsp/env/freedom-e300-arty/flash.lds b/bsp/env/freedom-e300-arty/flash.lds
deleted file mode 120000
index 6441ce5..0000000
--- a/bsp/env/freedom-e300-arty/flash.lds
+++ /dev/null
@@ -1 +0,0 @@
-../freedom-e300-hifive1/flash.lds \ No newline at end of file
diff --git a/bsp/env/freedom-e300-arty/init.c b/bsp/env/freedom-e300-arty/init.c
deleted file mode 100644
index a6f4b39..0000000
--- a/bsp/env/freedom-e300-arty/init.c
+++ /dev/null
@@ -1,87 +0,0 @@
-//See LICENSE for license details.
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "platform.h"
-#include "encoding.h"
-
-extern int main(int argc, char** argv);
-extern void trap_entry();
-
-static unsigned long get_cpu_freq()
-{
- return 65000000;
-}
-
-unsigned long get_timer_freq()
-{
- return get_cpu_freq();
-}
-
-uint64_t get_timer_value()
-{
-#if __riscv_xlen == 32
- while (1) {
- uint32_t hi = read_csr(mcycleh);
- uint32_t lo = read_csr(mcycle);
- if (hi == read_csr(mcycleh))
- return ((uint64_t)hi << 32) | lo;
- }
-#else
- return read_csr(mcycle);
-#endif
-}
-
-static void uart_init(size_t baud_rate)
-{
- GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
- GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
- UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
- UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
- if (0){
-#ifdef USE_PLIC
- // External Machine-Level interrupt from PLIC
- } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
- handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
- // External Machine-Level interrupt from PLIC
- } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
- handle_m_time_interrupt();
-#endif
- }
- else {
- write(1, "Unhandled Trap:\n", 16);
- _exit(1 + mcause);
- }
- return epc;
-}
-
-void _init()
-{
- #ifndef NO_INIT
- uart_init(115200);
-
- printf("core freq at %d Hz\n", get_cpu_freq());
-
- write_csr(mtvec, &trap_entry);
- #endif
-}
-
-void _fini()
-{
-}
diff --git a/bsp/env/freedom-e300-arty/openocd.cfg b/bsp/env/freedom-e300-arty/openocd.cfg
deleted file mode 100644
index ba13207..0000000
--- a/bsp/env/freedom-e300-arty/openocd.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-adapter_khz 10000
-
-#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-#
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10014000
-init
-#reset
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-#flash protect 0 64 last off
diff --git a/bsp/env/freedom-e300-arty/platform.h b/bsp/env/freedom-e300-arty/platform.h
deleted file mode 100644
index 8ff7ae6..0000000
--- a/bsp/env/freedom-e300-arty/platform.h
+++ /dev/null
@@ -1,124 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-// Some things missing from the official encoding.h
-#define MCAUSE_INT 0x80000000
-#define MCAUSE_CAUSE 0x7FFFFFFF
-
-#include "sifive/const.h"
-#include "sifive/devices/aon.h"
-#include "sifive/devices/clint.h"
-#include "sifive/devices/gpio.h"
-#include "sifive/devices/plic.h"
-#include "sifive/devices/pwm.h"
-#include "sifive/devices/spi.h"
-#include "sifive/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
-#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
-#define AON_CTRL_ADDR _AC(0x10000000,UL)
-#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
-#define UART0_CTRL_ADDR _AC(0x10013000,UL)
-#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
-#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
-#define UART1_CTRL_ADDR _AC(0x10023000,UL)
-#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
-#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
-#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
-#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
-#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
-#define MEM_CTRL_ADDR _AC(0x80000000,UL)
-
-// IOF Mappings
-#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
-#define SPI11_NUM_SS (4)
-#define IOF_SPI1_SS0 (2u)
-#define IOF_SPI1_SS1 (8u)
-#define IOF_SPI1_SS2 (9u)
-#define IOF_SPI1_SS3 (10u)
-#define IOF_SPI1_MOSI (3u)
-#define IOF_SPI1_MISO (4u)
-#define IOF_SPI1_SCK (5u)
-#define IOF_SPI1_DQ0 (3u)
-#define IOF_SPI1_DQ1 (4u)
-#define IOF_SPI1_DQ2 (6u)
-#define IOF_SPI1_DQ3 (7u)
-
-#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
-#define SPI2_NUM_SS (1)
-#define IOF_SPI2_SS0 (26u)
-#define IOF_SPI2_MOSI (27u)
-#define IOF_SPI2_MISO (28u)
-#define IOF_SPI2_SCK (29u)
-#define IOF_SPI2_DQ0 (27u)
-#define IOF_SPI2_DQ1 (28u)
-#define IOF_SPI2_DQ2 (30u)
-#define IOF_SPI2_DQ3 (31u)
-
-#define IOF0_UART0_MASK _AC(0x00030000, UL)
-#define IOF_UART0_RX (16u)
-#define IOF_UART0_TX (17u)
-
-#define IOF0_UART1_MASK _AC(0x03000000, UL)
-#define IOF_UART1_RX (24u)
-#define IOF_UART1_TX (25u)
-
-#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
-#define IOF1_PWM1_MASK _AC(0x00780000, UL)
-#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
-
-// Interrupt Numbers
-#define INT_RESERVED 0
-#define INT_WDOGCMP 1
-#define INT_RTCCMP 2
-#define INT_UART0_BASE 3
-#define INT_UART1_BASE 4
-#define INT_SPI0_BASE 5
-#define INT_SPI1_BASE 6
-#define INT_SPI2_BASE 7
-#define INT_GPIO_BASE 8
-#define INT_PWM0_BASE 40
-#define INT_PWM1_BASE 44
-#define INT_PWM2_BASE 48
-
-// Helper functions
-#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
-#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
-#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
-#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
-#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
-#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
-#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
-#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
-
-// Misc
-
-#include <stdint.h>
-
-
-#define NUM_GPIO 32
-
-#define PLIC_NUM_INTERRUPTS 52
-#define PLIC_NUM_PRIORITIES 7
-
-#define HAS_BOARD_BUTTONS
-#include "hifive1.h"
-
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/freedom-e300-arty/settings.mk b/bsp/env/freedom-e300-arty/settings.mk
deleted file mode 100644
index 230fccc..0000000
--- a/bsp/env/freedom-e300-arty/settings.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-# Describes the CPU on this board to the rest of the SDK.
-RISCV_ARCH := rv32imac
-RISCV_ABI := ilp32
diff --git a/bsp/env/freedom-e300-hifive1/dhrystone.lds b/bsp/env/freedom-e300-hifive1/dhrystone.lds
deleted file mode 100644
index cc9cd9b..0000000
--- a/bsp/env/freedom-e300-hifive1/dhrystone.lds
+++ /dev/null
@@ -1,157 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash :flash
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >flash AT>flash :flash
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash :flash
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash :flash
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash :flash
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash :flash
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >flash AT>flash :flash
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >flash AT>flash :flash
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >flash AT>flash :flash
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>flash :ram_init
-
- .data :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>flash :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/freedom-e300-hifive1/flash.lds b/bsp/env/freedom-e300-hifive1/flash.lds
deleted file mode 100644
index 6b37141..0000000
--- a/bsp/env/freedom-e300-hifive1/flash.lds
+++ /dev/null
@@ -1,161 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-
-ENTRY( _start )
-
-MEMORY
-{
- flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- ram PT_NULL;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
-
- .init :
- {
- KEEP (*(SORT_NONE(.init)))
- } >flash AT>flash :flash
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >flash AT>flash :flash
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >flash AT>flash :flash
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- } >flash AT>flash :flash
-
- . = ALIGN(4);
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >flash AT>flash :flash
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >flash AT>flash :flash
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >flash AT>flash :flash
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >flash AT>flash :flash
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >flash AT>flash :flash
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- } >flash AT>flash :flash
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( _data = . );
- } >ram AT>flash :ram_init
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>flash :ram_init
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
-
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
-
- .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = __stack_size;
- PROVIDE( _sp = . );
- } >ram AT>ram :ram
-}
diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c
deleted file mode 100644
index 621a6e2..0000000
--- a/bsp/env/freedom-e300-hifive1/init.c
+++ /dev/null
@@ -1,238 +0,0 @@
-#include <stdint.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#include "platform.h"
-#include "encoding.h"
-
-extern int main(int argc, char** argv);
-extern void trap_entry();
-
-static unsigned long mtime_lo(void)
-{
- return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
-}
-
-#ifdef __riscv32
-
-static uint32_t mtime_hi(void)
-{
- return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
-}
-
-uint64_t get_timer_value()
-{
- while (1) {
- uint32_t hi = mtime_hi();
- uint32_t lo = mtime_lo();
- if (hi == mtime_hi())
- return ((uint64_t)hi << 32) | lo;
- }
-}
-
-#else /* __riscv32 */
-
-uint64_t get_timer_value()
-{
- return mtime_lo();
-}
-
-#endif
-
-unsigned long get_timer_freq()
-{
- return 32768;
-}
-
-static void use_hfrosc(int div, int trim)
-{
- // Make sure the HFROSC is running at its default setting
- PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
- while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
- PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
-}
-
-static void use_pll(int refsel, int bypass, int r, int f, int q)
-{
- // Ensure that we aren't running off the PLL before we mess with it.
- if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
- // Make sure the HFROSC is running at its default setting
- use_hfrosc(4, 16);
- }
-
- // Set PLL Source to be HFXOSC if available.
- uint32_t config_value = 0;
-
- config_value |= PLL_REFSEL(refsel);
-
- if (bypass) {
- // Bypass
- config_value |= PLL_BYPASS(1);
-
- PRCI_REG(PRCI_PLLCFG) = config_value;
-
- // If we don't have an HFXTAL, this doesn't really matter.
- // Set our Final output divide to divide-by-1:
- PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
- } else {
- // In case we are executing from QSPI,
- // (which is quite likely) we need to
- // set the QSPI clock divider appropriately
- // before boosting the clock frequency.
-
- // Div = f_sck/2
- SPI0_REG(SPI_REG_SCKDIV) = 8;
-
- // Set DIV Settings for PLL
- // Both HFROSC and HFXOSC are modeled as ideal
- // 16MHz sources (assuming dividers are set properly for
- // HFROSC).
- // (Legal values of f_REF are 6-48MHz)
-
- // Set DIVR to divide-by-2 to get 8MHz frequency
- // (legal values of f_R are 6-12 MHz)
-
- config_value |= PLL_BYPASS(1);
- config_value |= PLL_R(r);
-
- // Set DIVF to get 512Mhz frequncy
- // There is an implied multiply-by-2, 16Mhz.
- // So need to write 32-1
- // (legal values of f_F are 384-768 MHz)
- config_value |= PLL_F(f);
-
- // Set DIVQ to divide-by-2 to get 256 MHz frequency
- // (legal values of f_Q are 50-400Mhz)
- config_value |= PLL_Q(q);
-
- // Set our Final output divide to divide-by-1:
- PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
-
- PRCI_REG(PRCI_PLLCFG) = config_value;
-
- // Un-Bypass the PLL.
- PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
-
- // Wait for PLL Lock
- // Note that the Lock signal can be glitchy.
- // Need to wait 100 us
- // RTC is running at 32kHz.
- // So wait 4 ticks of RTC.
- uint32_t now = mtime_lo();
- while (mtime_lo() - now < 4) ;
-
- // Now it is safe to check for PLL Lock
- while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
- }
-
- // Switch over to PLL Clock source
- PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
-}
-
-static void use_default_clocks()
-{
- // Turn off the LFROSC
- AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
-
- // Use HFROSC
- use_hfrosc(4, 16);
-}
-
-static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
-{
- unsigned long start_mtime, delta_mtime;
- unsigned long mtime_freq = get_timer_freq();
-
- // Don't start measuruing until we see an mtime tick
- unsigned long tmp = mtime_lo();
- do {
- start_mtime = mtime_lo();
- } while (start_mtime == tmp);
-
- unsigned long start_mcycle = read_csr(mcycle);
-
- do {
- delta_mtime = mtime_lo() - start_mtime;
- } while (delta_mtime < n);
-
- unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
-
- return (delta_mcycle / delta_mtime) * mtime_freq
- + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
-}
-
-unsigned long get_cpu_freq()
-{
- static uint32_t cpu_freq;
-
- if (!cpu_freq) {
- // warm up I$
- measure_cpu_freq(1);
- // measure for real
- cpu_freq = measure_cpu_freq(10);
- }
-
- return cpu_freq;
-}
-
-static void uart_init(size_t baud_rate)
-{
- GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
- GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
- UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
- UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
-}
-
-
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
- if (0){
-#ifdef USE_PLIC
- // External Machine-Level interrupt from PLIC
- } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
- handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
- // External Machine-Level interrupt from PLIC
- } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
- handle_m_time_interrupt();
-#endif
- }
- else {
- write(1, "trap\n", 5);
- _exit(1 + mcause);
- }
- return epc;
-}
-
-void _init()
-{
-
- #ifndef NO_INIT
- use_default_clocks();
- use_pll(0, 0, 1, 31, 1);
- uart_init(115200);
-
- printf("core freq at %d Hz\n", get_cpu_freq());
-
- write_csr(mtvec, &trap_entry);
- if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
- write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
- write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
- }
- #endif
-
-}
-
-void _fini()
-{
-}
diff --git a/bsp/env/freedom-e300-hifive1/openocd.cfg b/bsp/env/freedom-e300-hifive1/openocd.cfg
deleted file mode 100644
index b531e9c..0000000
--- a/bsp/env/freedom-e300-hifive1/openocd.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
- #Wait for the reset stretcher
- #It will work without this, but
- #will incur lots of delays for later commands.
- sleep 1500
-}
-halt
-#flash protect 0 64 last off
diff --git a/bsp/env/freedom-e300-hifive1/platform.h b/bsp/env/freedom-e300-hifive1/platform.h
deleted file mode 100644
index 806fcfc..0000000
--- a/bsp/env/freedom-e300-hifive1/platform.h
+++ /dev/null
@@ -1,133 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-// Some things missing from the official encoding.h
-#define MCAUSE_INT 0x80000000
-#define MCAUSE_CAUSE 0x7FFFFFFF
-
-#include "sifive/const.h"
-#include "sifive/devices/aon.h"
-#include "sifive/devices/clint.h"
-#include "sifive/devices/gpio.h"
-#include "sifive/devices/otp.h"
-#include "sifive/devices/plic.h"
-#include "sifive/devices/prci.h"
-#include "sifive/devices/pwm.h"
-#include "sifive/devices/spi.h"
-#include "sifive/devices/uart.h"
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// Memory map
-#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
-#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
-#define OTP_MEM_ADDR _AC(0x00020000,UL)
-#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
-#define AON_CTRL_ADDR _AC(0x10000000,UL)
-#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
-#define OTP_CTRL_ADDR _AC(0x10010000,UL)
-#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
-#define UART0_CTRL_ADDR _AC(0x10013000,UL)
-#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
-#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
-#define UART1_CTRL_ADDR _AC(0x10023000,UL)
-#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
-#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
-#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
-#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
-#define SPI0_MEM_ADDR _AC(0x20000000,UL)
-#define MEM_CTRL_ADDR _AC(0x80000000,UL)
-
-// IOF masks
-#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
-#define SPI11_NUM_SS (4)
-#define IOF_SPI1_SS0 (2u)
-#define IOF_SPI1_SS1 (8u)
-#define IOF_SPI1_SS2 (9u)
-#define IOF_SPI1_SS3 (10u)
-#define IOF_SPI1_MOSI (3u)
-#define IOF_SPI1_MISO (4u)
-#define IOF_SPI1_SCK (5u)
-#define IOF_SPI1_DQ0 (3u)
-#define IOF_SPI1_DQ1 (4u)
-#define IOF_SPI1_DQ2 (6u)
-#define IOF_SPI1_DQ3 (7u)
-
-#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
-#define SPI2_NUM_SS (1)
-#define IOF_SPI2_SS0 (26u)
-#define IOF_SPI2_MOSI (27u)
-#define IOF_SPI2_MISO (28u)
-#define IOF_SPI2_SCK (29u)
-#define IOF_SPI2_DQ0 (27u)
-#define IOF_SPI2_DQ1 (28u)
-#define IOF_SPI2_DQ2 (30u)
-#define IOF_SPI2_DQ3 (31u)
-
-//#define IOF0_I2C_MASK _AC(0x00003000,UL)
-
-#define IOF0_UART0_MASK _AC(0x00030000, UL)
-#define IOF_UART0_RX (16u)
-#define IOF_UART0_TX (17u)
-
-#define IOF0_UART1_MASK _AC(0x03000000, UL)
-#define IOF_UART1_RX (24u)
-#define IOF_UART1_TX (25u)
-
-#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
-#define IOF1_PWM1_MASK _AC(0x00780000, UL)
-#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
-
-// Interrupt numbers
-#define INT_RESERVED 0
-#define INT_WDOGCMP 1
-#define INT_RTCCMP 2
-#define INT_UART0_BASE 3
-#define INT_UART1_BASE 4
-#define INT_SPI0_BASE 5
-#define INT_SPI1_BASE 6
-#define INT_SPI2_BASE 7
-#define INT_GPIO_BASE 8
-#define INT_PWM0_BASE 40
-#define INT_PWM1_BASE 44
-#define INT_PWM2_BASE 48
-
-// Helper functions
-#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
-#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
-#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
-#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
-#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
-#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
-#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
-#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
-#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
-#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
-#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
-#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
-
-// Misc
-
-#include <stdint.h>
-
-#define NUM_GPIO 32
-
-#define PLIC_NUM_INTERRUPTS 52
-#define PLIC_NUM_PRIORITIES 7
-
-#include "hifive1.h"
-
-unsigned long get_cpu_freq(void);
-unsigned long get_timer_freq(void);
-uint64_t get_timer_value(void);
-
-#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/freedom-e300-hifive1/settings.mk b/bsp/env/freedom-e300-hifive1/settings.mk
deleted file mode 100644
index 230fccc..0000000
--- a/bsp/env/freedom-e300-hifive1/settings.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-# Describes the CPU on this board to the rest of the SDK.
-RISCV_ARCH := rv32imac
-RISCV_ABI := ilp32
diff --git a/bsp/env/hifive1.h b/bsp/env/hifive1.h
deleted file mode 100644
index 0db2f0f..0000000
--- a/bsp/env/hifive1.h
+++ /dev/null
@@ -1,81 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_HIFIVE1_H
-#define _SIFIVE_HIFIVE1_H
-
-#include <stdint.h>
-
-/****************************************************************************
- * GPIO Connections
- *****************************************************************************/
-
-// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
-// These are also mapped to RGB LEDs on the Freedom E300 Arty
-// FPGA
-// Dev Kit.
-
-#define RED_LED_OFFSET 22
-#define GREEN_LED_OFFSET 19
-#define BLUE_LED_OFFSET 21
-
-// These are the GPIO bit offsets for the differen digital pins
-// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
-#define PIN_0_OFFSET 16
-#define PIN_1_OFFSET 17
-#define PIN_2_OFFSET 18
-#define PIN_3_OFFSET 19
-#define PIN_4_OFFSET 20
-#define PIN_5_OFFSET 21
-#define PIN_6_OFFSET 22
-#define PIN_7_OFFSET 23
-#define PIN_8_OFFSET 0
-#define PIN_9_OFFSET 1
-#define PIN_10_OFFSET 2
-#define PIN_11_OFFSET 3
-#define PIN_12_OFFSET 4
-#define PIN_13_OFFSET 5
-//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
-#define PIN_15_OFFSET 9
-#define PIN_16_OFFSET 10
-#define PIN_17_OFFSET 11
-#define PIN_18_OFFSET 12
-#define PIN_19_OFFSET 13
-
-// These are *PIN* numbers, not
-// GPIO Offset Numbers.
-#define PIN_SPI1_SCK (13u)
-#define PIN_SPI1_MISO (12u)
-#define PIN_SPI1_MOSI (11u)
-#define PIN_SPI1_SS0 (10u)
-#define PIN_SPI1_SS1 (14u)
-#define PIN_SPI1_SS2 (15u)
-#define PIN_SPI1_SS3 (16u)
-
-#define SS_PIN_TO_CS_ID(x) \
- ((x==PIN_SPI1_SS0 ? 0 : \
- (x==PIN_SPI1_SS1 ? 1 : \
- (x==PIN_SPI1_SS2 ? 2 : \
- (x==PIN_SPI1_SS3 ? 3 : \
- -1)))))
-
-
-// These buttons are present only on the Freedom E300 Arty Dev Kit.
-#ifdef HAS_BOARD_BUTTONS
-#define BUTTON_0_OFFSET 15
-#define BUTTON_1_OFFSET 30
-#define BUTTON_2_OFFSET 31
-
-#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
-#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
-#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
-
-#endif
-
-#define HAS_HFXOSC 1
-#define HAS_LFROSC_BYPASS 1
-
-#define RTC_FREQ 32768
-
-void write_hex(int fd, unsigned long int hex);
-
-#endif /* _SIFIVE_HIFIVE1_H */
diff --git a/bsp/env/start.S b/bsp/env/start.S
deleted file mode 100644
index 4d1eb04..0000000
--- a/bsp/env/start.S
+++ /dev/null
@@ -1,112 +0,0 @@
-// See LICENSE for license details.
-#include <sifive/smp.h>
-#include <encoding.h>
-
-/* This is defined in sifive/platform.h, but that can't be included from
- * assembly. */
-#define CLINT_CTRL_ADDR 0x02000000
-
- .section .init
- .globl _start
- .type _start,@function
-
-_start:
- .cfi_startproc
- .cfi_undefined ra
-.option push
-.option norelax
- la gp, __global_pointer$
-.option pop
- la sp, _sp
-
-#if defined(ENABLE_SMP)
- smp_pause(t0, t1)
-#endif
-
- /* Load data section */
- la a0, _data_lma
- la a1, _data
- la a2, _edata
- bgeu a1, a2, 2f
-1:
- lw t0, (a0)
- sw t0, (a1)
- addi a0, a0, 4
- addi a1, a1, 4
- bltu a1, a2, 1b
-2:
-
- /* Clear bss section */
- la a0, __bss_start
- la a1, _end
- bgeu a0, a1, 2f
-1:
- sw zero, (a0)
- addi a0, a0, 4
- bltu a0, a1, 1b
-2:
-
- /* Call global constructors */
- la a0, __libc_fini_array
- call atexit
- call __libc_init_array
-
-#ifndef __riscv_float_abi_soft
- /* Enable FPU */
- li t0, MSTATUS_FS
- csrs mstatus, t0
- csrr t1, mstatus
- and t1, t1, t0
- beqz t1, 1f
- fssr x0
-1:
-#endif
-
-#if defined(ENABLE_SMP)
- smp_resume(t0, t1)
-
- csrr a0, mhartid
- bnez a0, 2f
-#endif
-
- auipc ra, 0
- addi sp, sp, -16
-#if __riscv_xlen == 32
- sw ra, 8(sp)
-#else
- sd ra, 8(sp)
-#endif
-
- /* argc = argv = 0 */
- li a0, 0
- li a1, 0
- call main
- tail exit
-1:
- j 1b
-
-#if defined(ENABLE_SMP)
-2:
- la t0, trap_entry
- csrw mtvec, t0
-
- csrr a0, mhartid
- la t1, _sp
- slli t0, a0, 10
- sub sp, t1, t0
-
- auipc ra, 0
- addi sp, sp, -16
-#if __riscv_xlen == 32
- sw ra, 8(sp)
-#else
- sd ra, 8(sp)
-#endif
-
- call secondary_main
- tail exit
-
-1:
- j 1b
-#endif
- .cfi_endproc
diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S
deleted file mode 100644
index 5c82c48..0000000
--- a/bsp/env/ventry.S
+++ /dev/null
@@ -1,288 +0,0 @@
-// See LICENSE for license details
-
-#ifndef VENTRY_S
-#define VENTRY_S
-
-#include "encoding.h"
-#include "sifive/bits.h"
-
-#only save caller registers
-.macro TRAP_ENTRY
- addi sp, sp, -16*REGBYTES
-
- STORE x1, 0*REGBYTES(sp)
- STORE x5, 1*REGBYTES(sp)
- STORE x6, 2*REGBYTES(sp)
- STORE x7, 3*REGBYTES(sp)
- STORE x10, 4*REGBYTES(sp)
- STORE x11, 5*REGBYTES(sp)
- STORE x12, 6*REGBYTES(sp)
- STORE x13, 7*REGBYTES(sp)
- STORE x14, 8*REGBYTES(sp)
- STORE x15, 9*REGBYTES(sp)
- STORE x16, 10*REGBYTES(sp)
- STORE x17, 11*REGBYTES(sp)
- STORE x28, 12*REGBYTES(sp)
- STORE x29, 13*REGBYTES(sp)
- STORE x30, 14*REGBYTES(sp)
- STORE x31, 15*REGBYTES(sp)
-.endm
-
-#restore caller registers
-.macro TRAP_EXIT
-# Remain in M-mode after mret
- li t0, MSTATUS_MPP
- csrs mstatus, t0
-
- LOAD x1, 0*REGBYTES(sp)
- LOAD x5, 1*REGBYTES(sp)
- LOAD x6, 2*REGBYTES(sp)
- LOAD x7, 3*REGBYTES(sp)
- LOAD x10, 4*REGBYTES(sp)
- LOAD x11, 5*REGBYTES(sp)
- LOAD x12, 6*REGBYTES(sp)
- LOAD x13, 7*REGBYTES(sp)
- LOAD x14, 8*REGBYTES(sp)
- LOAD x15, 9*REGBYTES(sp)
- LOAD x16, 10*REGBYTES(sp)
- LOAD x17, 11*REGBYTES(sp)
- LOAD x28, 12*REGBYTES(sp)
- LOAD x29, 13*REGBYTES(sp)
- LOAD x30, 14*REGBYTES(sp)
- LOAD x31, 15*REGBYTES(sp)
-
- addi sp, sp, 16*REGBYTES
- mret
-.endm
-
-
-
-#Vector table for E31/E51
-
- .section .text.entry
- .align 8
- .global vtrap_entry
-vtrap_entry:
- j sync_trap
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j vmsi_Handler
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j vmti_Handler
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j vmei_Handler
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j reserved
- .align 2
- j vlip_Handler0
- .align 2
- j vlip_Handler1
- .align 2
- j vlip_Handler2
- .align 2
- j vlip_Handler3
- .align 2
- j vlip_Handler4
- .align 2
- j vlip_Handler5
- .align 2
- j vlip_Handler6
- .align 2
- j vlip_Handler7
- .align 2
- j vlip_Handler8
- .align 2
- j vlip_Handler9
- .align 2
- j vlip_Handler10
- .align 2
- j vlip_Handler11
- .align 2
- j vlip_Handler12
- .align 2
- j vlip_Handler13
- .align 2
- j vlip_Handler14
- .align 2
- j vlip_Handler15
-
-#synchronous trap
-sync_trap:
- TRAP_ENTRY
- jal handle_sync_trap
- TRAP_EXIT
-
-#Machine Software Interrupt
-vmsi_Handler:
- TRAP_ENTRY
- jal reserved
- TRAP_EXIT
-
-#Machine Timer Interrupt
-vmti_Handler:
- TRAP_ENTRY
- jal handle_m_time_interrupt
- TRAP_EXIT
-
-#Machine External Interrupt
-vmei_Handler:
- TRAP_ENTRY
- jal handle_m_external_interrupt
- TRAP_EXIT
-
-#LIP0
-vlip_Handler0:
- TRAP_ENTRY
- jal handle_local_interrupt0
- TRAP_EXIT
-
-#LIP1
-vlip_Handler1:
- TRAP_ENTRY
- jal handle_local_interrupt1
- TRAP_EXIT
-
-#LIP2
-vlip_Handler2:
- TRAP_ENTRY
- jal handle_local_interrupt2
- TRAP_EXIT
-
-#LIP3
-vlip_Handler3:
- TRAP_ENTRY
- jal handle_local_interrupt3
- TRAP_EXIT
-
-#LIP4
-vlip_Handler4:
- TRAP_ENTRY
- jal handle_local_interrupt4
- TRAP_EXIT
-
-#LIP5
-vlip_Handler5:
- TRAP_ENTRY
- jal handle_local_interrupt5
- TRAP_EXIT
-
-#LIP6
-vlip_Handler6:
- TRAP_ENTRY
- jal handle_local_interrupt6
- TRAP_EXIT
-
-#LIP7
-vlip_Handler7:
- TRAP_ENTRY
- jal handle_local_interrupt7
- TRAP_EXIT
-
-#LIP8
-vlip_Handler8:
- TRAP_ENTRY
- jal handle_local_interrupt8
- TRAP_EXIT
-
-#LIP9
-vlip_Handler9:
- TRAP_ENTRY
- jal handle_local_interrupt9
- TRAP_EXIT
-
-#LIP10
-vlip_Handler10:
- TRAP_ENTRY
- jal handle_local_interrupt10
- TRAP_EXIT
-
-#LIP11
-vlip_Handler11:
- TRAP_ENTRY
- jal handle_local_interrupt11
- TRAP_EXIT
-
-#LIP12
-vlip_Handler12:
- TRAP_ENTRY
- jal handle_local_interrupt12
- TRAP_EXIT
-
-#LIP13
-vlip_Handler13:
- TRAP_ENTRY
- jal handle_local_interrupt13
- TRAP_EXIT
-
-#LIP14
-vlip_Handler14:
- TRAP_ENTRY
- jal handle_local_interrupt14
- TRAP_EXIT
-
-#LIP15
-vlip_Handler15:
- TRAP_ENTRY
- jal handle_local_interrupt15
- TRAP_EXIT
-
-#unimplemented ISRs trap here
-.weak reserved
-reserved:
-.weak handle_local_interrupt0
-handle_local_interrupt0:
-.weak handle_local_interrupt1
-handle_local_interrupt1:
-.weak handle_local_interrupt2
-handle_local_interrupt2:
-.weak handle_local_interrupt3
-handle_local_interrupt3:
-.weak handle_local_interrupt4
-handle_local_interrupt4:
-.weak handle_local_interrupt5
-handle_local_interrupt5:
-.weak handle_local_interrupt6
-handle_local_interrupt6:
-.weak handle_local_interrupt7
-handle_local_interrupt7:
-.weak handle_local_interrupt8
-handle_local_interrupt8:
-.weak handle_local_interrupt9
-handle_local_interrupt9:
-.weak handle_local_interrupt10
-handle_local_interrupt10:
-.weak handle_local_interrupt11
-handle_local_interrupt11:
-.weak handle_local_interrupt12
-handle_local_interrupt12:
-.weak handle_local_interrupt13
-handle_local_interrupt13:
-.weak handle_local_interrupt14
-handle_local_interrupt14:
-.weak handle_local_interrupt15
-handle_local_interrupt15:
-1:
- j 1b
-
-#endif