diff options
| author | cgsfv <cgsfv@users.noreply.github.com> | 2019-06-05 23:26:40 +0200 |
|---|---|---|
| committer | cgsfv <cgsfv@users.noreply.github.com> | 2019-06-05 23:26:40 +0200 |
| commit | 43c3d481f420f929de1e05dfe7169edd1dbe110b (patch) | |
| tree | 773084ab939d2d386ab3c98449564a9e80bd73d4 /bsp/qemu-sifive-s51/README.md | |
| parent | f2c7f75ceef24aec9891d75c2b4fb5db5b847868 (diff) | |
Adding QEMU BSP's for E31 and S51 targets
Diffstat (limited to 'bsp/qemu-sifive-s51/README.md')
| -rw-r--r-- | bsp/qemu-sifive-s51/README.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md new file mode 100644 index 0000000..64593f3 --- /dev/null +++ b/bsp/qemu-sifive-s51/README.md @@ -0,0 +1,12 @@ +SiFive QEMU S51 is a virtual development platform matching the Freedom S510. It’s the best way to start prototyping and developing your RISC‑V applications. + +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS |