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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-14 16:49:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-14 16:49:17 +0000 |
| commit | 8002c66bf83ab6321494904c082cd1d03e799493 (patch) | |
| tree | feb5c1aadd486f522e50db4873d49d360bc33493 /bsp/qemu-sifive-s51/README.md | |
| parent | dac5d29f1c55fd43d9b95e8bc0acc7eadad6799a (diff) | |
| parent | 7ad24f2558984dcf03cf58b6fc90431067e78901 (diff) | |
Merge pull request #270 from sifive/qemu-integration
Adding QEMU BSP's for E31 and S51 targets
Diffstat (limited to 'bsp/qemu-sifive-s51/README.md')
| -rw-r--r-- | bsp/qemu-sifive-s51/README.md | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md new file mode 100644 index 0000000..7825a98 --- /dev/null +++ b/bsp/qemu-sifive-s51/README.md @@ -0,0 +1,14 @@ +SiFive QEMU S51 is a virtual development platform matching the Freedom S510. It’s the best way to start prototyping and developing your RISC‑V applications. + +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS + +This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1 |