Update BSP files to pickup inline support

6 files changed, 1021 insertions, 411 deletions

diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h
new file mode 100644
index 0000000..6968bab
--- /dev/null
+++ b/bsp/sifive-hifive-unleashed/metal-inline.h
@@ -0,0 +1,345 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_INLINE_H
+#define SIFIVE_HIFIVE_UNLEASHED__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+extern inline struct metal_clock * __metal_driver_fixed_factor_clock_parent(struct metal_clock *clock);
+extern inline unsigned long __metal_driver_fixed_factor_clock_mult(struct metal_clock *clock);
+extern inline unsigned long __metal_driver_fixed_factor_clock_div(struct metal_clock *clock);
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From refclk */
+struct __metal_driver_fixed_clock __metal_dt_refclk = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+/* From tlclk */
+struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = {
+    .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_1000000 = {
+    ._base_address = 16777216UL,
+    ._size = 8192UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1800000 = {
+    ._base_address = 25165824UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1808000 = {
+    ._base_address = 25198592UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1810000 = {
+    ._base_address = 25231360UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1818000 = {
+    ._base_address = 25264128UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1820000 = {
+    ._base_address = 25296896UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 135291469824UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10040000 = {
+    ._base_address = 536870912UL,
+    ._size = 268435456UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10041000 = {
+    ._base_address = 805306368UL,
+    ._size = 268435456UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10050000 = {
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@1 */
+struct __metal_driver_cpu __metal_dt_cpu_1 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@2 */
+struct __metal_driver_cpu __metal_dt_cpu_2 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@3 */
+struct __metal_driver_cpu __metal_dt_cpu_3 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@4 */
+struct __metal_driver_cpu __metal_dt_cpu_4 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From gpio@10060000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From spi@10040000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From spi@10041000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From spi@10050000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@10010000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+/* From serial@10011000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+/* From cache_controller@2010000 */
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
+    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
+};
+
+
+#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h
index db4360e..0a1d909 100644
--- a/bsp/sifive-hifive-unleashed/metal-platform.h
+++ b/bsp/sifive-hifive-unleashed/metal-platform.h
@@ -3,18 +3,23 @@
 
 /* From refclk */
 #define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 33333333UL
 
 #define METAL_FIXED_CLOCK
 
 /* From tlclk */
 #define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL
+#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_DIV 2UL
 #define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL
+#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_MULT 1UL
 
 #define METAL_FIXED_FACTOR_CLOCK
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -23,9 +28,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 54UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 54UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -36,12 +45,25 @@
 
 /* From pmp@0 */
 #define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
+#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
 
 #define METAL_RISCV_PMP
 
+/* From cache_controller@2010000 */
+#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL
+#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL
+
+#define METAL_SIFIVE_FU540_C000_L2
+#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL
+#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL
+
 /* From gpio@10060000 */
 #define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268828672UL
 #define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -62,17 +84,59 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From i2c@10030000 */
+#define METAL_SIFIVE_I2C0_10030000_BASE_ADDRESS 268632064UL
+#define METAL_SIFIVE_I2C0_0_BASE_ADDRESS 268632064UL
+#define METAL_SIFIVE_I2C0_10030000_SIZE 4096UL
+#define METAL_SIFIVE_I2C0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_I2C0
+#define METAL_SIFIVE_I2C0_PRESCALE_LOW 0UL
+#define METAL_SIFIVE_I2C0_PRESCALE_HIGH 4UL
+#define METAL_SIFIVE_I2C0_CONTROL 8UL
+#define METAL_SIFIVE_I2C0_TRANSMIT 12UL
+#define METAL_SIFIVE_I2C0_RECEIVE 12UL
+#define METAL_SIFIVE_I2C0_COMMAND 16UL
+#define METAL_SIFIVE_I2C0_STATUS 16UL
+
+/* From pwm@10020000 */
+#define METAL_SIFIVE_PWM0_10020000_BASE_ADDRESS 268566528UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 268566528UL
+#define METAL_SIFIVE_PWM0_10020000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+/* From pwm@10021000 */
+#define METAL_SIFIVE_PWM0_10021000_BASE_ADDRESS 268570624UL
+#define METAL_SIFIVE_PWM0_1_BASE_ADDRESS 268570624UL
+#define METAL_SIFIVE_PWM0_10021000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_1_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@10040000 */
 #define METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS 268697600UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 268697600UL
 #define METAL_SIFIVE_SPI0_10040000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 /* From spi@10041000 */
 #define METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS 268701696UL
+#define METAL_SIFIVE_SPI0_1_BASE_ADDRESS 268701696UL
 #define METAL_SIFIVE_SPI0_10041000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_1_SIZE 4096UL
 
 /* From spi@10050000 */
 #define METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS 268763136UL
+#define METAL_SIFIVE_SPI0_2_BASE_ADDRESS 268763136UL
 #define METAL_SIFIVE_SPI0_10050000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_2_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -94,18 +158,24 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@10010000 */
 #define METAL_SIFIVE_UART0_10010000_BASE_ADDRESS 268500992UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268500992UL
 #define METAL_SIFIVE_UART0_10010000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 /* From serial@10011000 */
 #define METAL_SIFIVE_UART0_10011000_BASE_ADDRESS 268505088UL
+#define METAL_SIFIVE_UART0_1_BASE_ADDRESS 268505088UL
 #define METAL_SIFIVE_UART0_10011000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_1_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds
index 61b2203..b4c68be 100644
--- a/bsp/sifive-hifive-unleashed/metal.default.lds
+++ b/bsp/sifive-hifive-unleashed/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h
index 118bdd3..e72a3db 100644
--- a/bsp/sifive-hifive-unleashed/metal.h
+++ b/bsp/sifive-hifive-unleashed/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H
-#define SIFIVE_HIFIVE_UNLEASHED__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+#define MACROS_IF_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 10
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_SIFIVE_HIFIVE_UNLEASHED__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+#define MACROS_ELSE_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 10
 
 #define METAL_MAX_CLINT_INTERRUPTS 10
@@ -74,495 +85,655 @@
 #include <metal/drivers/sifive,fu540-c000,l2.h>
 
 /* From refclk */
-asm (".weak __metal_dt_refclk");
 struct __metal_driver_fixed_clock __metal_dt_refclk;
 
 /* From tlclk */
-asm (".weak __metal_dt_tlclk");
 struct __metal_driver_fixed_factor_clock __metal_dt_tlclk;
 
-asm (".weak __metal_dt_mem_dtim_1000000");
 struct metal_memory __metal_dt_mem_dtim_1000000;
 
-asm (".weak __metal_dt_mem_itim_1800000");
 struct metal_memory __metal_dt_mem_itim_1800000;
 
-asm (".weak __metal_dt_mem_itim_1808000");
 struct metal_memory __metal_dt_mem_itim_1808000;
 
-asm (".weak __metal_dt_mem_itim_1810000");
 struct metal_memory __metal_dt_mem_itim_1810000;
 
-asm (".weak __metal_dt_mem_itim_1818000");
 struct metal_memory __metal_dt_mem_itim_1818000;
 
-asm (".weak __metal_dt_mem_itim_1820000");
 struct metal_memory __metal_dt_mem_itim_1820000;
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
-asm (".weak __metal_dt_mem_spi_10040000");
 struct metal_memory __metal_dt_mem_spi_10040000;
 
-asm (".weak __metal_dt_mem_spi_10041000");
 struct metal_memory __metal_dt_mem_spi_10041000;
 
-asm (".weak __metal_dt_mem_spi_10050000");
 struct metal_memory __metal_dt_mem_spi_10050000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
 /* From cpu@1 */
-asm (".weak __metal_dt_cpu_1");
 struct __metal_driver_cpu __metal_dt_cpu_1;
 
 /* From cpu@2 */
-asm (".weak __metal_dt_cpu_2");
 struct __metal_driver_cpu __metal_dt_cpu_2;
 
 /* From cpu@3 */
-asm (".weak __metal_dt_cpu_3");
 struct __metal_driver_cpu __metal_dt_cpu_3;
 
 /* From cpu@4 */
-asm (".weak __metal_dt_cpu_4");
 struct __metal_driver_cpu __metal_dt_cpu_4;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_1_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_2_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_3_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_4_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From gpio@10060000 */
-asm (".weak __metal_dt_gpio_10060000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000;
 
 /* From spi@10040000 */
-asm (".weak __metal_dt_spi_10040000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000;
 
 /* From spi@10041000 */
-asm (".weak __metal_dt_spi_10041000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000;
 
 /* From spi@10050000 */
-asm (".weak __metal_dt_spi_10050000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@10010000 */
-asm (".weak __metal_dt_serial_10010000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000;
 
 /* From serial@10011000 */
-asm (".weak __metal_dt_serial_10011000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000;
 
 /* From cache_controller@2010000 */
-asm (".weak __metal_dt_cache_controller_2010000");
 struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
 
 
-/* From refclk */
-struct __metal_driver_fixed_clock __metal_dt_refclk = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
-};
 
-/* From tlclk */
-struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = {
-    .vtable = &__metal_driver_vtable_fixed_factor_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock,
-/* From refclk */
-    .parent = &__metal_dt_refclk.clock,
-    .mult = METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT,
-    .div = METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV,
-};
-
-struct metal_memory __metal_dt_mem_dtim_1000000 = {
-    ._base_address = 16777216UL,
-    ._size = 8192UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1800000 = {
-    ._base_address = 25165824UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1808000 = {
-    ._base_address = 25198592UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1810000 = {
-    ._base_address = 25231360UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1818000 = {
-    ._base_address = 25264128UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1820000 = {
-    ._base_address = 25296896UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 135291469824UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10040000 = {
-    ._base_address = 536870912UL,
-    ._size = 268435456UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10041000 = {
-    ._base_address = 805306368UL,
-    ._size = 268435456UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10050000 = {
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_refclk) {
+		return METAL_FIXED_CLOCK__CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+static inline struct metal_clock * __metal_driver_fixed_factor_clock_parent(struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_refclk.clock;
+}
+
+static inline unsigned long __metal_driver_fixed_factor_clock_mult(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_tlclk) {
+		return METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_fixed_factor_clock_div(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_tlclk) {
+		return METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 2) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 3) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 4) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 5) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 6) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 7) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 8) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else if (idx == 9) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 7;
+	}
+	else if (idx == 4) {
+		return 3;
+	}
+	else if (idx == 5) {
+		return 7;
+	}
+	else if (idx == 6) {
+		return 3;
+	}
+	else if (idx == 7) {
+		return 7;
+	}
+	else if (idx == 8) {
+		return 3;
+	}
+	else if (idx == 9) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+		return &__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+		return &__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+		return &__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 2) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 3) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 4) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 5) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 6) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 7) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else if (idx == 8) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 1) {
+		return 11;
+	}
+	else if (idx == 2) {
+		return 9;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else if (idx == 4) {
+		return 9;
+	}
+	else if (idx == 5) {
+		return 11;
+	}
+	else if (idx == 6) {
+		return 9;
+	}
+	else if (idx == 7) {
+		return 11;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 0)) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 1))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 2))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 3))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 4))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 5))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 6))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 7))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 8))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 9))) {
+		return 16;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 10))) {
+		return 17;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 11))) {
+		return 18;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 12))) {
+		return 19;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 13))) {
+		return 20;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 14))) {
+		return 21;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 15))) {
+		return 22;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10040000) {
+		return METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10040000) {
+		return METAL_SIFIVE_SPI0_10040000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return METAL_SIFIVE_UART0_10010000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return METAL_SIFIVE_UART0_10010000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[2] = 3,
-    .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[3] = 7,
-    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[4] = 3,
-    .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[5] = 7,
-    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[6] = 3,
-    .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[7] = 7,
-    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[8] = 3,
-    .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[9] = 7,
-};
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From cpu@1 */
-struct __metal_driver_cpu __metal_dt_cpu_1 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 4;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
 
-/* From cpu@2 */
-struct __metal_driver_cpu __metal_dt_cpu_2 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From cpu@3 */
-struct __metal_driver_cpu __metal_dt_cpu_3 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From cpu@4 */
-struct __metal_driver_cpu __metal_dt_cpu_4 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[1] = 11,
-    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[2] = 9,
-    .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[3] = 11,
-    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[4] = 9,
-    .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[5] = 11,
-    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[6] = 9,
-    .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[7] = 11,
-    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[8] = 9,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
 
-/* From gpio@10060000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 7,
-    .interrupt_lines[1] = 8,
-    .interrupt_lines[2] = 9,
-    .interrupt_lines[3] = 10,
-    .interrupt_lines[4] = 11,
-    .interrupt_lines[5] = 12,
-    .interrupt_lines[6] = 13,
-    .interrupt_lines[7] = 14,
-    .interrupt_lines[8] = 15,
-    .interrupt_lines[9] = 16,
-    .interrupt_lines[10] = 17,
-    .interrupt_lines[11] = 18,
-    .interrupt_lines[12] = 19,
-    .interrupt_lines[13] = 20,
-    .interrupt_lines[14] = 21,
-    .interrupt_lines[15] = 22,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From spi@10040000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10040000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
 
-/* From spi@10041000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10041000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From spi@10050000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10050000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From serial@10010000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10010000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10010000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 4UL,
-};
 
-/* From serial@10011000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10011000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10011000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 5UL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
-    .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2,
-    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 9
@@ -643,7 +814,13 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+/* From cache_controller@2010000 */
+#define __METAL_DT_SIFIVE_FU540_C000_L2_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#define __METAL_DT_CACHE_CONTROLLER_2010000_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#endif /* MACROS_ELSE_SIFIVE_HIFIVE_UNLEASHED__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
index b57aaf7..3301bb0 100644
--- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
+++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
index f145bc7..cf43226 100644
--- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
+++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init