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| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-05-24 10:22:08 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-24 10:22:08 +0800 |
| commit | faf58a49c3b6421107ada0e8af43170a5ffafcea (patch) | |
| tree | 3996d52a748ae2420b5c9c6c9efe4158d5dece53 /bsp/sifive-hifive1-revb/design.dts | |
| parent | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (diff) | |
| parent | 2c0269905929128bd0bd13a55ae3d8afd60a1af6 (diff) | |
Merge branch 'development-19.05' into dhrystone_19.05
Diffstat (limited to 'bsp/sifive-hifive1-revb/design.dts')
| -rw-r--r-- | bsp/sifive-hifive1-revb/design.dts | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/bsp/sifive-hifive1-revb/design.dts b/bsp/sifive-hifive1-revb/design.dts index 0e48622..970d3be 100644 --- a/bsp/sifive-hifive1-revb/design.dts +++ b/bsp/sifive-hifive1-revb/design.dts @@ -25,6 +25,7 @@ next-level-cache = <&spi0>; reg = <0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <8>; sifive,dtim = <&dtim>; status = "okay"; timebase-frequency = <1000000>; @@ -43,12 +44,6 @@ #clock-cells = <1>; compatible = "sifive,hifive1"; ranges; - - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; - hfxoscin: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; |