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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-06-05 19:52:44 +0000
committerGitHub <noreply@github.com>2019-06-05 19:52:44 +0000
commite11e2a064dd91a11296a69192ae70f3418141d5a (patch)
tree49702719af2957816014986a7828f0251db38598 /bsp/sifive-hifive1-revb/design.reglist
parent78b48aac4add3ba3a8a46eafa2b8c8cde065d1f2 (diff)
parentd29a5d443cabe9373016bb158203c9dcd6f32279 (diff)
Merge pull request #266 from sifive/fixup-arty-metal-entry
Detect when we need to add metal,entry for FPGA targets
Diffstat (limited to 'bsp/sifive-hifive1-revb/design.reglist')
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