Update BSPs for platform header

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

2 files changed, 134 insertions, 22 deletions

diff --git a/bsp/sifive-hifive1-revb/metal-platform.h b/bsp/sifive-hifive1-revb/metal-platform.h
new file mode 100644
index 0000000..ae992ff
--- /dev/null
+++ b/bsp/sifive-hifive1-revb/metal-platform.h
@@ -0,0 +1,110 @@
+#ifndef SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H
+#define SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 16000000UL
+
+/* From clock@2 */
+#define METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY 72000000UL
+
+/* From clock@5 */
+#define METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY 32000000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From prci@10008000 */
+#define METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS 268468224UL
+#define METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE 32768UL
+
+#define METAL_SIFIVE_FE310_G000_PRCI
+#define METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG 0UL
+#define METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG 4UL
+#define METAL_SIFIVE_FE310_G000_PRCI_PLLCFG 8UL
+#define METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV 12UL
+
+/* From gpio@10012000 */
+#define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@10014000 */
+#define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From serial@10013000 */
+#define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H*/
diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h
index 82bfd01..330f08e 100644
--- a/bsp/sifive-hifive1-revb/metal.h
+++ b/bsp/sifive-hifive1-revb/metal.h
@@ -3,6 +3,8 @@
 #ifndef SIFIVE_HIFIVE1_REVB__METAL_H
 #define SIFIVE_HIFIVE1_REVB__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -159,21 +161,21 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 16000000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 /* From clock@2 */
 struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 72000000UL,
+    .rate = METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY,
 };
 
 /* From clock@5 */
 struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32000000UL,
+    .rate = METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -202,8 +204,8 @@ struct metal_memory __metal_dt_mem_spi_10014000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -235,16 +237,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
@@ -276,8 +278,8 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268509184UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -333,8 +335,8 @@ struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268517376UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
 /* From clock@4 */
     .clock = &__metal_dt_clock_4.clock,
 /* From gpio@10012000 */
@@ -347,8 +349,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 268513280UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
 /* From clock@4 */
     .clock = &__metal_dt_clock_4.clock,
 /* From gpio@10012000 */
@@ -369,7 +371,7 @@ struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
     .ref = &__metal_dt_clock_2.clock,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 0UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG,
 };
 
 /* From clock@1 */
@@ -380,7 +382,7 @@ struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
     .ref = &__metal_dt_clock_0.clock,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 4UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG,
 };
 
 /* From clock@4 */
@@ -393,18 +395,18 @@ struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
     .pllref = &__metal_dt_clock_1.clock,
 /* From prci@10008000 */
     .divider_base = &__metal_dt_prci_10008000,
-    .divider_offset = 12UL,
+    .divider_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 8UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLCFG,
     .init_rate = 16000000UL,
 };
 
 /* From prci@10008000 */
 struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
     .vtable = &__metal_driver_vtable_sifive_fe310_g000_prci,
-    .base = 268468224UL,
-    .size = 32768UL,
+    .base = METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE,
 };