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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-01-07 19:06:03 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-07 19:06:03 +0000 |
| commit | 7a965490cc35a8f9880f0a7d15a28a5dfb954bfd (patch) | |
| tree | fd8ceb059aa13860b39ec536013373339d863fba /bsp/sifive-hifive1/design.dts | |
| parent | 1a8f64bd33401e2f7b743558b3453ec30a092c9a (diff) | |
| parent | 2139efac01f4bd8826eeec3cf5a60ffaf4d5c942 (diff) | |
Merge pull request #127 from sifive/itim
Add an ITIM example
Diffstat (limited to 'bsp/sifive-hifive1/design.dts')
| -rw-r--r-- | bsp/sifive-hifive1/design.dts | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts index a71956a..26e4048 100644 --- a/bsp/sifive-hifive1/design.dts +++ b/bsp/sifive-hifive1/design.dts @@ -26,7 +26,6 @@ reg = <0>; riscv,isa = "rv32imac"; sifive,dtim = <&dtim>; - sifive,itim = <&itim>; status = "okay"; timebase-frequency = <1000000>; hlic: interrupt-controller { @@ -147,11 +146,6 @@ reg = <0x80000000 0x4000>; reg-names = "mem"; }; - itim: itim@8000000 { - compatible = "sifive,itim0"; - reg = <0x8000000 0x4000>; - reg-names = "mem"; - }; pwm@10015000 { compatible = "sifive,pwm0"; |