diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2018-12-13 14:03:18 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-12-13 18:14:36 -0800 |
| commit | 7202b8ed15a46645de54906f0f08c7f7e9b5e654 (patch) | |
| tree | fc09705176c45061dbea8a77df1359c0e82d82e3 /bsp/sifive-hifive1/openocd.cfg | |
| parent | cc139c77212bd1c8bf306048539eef20ad955f9a (diff) | |
Add MEE BSP for SiFive HiFive1
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/sifive-hifive1/openocd.cfg')
| -rw-r--r-- | bsp/sifive-hifive1/openocd.cfg | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/bsp/sifive-hifive1/openocd.cfg b/bsp/sifive-hifive1/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/bsp/sifive-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off |