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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-05 23:44:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 23:44:22 +0000 |
| commit | 3e51e0289ec728b6ff6dcf90bb8ddcb50c24cb04 (patch) | |
| tree | 722614f1613432a0aeb440fa0000bd4356dcbd2e /bsp/sifive-hifive1 | |
| parent | 39ea32d9f14d786d8457ef2e30b0bceb2e5729ce (diff) | |
| parent | 32ca53e7340922b1fa0aa379788430004504a2de (diff) | |
Merge pull request #188 from sifive/hifive1-revb
Add HiFive1 RevB Support
Diffstat (limited to 'bsp/sifive-hifive1')
| -rw-r--r-- | bsp/sifive-hifive1/README.md | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index 6311207..d0d0c7a 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -4,7 +4,6 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines |