Add MEE BSP for SiFive HiFive1

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

5 files changed, 551 insertions, 0 deletions

diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts
new file mode 100644
index 0000000..a71956a
--- /dev/null
+++ b/bsp/sifive-hifive1/design.dts
@@ -0,0 +1,187 @@
+/dts-v1/;
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "sifive,hifive1";
+        model = "sifive,hifive1";
+
+        chosen {
+                stdout-path = "/soc/serial@10013000:115200";
+                mee,entry = <&sip0 0x400000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "sifive,fe310-g000";
+                L6: cpu@0 {
+                        clocks = <&hfclk>;
+                        compatible = "sifive,rocket0", "riscv";
+                        device_type = "cpu";
+                        i-cache-block-size = <64>;
+                        i-cache-sets = <128>;
+                        i-cache-size = <16384>;
+                        next-level-cache = <&sip0>;
+                        reg = <0>;
+                        riscv,isa = "rv32imac";
+                        sifive,dtim = <&dtim>;
+                        sifive,itim = <&itim>;
+                        status = "okay";
+                        timebase-frequency = <1000000>;
+                        hlic: interrupt-controller {
+                                #interrupt-cells = <1>;
+                                compatible = "riscv,cpu-intc";
+                                interrupt-controller;
+                        };
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                #clock-cells = <1>;
+                compatible = "sifive,hifive1";
+                ranges;
+
+                hfxoscin: clock@0 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <16000000>;
+                };
+                hfxoscout: clock@1 {
+                        compatible = "sifive,fe310-g000,hfxosc";
+                        clocks = <&hfxoscin>;
+                        reg = <&prci 0x4>;
+                        reg-names = "config";
+                };
+                hfroscin: clock@2 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <72000000>;
+                };
+                hfroscout: clock@3 {
+                        compatible = "sifive,fe310-g000,hfrosc";
+                        clocks = <&hfroscin>;
+                        reg = <&prci 0x0>;
+                        reg-names = "config";
+                };
+                hfclk: clock@4 {
+                        compatible = "sifive,fe310-g000,pll";
+                        clocks = <&hfxoscout &hfroscout>;
+                        clock-names = "pllref", "pllsel0";
+                        reg = <&prci 0x8 &prci 0xc>;
+                        reg-names = "config", "divider";
+			clock-frequency = <16000000>;
+                };
+
+                lfroscin: clock@5 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000000>;
+                };
+                lfclk: clock@6 {
+                        compatible = "sifive,fe310-g000,lfrosc";
+                        clocks = <&lfroscin>;
+                        reg = <&aon 0x70>;
+                        reg-names = "config";
+                };
+
+                aon: aon@10000000 {
+                        compatible = "sifive,aon0";
+                        reg = <0x10000000 0x8000>;
+                        reg-names = "mem";
+                };
+
+                prci: prci@10008000 {
+                        compatible = "sifive,fe310-g000,prci";
+                        reg = <0x10008000 0x8000>;
+                        reg-names = "mem";
+                };
+
+                clint: clint@2000000 {
+                        compatible = "riscv,clint0";
+                        interrupts-extended = <&hlic 3 &hlic 7>;
+                        reg = <0x2000000 0x10000>;
+                        reg-names = "control";
+                };
+                local-external-interrupts-0 {
+                        compatible = "sifive,local-external-interrupts0";
+                        interrupt-parent = <&hlic>;
+                        interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
+                };
+                plic: interrupt-controller@c000000 {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,plic0";
+                        interrupt-controller;
+                        interrupts-extended = <&hlic 11>;
+                        reg = <0xc000000 0x4000000>;
+                        reg-names = "control";
+                        riscv,max-priority = <7>;
+                        riscv,ndev = <26>;
+                };
+                global-external-interrupts {
+                        compatile = "sifive,global-external-interrupts0";
+                        interrupt-parent = <&plic>;
+                        interrupts = <1 2 3 4>;
+                };
+
+                debug-controller@0 {
+                        compatible = "sifive,debug-011", "riscv,debug-011";
+                        interrupts-extended = <&hlic 65535>;
+                        reg = <0x0 0x100>;
+                        reg-names = "control";
+                };
+
+                maskrom@1000 {
+                        reg = <0x1000 0x2000>;
+                        reg-names = "mem";
+                };
+                otp@20000 {
+                        reg = <0x20000 0x2000 0x10010000 0x1000>;
+                        reg-names = "mem", "control";
+                };
+
+                dtim: dtim@80000000 {
+                        compatible = "sifive,dtim0";
+                        reg = <0x80000000 0x4000>;
+                        reg-names = "mem";
+                };
+                itim: itim@8000000 {
+                        compatible = "sifive,itim0";
+                        reg = <0x8000000 0x4000>;
+                        reg-names = "mem";
+                };
+
+                pwm@10015000 {
+                        compatible = "sifive,pwm0";
+                        interrupt-parent = <&plic>;
+                        interrupts = <23 24 25 26>;
+                        reg = <0x10015000 0x1000>;
+                        reg-names = "control";
+                };
+                gpio0: gpio@10012000 {
+                        compatible = "sifive,gpio0";
+                        interrupt-parent = <&plic>;
+                        interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
+                        reg = <0x10012000 0x1000>;
+                        reg-names = "control";
+                };
+                uart0: serial@10013000 {
+                        compatible = "sifive,uart0";
+                        interrupt-parent = <&plic>;
+                        interrupts = <5>;
+                        reg = <0x10013000 0x1000>;
+                        reg-names = "control";
+                        clocks = <&hfclk>;
+                        pinmux = <&gpio0 0x30000 0x30000>;
+                };
+                sip0: spi@10014000 {
+                        compatible = "sifive,spi0";
+                        interrupt-parent = <&plic>;
+                        interrupts = <6>;
+                        reg = <0x10014000 0x1000 0x20000000 0x20000000>;
+                        reg-names = "control", "mem";
+                };
+        };
+};
diff --git a/bsp/sifive-hifive1/mee.h b/bsp/sifive-hifive1/mee.h
new file mode 100644
index 0000000..e220490
--- /dev/null
+++ b/bsp/sifive-hifive1/mee.h
@@ -0,0 +1,138 @@
+#ifndef ASSEMBLY
+#include <mee/drivers/fixed-clock.h>
+#include <mee/drivers/sifive,fe310-g000,pll.h>
+#include <mee/drivers/sifive,fe310-g000,prci.h>
+#include <mee/drivers/sifive,fe310-g000,hfxosc.h>
+#include <mee/drivers/sifive,fe310-g000,hfrosc.h>
+#include <mee/drivers/sifive,gpio0.h>
+#include <mee/drivers/sifive,uart0.h>
+/* From clock@0 */
+asm (".weak __mee_dt_clock_0");
+struct __mee_driver_fixed_clock __mee_dt_clock_0;
+
+/* From clock@2 */
+asm (".weak __mee_dt_clock_2");
+struct __mee_driver_fixed_clock __mee_dt_clock_2;
+
+/* From clock@5 */
+asm (".weak __mee_dt_clock_5");
+struct __mee_driver_fixed_clock __mee_dt_clock_5;
+
+/* From clock@4 */
+asm (".weak __mee_dt_clock_4");
+struct __mee_driver_sifive_fe310_g000_pll __mee_dt_clock_4;
+
+/* From prci@10008000 */
+asm (".weak __mee_dt_prci_10008000");
+struct __mee_driver_sifive_fe310_g000_prci __mee_dt_prci_10008000;
+
+/* From clock@1 */
+asm (".weak __mee_dt_clock_1");
+struct __mee_driver_sifive_fe310_g000_hfxosc __mee_dt_clock_1;
+
+/* From clock@3 */
+asm (".weak __mee_dt_clock_3");
+struct __mee_driver_sifive_fe310_g000_hfrosc __mee_dt_clock_3;
+
+/* From gpio@10012000 */
+asm (".weak __mee_dt_gpio_10012000");
+struct __mee_driver_sifive_gpio0 __mee_dt_gpio_10012000;
+
+/* From serial@10013000 */
+asm (".weak __mee_dt_serial_10013000");
+struct __mee_driver_sifive_uart0 __mee_dt_serial_10013000;
+
+/* From clock@0 */
+struct __mee_driver_fixed_clock __mee_dt_clock_0 = {
+    .vtable = &__mee_driver_vtable_fixed_clock,
+    .clock.vtable = &__mee_driver_vtable_fixed_clock.clock,
+    .rate = 16000000UL,
+};
+
+/* From clock@2 */
+struct __mee_driver_fixed_clock __mee_dt_clock_2 = {
+    .vtable = &__mee_driver_vtable_fixed_clock,
+    .clock.vtable = &__mee_driver_vtable_fixed_clock.clock,
+    .rate = 72000000UL,
+};
+
+/* From clock@5 */
+struct __mee_driver_fixed_clock __mee_dt_clock_5 = {
+    .vtable = &__mee_driver_vtable_fixed_clock,
+    .clock.vtable = &__mee_driver_vtable_fixed_clock.clock,
+    .rate = 32000000UL,
+};
+
+/* From clock@4 */
+struct __mee_driver_sifive_fe310_g000_pll __mee_dt_clock_4 = {
+    .vtable = &__mee_driver_vtable_sifive_fe310_g000_pll,
+    .clock.vtable = &__mee_driver_vtable_sifive_fe310_g000_pll.clock,
+/* From clock@3 */
+    .pllsel0 = &__mee_dt_clock_3.clock,
+/* From clock@1 */
+    .pllref = &__mee_dt_clock_1.clock,
+/* From prci@10008000 */
+    .divider_base = &__mee_dt_prci_10008000,
+    .divider_offset = 12UL,
+/* From prci@10008000 */
+    .config_base = &__mee_dt_prci_10008000,
+    .config_offset = 8UL,
+    .init_rate = 16000000UL,
+};
+
+/* From clock@4 */
+#define __MEE_DT_SIFIVE_FE310_G000_PLL_HANDLE (&__mee_dt_clock_4)
+/* From prci@10008000 */
+struct __mee_driver_sifive_fe310_g000_prci __mee_dt_prci_10008000 = {
+    .vtable = &__mee_driver_vtable_sifive_fe310_g000_prci,
+    .base = 268468224UL,
+    .size = 32768UL,
+};
+
+/* From clock@1 */
+struct __mee_driver_sifive_fe310_g000_hfxosc __mee_dt_clock_1 = {
+    .vtable = &__mee_driver_vtable_sifive_fe310_g000_hfxosc,
+    .clock.vtable = &__mee_driver_vtable_sifive_fe310_g000_hfxosc.clock,
+/* From clock@0 */
+    .ref = &__mee_dt_clock_0.clock,
+/* From prci@10008000 */
+    .config_base = &__mee_dt_prci_10008000,
+    .config_offset = 4UL,
+};
+
+/* From clock@3 */
+struct __mee_driver_sifive_fe310_g000_hfrosc __mee_dt_clock_3 = {
+    .vtable = &__mee_driver_vtable_sifive_fe310_g000_hfrosc,
+    .clock.vtable = &__mee_driver_vtable_sifive_fe310_g000_hfrosc.clock,
+/* From clock@2 */
+    .ref = &__mee_dt_clock_2.clock,
+/* From prci@10008000 */
+    .config_base = &__mee_dt_prci_10008000,
+    .config_offset = 0UL,
+};
+
+/* From gpio@10012000 */
+struct __mee_driver_sifive_gpio0 __mee_dt_gpio_10012000 = {
+    .vtable = &__mee_driver_vtable_sifive_gpio0,
+    .base = 268509184UL,
+    .size = 4096UL,
+};
+
+/* From serial@10013000 */
+struct __mee_driver_sifive_uart0 __mee_dt_serial_10013000 = {
+    .vtable = &__mee_driver_vtable_sifive_uart0,
+    .uart.vtable = &__mee_driver_vtable_sifive_uart0.uart,
+    .control_base = 268513280UL,
+    .control_size = 4096UL,
+/* From clock@4 */
+    .clock = &__mee_dt_clock_4.clock,
+/* From gpio@10012000 */
+    .pinmux = &__mee_dt_gpio_10012000,
+    .pinmux_output_selector = 196608UL,
+    .pinmux_source_selector = 196608UL,
+};
+
+/* From serial@10013000 */
+#define __MEE_DT_STDOUT_UART_HANDLE (&__mee_dt_serial_10013000.uart)
+#define __MEE_DT_STDOUT_UART_BAUD 115200
+#endif/*ASSEMBLY*/
diff --git a/bsp/sifive-hifive1/mee.lds b/bsp/sifive-hifive1/mee.lds
new file mode 100644
index 0000000..cf24a7c
--- /dev/null
+++ b/bsp/sifive-hifive1/mee.lds
@@ -0,0 +1,190 @@
+OUTPUT_ARCH("riscv")
+
+ENTRY(_enter)
+
+MEMORY
+{
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x20000000
+}
+
+PHDRS
+{
+	flash PT_LOAD;
+	ram_init PT_LOAD;
+	ram PT_NULL;
+}
+
+SECTIONS
+{
+	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x800;
+
+
+	.init 		:
+	{
+		KEEP (*(.text.mee.init.enter))
+		KEEP (*(SORT_NONE(.init)))
+	} >flash AT>flash :flash
+
+
+	.text 		:
+	{
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.*)
+		*(.gnu.linkonce.t.*)
+	} >flash AT>flash :flash
+
+
+	.fini 		:
+	{
+		KEEP (*(SORT_NONE(.fini)))
+	} >flash AT>flash :flash
+
+
+	PROVIDE (__etext = .);
+	PROVIDE (_etext = .);
+	PROVIDE (etext = .);
+
+
+	.rodata 		:
+	{
+		*(.rdata)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.r.*)
+	} >flash AT>flash :flash
+
+
+	. = ALIGN(4);
+
+
+	.preinit_array 		:
+	{
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >flash AT>flash :flash
+
+
+	.init_array 		:
+	{
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+		PROVIDE_HIDDEN (__init_array_end = .);
+	} >flash AT>flash :flash
+
+
+	.finit_array 		:
+	{
+		PROVIDE_HIDDEN (__finit_array_start = .);
+		KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+		KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+		PROVIDE_HIDDEN (__finit_array_end = .);
+	} >flash AT>flash :flash
+
+
+	.ctors 		:
+	{
+		/* gcc uses crtbegin.o to find the start of
+		   the constructors, so we make sure it is
+		   first.  Because this is a wildcard, it
+		   doesn't matter if the user does not
+		   actually link against crtbegin.o; the
+		   linker won't look for a file to match a
+		   wildcard.  The wildcard also means that it
+		   doesn't matter which directory crtbegin.o
+		   is in.  */
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*crtbegin?.o(.ctors))
+		/* We don't want to include the .ctor section from
+		   the crtend.o file until after the sorted ctors.
+		   The .ctor section from the crtend file contains the
+		   end of ctors marker and it must be last */
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >flash AT>flash :flash
+
+
+	.dtors 		:
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*crtbegin?.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >flash AT>flash :flash
+
+
+	.lalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( _data_lma = . );
+		PROVIDE( mee_segment_data_source_start = . );
+	} >flash AT>flash :flash
+
+
+	.dalign 		:
+	{
+		. = ALIGN(4);
+		PROVIDE( mee_segment_data_target_start = . );
+	} >ram AT>flash :ram_init
+
+
+	.data 		:
+	{
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.*)
+		*(.gnu.linkonce.s.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
+	} >ram AT>flash :ram_init
+
+
+	. = ALIGN(4);
+	PROVIDE( _edata = . );
+	PROVIDE( edata = . );
+	PROVIDE( mee_segment_data_target_end = . );
+	PROVIDE( _fbss = . );
+	PROVIDE( __bss_start = . );
+	PROVIDE( mee_segment_bss_target_start = . );
+
+
+	.bss 		:
+	{
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(4);
+	} >ram AT>ram :ram
+
+
+	. = ALIGN(8);
+	PROVIDE( _end = . );
+	PROVIDE( end = . );
+	PROVIDE( mee_segment_bss_target_end = . );
+	PROVIDE( mee_segment_heap_target_start = . );
+
+
+	.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+	{
+		PROVIDE( mee_segment_heap_target_end = . );
+		PROVIDE( _heap_end = . );
+		. = __stack_size;
+		PROVIDE( _sp = . );
+		PROVIDE(mee_segment_stack_end = .);
+	} >ram AT>ram :ram
+
+
+}
+
diff --git a/bsp/sifive-hifive1/openocd.cfg b/bsp/sifive-hifive1/openocd.cfg
new file mode 100644
index 0000000..b531e9c
--- /dev/null
+++ b/bsp/sifive-hifive1/openocd.cfg
@@ -0,0 +1,34 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+#Reset Stretcher logic on FE310 is ~1 second long
+#This doesn't apply if you use
+# ftdi_set_signal, but still good to document
+#adapter_nsrst_delay 1500
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset -- This type of reset is not implemented yet
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+  #Wait for the reset stretcher
+  #It will work without this, but
+  #will incur lots of delays for later commands.
+  sleep 1500
+}	
+halt
+#flash protect 0 64 last off
diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk
new file mode 100644
index 0000000..b9424bc
--- /dev/null
+++ b/bsp/sifive-hifive1/settings.mk
@@ -0,0 +1,2 @@
+RISCV_ARCH = rv32imac
+RISCV_ABI  = ilp32