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authorBunnaroath Sou <bsou@sifive.com>2019-02-27 15:26:41 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-02-27 15:26:41 -0800
commit7570a33f98d1980b9bc9e799b0b202fde2cda1ce (patch)
tree5755c5c187cced4e33f6661b46a47c3b2bb44433 /bsp/sifive-hifive1
parent01767ffd966798887ea3719fd51adb8c606710e8 (diff)
parent2ee3eec227ca11e0355358aa553b4618fff50bd9 (diff)
Merge branch 'e-series' of github.com:sifive/freedom-e-sdk into e-series
Diffstat (limited to 'bsp/sifive-hifive1')
-rw-r--r--bsp/sifive-hifive1/README.md19
1 files changed, 10 insertions, 9 deletions
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md
index 1cc077e..faca2eb 100644
--- a/bsp/sifive-hifive1/README.md
+++ b/bsp/sifive-hifive1/README.md
@@ -1,12 +1,13 @@
HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications.
his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
- - 1 hart with RV32IMAC core
- - 4 hardware breakpoints
- - Physical Mempory Protectin with 8 regions
- - 16 local interrupts signal that can be connected to off core complex devices
- - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
- - GPIO memory with 16 interrupt lines
- - SPI memory with 1 intterupt line
- - Serial port with 1 interrupt line
- - 1 RGB LEDS
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 intterupt line
+- Serial port with 1 interrupt line
+- 1 RGB LEDS