diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-27 15:46:57 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-27 15:46:57 -0800 |
| commit | cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 (patch) | |
| tree | ee323a74e2355cfedd0d528a407a6d5d252e8a7c /bsp/sifive-hifive1 | |
| parent | 7570a33f98d1980b9bc9e799b0b202fde2cda1ce (diff) | |
Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/sifive-hifive1')
| -rw-r--r-- | bsp/sifive-hifive1/README.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index faca2eb..6311207 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -1,13 +1,13 @@ HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. -his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS |