diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
| commit | e18401806b38ca0f60394780191df4b72cb2f88a (patch) | |
| tree | 50c31a3efbe1f1acce3aeec706c0d8d1227c0964 /bsp/sifive-hifive1 | |
| parent | bbea559f684a5eee7df45429ed55d41330f44474 (diff) | |
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/sifive-hifive1')
| -rw-r--r-- | bsp/sifive-hifive1/README.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md new file mode 100644 index 0000000..1cc077e --- /dev/null +++ b/bsp/sifive-hifive1/README.md @@ -0,0 +1,12 @@ +HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. + +his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + - GPIO memory with 16 interrupt lines + - SPI memory with 1 intterupt line + - Serial port with 1 interrupt line + - 1 RGB LEDS |