diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-23 14:16:04 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-28 10:06:45 -0700 |
| commit | 12485f45ebb7f96dc60951bf4365533652ac5139 (patch) | |
| tree | b38ce688ab045a41bbdcdc90462fb4e4646a0b5d /bsp | |
| parent | f7960558fd35113a89025f0971f3779d884f9a53 (diff) | |
Update BSPs
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp')
168 files changed, 490 insertions, 370 deletions
diff --git a/bsp/coreip-e20-arty/metal-inline.h b/bsp/coreip-e20-arty/metal-inline.h index 3b9c4e5..80d673c 100644 --- a/bsp/coreip-e20-arty/metal-inline.h +++ b/bsp/coreip-e20-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-52 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e20-arty/metal-platform.h b/bsp/coreip-e20-arty/metal-platform.h index d049910..269e419 100644 --- a/bsp/coreip-e20-arty/metal-platform.h +++ b/bsp/coreip-e20-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-52 */ /* ----------------------------------- */ #ifndef COREIP_E20_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-arty/metal.default.lds b/bsp/coreip-e20-arty/metal.default.lds index badb729..73f7f46 100644 --- a/bsp/coreip-e20-arty/metal.default.lds +++ b/bsp/coreip-e20-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-52 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h index 34014a1..6a73cba 100644 --- a/bsp/coreip-e20-arty/metal.h +++ b/bsp/coreip-e20-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-52 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,18 +69,18 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds index 5742665..a86761f 100644 --- a/bsp/coreip-e20-arty/metal.ramrodata.lds +++ b/bsp/coreip-e20-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-52 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-arty/metal.scratchpad.lds b/bsp/coreip-e20-arty/metal.scratchpad.lds index 3702a05..f672544 100644 --- a/bsp/coreip-e20-arty/metal.scratchpad.lds +++ b/bsp/coreip-e20-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-52 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index 9a4c6d6..7507947 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-52 # # ----------------------------------- # RISCV_ARCH=rv32imc RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-e20-rtl/metal-inline.h b/bsp/coreip-e20-rtl/metal-inline.h index a896131..8f6f5d3 100644 --- a/bsp/coreip-e20-rtl/metal-inline.h +++ b/bsp/coreip-e20-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h index 4aa40ea..fd91dd9 100644 --- a/bsp/coreip-e20-rtl/metal-platform.h +++ b/bsp/coreip-e20-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ #ifndef COREIP_E20_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-rtl/metal.default.lds b/bsp/coreip-e20-rtl/metal.default.lds index 7937b08..3015cee 100644 --- a/bsp/coreip-e20-rtl/metal.default.lds +++ b/bsp/coreip-e20-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h index 6749faa..c7b2850 100644 --- a/bsp/coreip-e20-rtl/metal.h +++ b/bsp/coreip-e20-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -63,11 +63,11 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_testram_20000000; diff --git a/bsp/coreip-e20-rtl/metal.ramrodata.lds b/bsp/coreip-e20-rtl/metal.ramrodata.lds index 2343ee7..c9054d5 100644 --- a/bsp/coreip-e20-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e20-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-rtl/metal.scratchpad.lds b/bsp/coreip-e20-rtl/metal.scratchpad.lds index 7937b08..3015cee 100644 --- a/bsp/coreip-e20-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e20-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index a935127..1d26ee1 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-53 # # ----------------------------------- # RISCV_ARCH=rv32imc RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-e21-arty/metal-inline.h b/bsp/coreip-e21-arty/metal-inline.h index 21116c7..a604c8e 100644 --- a/bsp/coreip-e21-arty/metal-inline.h +++ b/bsp/coreip-e21-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-54 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h index 3e275a2..772e33b 100644 --- a/bsp/coreip-e21-arty/metal-platform.h +++ b/bsp/coreip-e21-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-54 */ /* ----------------------------------- */ #ifndef COREIP_E21_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds index 5bea1f5..9bff795 100644 --- a/bsp/coreip-e21-arty/metal.default.lds +++ b/bsp/coreip-e21-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-54 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h index f5e9533..be2aab5 100644 --- a/bsp/coreip-e21-arty/metal.h +++ b/bsp/coreip-e21-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-54 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,18 +69,18 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds index 1e37ef6..bd05c35 100644 --- a/bsp/coreip-e21-arty/metal.ramrodata.lds +++ b/bsp/coreip-e21-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-54 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds index 21e626f..d9cae70 100644 --- a/bsp/coreip-e21-arty/metal.scratchpad.lds +++ b/bsp/coreip-e21-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-54 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index ab96737..63a291a 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-54 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-e21-rtl/metal-inline.h b/bsp/coreip-e21-rtl/metal-inline.h index fc8a319..a7a7546 100644 --- a/bsp/coreip-e21-rtl/metal-inline.h +++ b/bsp/coreip-e21-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-55 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e21-rtl/metal-platform.h b/bsp/coreip-e21-rtl/metal-platform.h index 51a7b22..dd03141 100644 --- a/bsp/coreip-e21-rtl/metal-platform.h +++ b/bsp/coreip-e21-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-55 */ /* ----------------------------------- */ #ifndef COREIP_E21_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e21-rtl/metal.default.lds b/bsp/coreip-e21-rtl/metal.default.lds index 0f4bf1e..4807dbc 100644 --- a/bsp/coreip-e21-rtl/metal.default.lds +++ b/bsp/coreip-e21-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-55 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h index eb1da58..78e3a7c 100644 --- a/bsp/coreip-e21-rtl/metal.h +++ b/bsp/coreip-e21-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-55 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -63,11 +63,11 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_sys_sram_0_80000000; diff --git a/bsp/coreip-e21-rtl/metal.ramrodata.lds b/bsp/coreip-e21-rtl/metal.ramrodata.lds index b3b1581..556706d 100644 --- a/bsp/coreip-e21-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e21-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-55 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e21-rtl/metal.scratchpad.lds b/bsp/coreip-e21-rtl/metal.scratchpad.lds index 4b1b222..60a5bba 100644 --- a/bsp/coreip-e21-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e21-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-55 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index afc60e3..5ed3263 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-55 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-e24-arty/metal-inline.h b/bsp/coreip-e24-arty/metal-inline.h index ddb5acd..f145c70 100644 --- a/bsp/coreip-e24-arty/metal-inline.h +++ b/bsp/coreip-e24-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e24-arty/metal-platform.h b/bsp/coreip-e24-arty/metal-platform.h index 160303c..b63f488 100644 --- a/bsp/coreip-e24-arty/metal-platform.h +++ b/bsp/coreip-e24-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ #ifndef COREIP_E24_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e24-arty/metal.default.lds b/bsp/coreip-e24-arty/metal.default.lds index 5bea1f5..78de917 100644 --- a/bsp/coreip-e24-arty/metal.default.lds +++ b/bsp/coreip-e24-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h index cb76f8f..39e45a9 100644 --- a/bsp/coreip-e24-arty/metal.h +++ b/bsp/coreip-e24-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,18 +69,18 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-e24-arty/metal.ramrodata.lds b/bsp/coreip-e24-arty/metal.ramrodata.lds index 1e37ef6..d21a507 100644 --- a/bsp/coreip-e24-arty/metal.ramrodata.lds +++ b/bsp/coreip-e24-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e24-arty/metal.scratchpad.lds b/bsp/coreip-e24-arty/metal.scratchpad.lds index 21e626f..bff9364 100644 --- a/bsp/coreip-e24-arty/metal.scratchpad.lds +++ b/bsp/coreip-e24-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 1e501a6..52e2390 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-56 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-e24-rtl/metal-inline.h b/bsp/coreip-e24-rtl/metal-inline.h index acc2c7e..c31feff 100644 --- a/bsp/coreip-e24-rtl/metal-inline.h +++ b/bsp/coreip-e24-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e24-rtl/metal-platform.h b/bsp/coreip-e24-rtl/metal-platform.h index db73ab4..75cc392 100644 --- a/bsp/coreip-e24-rtl/metal-platform.h +++ b/bsp/coreip-e24-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ #ifndef COREIP_E24_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e24-rtl/metal.default.lds b/bsp/coreip-e24-rtl/metal.default.lds index 0f4bf1e..de1e1e3 100644 --- a/bsp/coreip-e24-rtl/metal.default.lds +++ b/bsp/coreip-e24-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h index 222afa0..c30cb3b 100644 --- a/bsp/coreip-e24-rtl/metal.h +++ b/bsp/coreip-e24-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -63,11 +63,11 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_sys_sram_0_80000000; diff --git a/bsp/coreip-e24-rtl/metal.ramrodata.lds b/bsp/coreip-e24-rtl/metal.ramrodata.lds index b3b1581..8990b56 100644 --- a/bsp/coreip-e24-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e24-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e24-rtl/metal.scratchpad.lds b/bsp/coreip-e24-rtl/metal.scratchpad.lds index 4b1b222..e361b3e 100644 --- a/bsp/coreip-e24-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e24-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-56 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index dc10ea1..8e80c11 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-56 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-e31-arty/metal-inline.h b/bsp/coreip-e31-arty/metal-inline.h index 463ecca..ace6025 100644 --- a/bsp/coreip-e31-arty/metal-inline.h +++ b/bsp/coreip-e31-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e31-arty/metal-platform.h b/bsp/coreip-e31-arty/metal-platform.h index 3993a61..058df6f 100644 --- a/bsp/coreip-e31-arty/metal-platform.h +++ b/bsp/coreip-e31-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ #ifndef COREIP_E31_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e31-arty/metal.default.lds b/bsp/coreip-e31-arty/metal.default.lds index 4a9e1be..08ed7c1 100644 --- a/bsp/coreip-e31-arty/metal.default.lds +++ b/bsp/coreip-e31-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h index 43e71a3..7cbb276 100644 --- a/bsp/coreip-e31-arty/metal.h +++ b/bsp/coreip-e31-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,19 +75,19 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-e31-arty/metal.ramrodata.lds b/bsp/coreip-e31-arty/metal.ramrodata.lds index a280082..3edfa5b 100644 --- a/bsp/coreip-e31-arty/metal.ramrodata.lds +++ b/bsp/coreip-e31-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e31-arty/metal.scratchpad.lds b/bsp/coreip-e31-arty/metal.scratchpad.lds index 16211dc..ffaba0f 100644 --- a/bsp/coreip-e31-arty/metal.scratchpad.lds +++ b/bsp/coreip-e31-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index ab96737..b4d4cf6 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-57 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-e31-rtl/metal-inline.h b/bsp/coreip-e31-rtl/metal-inline.h index a5035c7..bce8f44 100644 --- a/bsp/coreip-e31-rtl/metal-inline.h +++ b/bsp/coreip-e31-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e31-rtl/metal-platform.h b/bsp/coreip-e31-rtl/metal-platform.h index 9e03fae..f47c1ab 100644 --- a/bsp/coreip-e31-rtl/metal-platform.h +++ b/bsp/coreip-e31-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ #ifndef COREIP_E31_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e31-rtl/metal.default.lds b/bsp/coreip-e31-rtl/metal.default.lds index f687862..3771ba4 100644 --- a/bsp/coreip-e31-rtl/metal.default.lds +++ b/bsp/coreip-e31-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h index 9e977af..0f72ce7 100644 --- a/bsp/coreip-e31-rtl/metal.h +++ b/bsp/coreip-e31-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -71,13 +71,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_testram_20000000; diff --git a/bsp/coreip-e31-rtl/metal.ramrodata.lds b/bsp/coreip-e31-rtl/metal.ramrodata.lds index e75a025..d6811a2 100644 --- a/bsp/coreip-e31-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e31-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e31-rtl/metal.scratchpad.lds b/bsp/coreip-e31-rtl/metal.scratchpad.lds index d05f5c2..8cfb05e 100644 --- a/bsp/coreip-e31-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e31-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-57 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index afc60e3..24dc2e9 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-57 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-e34-arty/metal-inline.h b/bsp/coreip-e34-arty/metal-inline.h index c322ecb..651a9d5 100644 --- a/bsp/coreip-e34-arty/metal-inline.h +++ b/bsp/coreip-e34-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e34-arty/metal-platform.h b/bsp/coreip-e34-arty/metal-platform.h index e3781a9..72b0606 100644 --- a/bsp/coreip-e34-arty/metal-platform.h +++ b/bsp/coreip-e34-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ #ifndef COREIP_E34_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e34-arty/metal.default.lds b/bsp/coreip-e34-arty/metal.default.lds index 4a9e1be..54c5873 100644 --- a/bsp/coreip-e34-arty/metal.default.lds +++ b/bsp/coreip-e34-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h index 384bd19..4ada6cf 100644 --- a/bsp/coreip-e34-arty/metal.h +++ b/bsp/coreip-e34-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,19 +75,19 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-e34-arty/metal.ramrodata.lds b/bsp/coreip-e34-arty/metal.ramrodata.lds index a280082..d6fa98e 100644 --- a/bsp/coreip-e34-arty/metal.ramrodata.lds +++ b/bsp/coreip-e34-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e34-arty/metal.scratchpad.lds b/bsp/coreip-e34-arty/metal.scratchpad.lds index 16211dc..e1909e6 100644 --- a/bsp/coreip-e34-arty/metal.scratchpad.lds +++ b/bsp/coreip-e34-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk index 1e501a6..c4fc996 100644 --- a/bsp/coreip-e34-arty/settings.mk +++ b/bsp/coreip-e34-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-00 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-e34-rtl/metal-inline.h b/bsp/coreip-e34-rtl/metal-inline.h index 8a7c179..23bcf3e 100644 --- a/bsp/coreip-e34-rtl/metal-inline.h +++ b/bsp/coreip-e34-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e34-rtl/metal-platform.h b/bsp/coreip-e34-rtl/metal-platform.h index 4b128f9..bd44e86 100644 --- a/bsp/coreip-e34-rtl/metal-platform.h +++ b/bsp/coreip-e34-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ #ifndef COREIP_E34_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e34-rtl/metal.default.lds b/bsp/coreip-e34-rtl/metal.default.lds index f687862..ac8d923 100644 --- a/bsp/coreip-e34-rtl/metal.default.lds +++ b/bsp/coreip-e34-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h index a77fc08..aba0ed4 100644 --- a/bsp/coreip-e34-rtl/metal.h +++ b/bsp/coreip-e34-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -71,13 +71,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_testram_20000000; diff --git a/bsp/coreip-e34-rtl/metal.ramrodata.lds b/bsp/coreip-e34-rtl/metal.ramrodata.lds index e75a025..23463e9 100644 --- a/bsp/coreip-e34-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e34-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e34-rtl/metal.scratchpad.lds b/bsp/coreip-e34-rtl/metal.scratchpad.lds index d05f5c2..0823b2c 100644 --- a/bsp/coreip-e34-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e34-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-00 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index dc10ea1..95513b9 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-00 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h index d1af334..d1ec2ff 100644 --- a/bsp/coreip-e76-arty/metal-inline.h +++ b/bsp/coreip-e76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h index a08971f..237a951 100644 --- a/bsp/coreip-e76-arty/metal-platform.h +++ b/bsp/coreip-e76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index fc983a7..573538c 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index 0c4f0eb..51cf900 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,18 +75,18 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From tlclk */ struct __metal_driver_fixed_clock __metal_dt_tlclk; diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index f53fd33..e44853a 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index eadc43f..f467347 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 1e501a6..87b6174 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-01 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-7-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-e76-rtl/metal-inline.h b/bsp/coreip-e76-rtl/metal-inline.h index aef66bd..179e00c 100644 --- a/bsp/coreip-e76-rtl/metal-inline.h +++ b/bsp/coreip-e76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h index 5513ead..04908bb 100644 --- a/bsp/coreip-e76-rtl/metal-platform.h +++ b/bsp/coreip-e76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ #ifndef COREIP_E76_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds index f1317d6..1289952 100644 --- a/bsp/coreip-e76-rtl/metal.default.lds +++ b/bsp/coreip-e76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h index 903e53d..48f7474 100644 --- a/bsp/coreip-e76-rtl/metal.h +++ b/bsp/coreip-e76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,12 +69,12 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_memory_80000000; diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds index 11169de..d2f4843 100644 --- a/bsp/coreip-e76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds index f1317d6..1289952 100644 --- a/bsp/coreip-e76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index 8f9bb0b..c48d58a 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-7-series COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-s51-arty/metal-inline.h b/bsp/coreip-s51-arty/metal-inline.h index 3d1cc63..6af2da7 100644 --- a/bsp/coreip-s51-arty/metal-inline.h +++ b/bsp/coreip-s51-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-04 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s51-arty/metal-platform.h b/bsp/coreip-s51-arty/metal-platform.h index 7edd9aa..b12e171 100644 --- a/bsp/coreip-s51-arty/metal-platform.h +++ b/bsp/coreip-s51-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-04 */ /* ----------------------------------- */ #ifndef COREIP_S51_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-s51-arty/metal.default.lds b/bsp/coreip-s51-arty/metal.default.lds index 4a9e1be..52b736e 100644 --- a/bsp/coreip-s51-arty/metal.default.lds +++ b/bsp/coreip-s51-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-04 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h index f5087cc..bb6c1b0 100644 --- a/bsp/coreip-s51-arty/metal.h +++ b/bsp/coreip-s51-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-04 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,19 +75,19 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-s51-arty/metal.ramrodata.lds b/bsp/coreip-s51-arty/metal.ramrodata.lds index a280082..4652f16 100644 --- a/bsp/coreip-s51-arty/metal.ramrodata.lds +++ b/bsp/coreip-s51-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-04 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s51-arty/metal.scratchpad.lds b/bsp/coreip-s51-arty/metal.scratchpad.lds index 16211dc..e74a0c1 100644 --- a/bsp/coreip-s51-arty/metal.scratchpad.lds +++ b/bsp/coreip-s51-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-04 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 4c84306..746be02 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-04 # # ----------------------------------- # RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-s51-rtl/metal-inline.h b/bsp/coreip-s51-rtl/metal-inline.h index 43b1d7b..de53041 100644 --- a/bsp/coreip-s51-rtl/metal-inline.h +++ b/bsp/coreip-s51-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-05 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s51-rtl/metal-platform.h b/bsp/coreip-s51-rtl/metal-platform.h index 9d7ee51..3b810aa 100644 --- a/bsp/coreip-s51-rtl/metal-platform.h +++ b/bsp/coreip-s51-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-05 */ /* ----------------------------------- */ #ifndef COREIP_S51_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-s51-rtl/metal.default.lds b/bsp/coreip-s51-rtl/metal.default.lds index e5be410..e2a4eae 100644 --- a/bsp/coreip-s51-rtl/metal.default.lds +++ b/bsp/coreip-s51-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-05 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h index 3a90f6c..05dc4ff 100644 --- a/bsp/coreip-s51-rtl/metal.h +++ b/bsp/coreip-s51-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-05 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -71,13 +71,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_testram_20000000; diff --git a/bsp/coreip-s51-rtl/metal.ramrodata.lds b/bsp/coreip-s51-rtl/metal.ramrodata.lds index e9f838a..e39e123 100644 --- a/bsp/coreip-s51-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s51-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-05 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s51-rtl/metal.scratchpad.lds b/bsp/coreip-s51-rtl/metal.scratchpad.lds index e46abb7..c6cde71 100644 --- a/bsp/coreip-s51-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s51-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-05 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index 12a8c2e..b166dd3 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-05 # # ----------------------------------- # RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-s54-arty/metal-inline.h b/bsp/coreip-s54-arty/metal-inline.h index b321a86..dedae73 100644 --- a/bsp/coreip-s54-arty/metal-inline.h +++ b/bsp/coreip-s54-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s54-arty/metal-platform.h b/bsp/coreip-s54-arty/metal-platform.h index d044a65..b04b3e1 100644 --- a/bsp/coreip-s54-arty/metal-platform.h +++ b/bsp/coreip-s54-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ #ifndef COREIP_S54_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-s54-arty/metal.default.lds b/bsp/coreip-s54-arty/metal.default.lds index 4a9e1be..fc6e2f5 100644 --- a/bsp/coreip-s54-arty/metal.default.lds +++ b/bsp/coreip-s54-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h index 6973c1b..788a3d8 100644 --- a/bsp/coreip-s54-arty/metal.h +++ b/bsp/coreip-s54-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,19 +75,19 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/coreip-s54-arty/metal.ramrodata.lds b/bsp/coreip-s54-arty/metal.ramrodata.lds index a280082..95b4c0d 100644 --- a/bsp/coreip-s54-arty/metal.ramrodata.lds +++ b/bsp/coreip-s54-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s54-arty/metal.scratchpad.lds b/bsp/coreip-s54-arty/metal.scratchpad.lds index 16211dc..1f27c02 100644 --- a/bsp/coreip-s54-arty/metal.scratchpad.lds +++ b/bsp/coreip-s54-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index ded9d2f..3e3e431 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-08 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-s54-rtl/metal-inline.h b/bsp/coreip-s54-rtl/metal-inline.h index a04cbc1..7b30a9b 100644 --- a/bsp/coreip-s54-rtl/metal-inline.h +++ b/bsp/coreip-s54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s54-rtl/metal-platform.h b/bsp/coreip-s54-rtl/metal-platform.h index 2175c30..f08baf2 100644 --- a/bsp/coreip-s54-rtl/metal-platform.h +++ b/bsp/coreip-s54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ #ifndef COREIP_S54_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-s54-rtl/metal.default.lds b/bsp/coreip-s54-rtl/metal.default.lds index e5be410..a288ae5 100644 --- a/bsp/coreip-s54-rtl/metal.default.lds +++ b/bsp/coreip-s54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s54-rtl/metal.h b/bsp/coreip-s54-rtl/metal.h index 3880110..a1aba5d 100644 --- a/bsp/coreip-s54-rtl/metal.h +++ b/bsp/coreip-s54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -71,13 +71,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_testram_20000000; diff --git a/bsp/coreip-s54-rtl/metal.ramrodata.lds b/bsp/coreip-s54-rtl/metal.ramrodata.lds index e9f838a..28a996b 100644 --- a/bsp/coreip-s54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s54-rtl/metal.scratchpad.lds b/bsp/coreip-s54-rtl/metal.scratchpad.lds index e46abb7..f89dac2 100644 --- a/bsp/coreip-s54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-08 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index a25dc18..4aa0944 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-08 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-s76-arty/metal-inline.h b/bsp/coreip-s76-arty/metal-inline.h index 56168da..204a35b 100644 --- a/bsp/coreip-s76-arty/metal-inline.h +++ b/bsp/coreip-s76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h index c849584..c52e5ac 100644 --- a/bsp/coreip-s76-arty/metal-platform.h +++ b/bsp/coreip-s76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef COREIP_S76_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds index fc983a7..d22d88e 100644 --- a/bsp/coreip-s76-arty/metal.default.lds +++ b/bsp/coreip-s76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h index 87f6ae5..0a6efa6 100644 --- a/bsp/coreip-s76-arty/metal.h +++ b/bsp/coreip-s76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,18 +75,18 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From tlclk */ struct __metal_driver_fixed_clock __metal_dt_tlclk; diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds index f53fd33..8b20b53 100644 --- a/bsp/coreip-s76-arty/metal.ramrodata.lds +++ b/bsp/coreip-s76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds index eadc43f..05c0700 100644 --- a/bsp/coreip-s76-arty/metal.scratchpad.lds +++ b/bsp/coreip-s76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index ded9d2f..6928c1e 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-10 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-7-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/coreip-s76-rtl/metal-inline.h b/bsp/coreip-s76-rtl/metal-inline.h index 57d7a4d..207deee 100644 --- a/bsp/coreip-s76-rtl/metal-inline.h +++ b/bsp/coreip-s76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s76-rtl/metal-platform.h b/bsp/coreip-s76-rtl/metal-platform.h index ca0320d..ca65c36 100644 --- a/bsp/coreip-s76-rtl/metal-platform.h +++ b/bsp/coreip-s76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef COREIP_S76_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-s76-rtl/metal.default.lds b/bsp/coreip-s76-rtl/metal.default.lds index f1317d6..85640c7 100644 --- a/bsp/coreip-s76-rtl/metal.default.lds +++ b/bsp/coreip-s76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h index 7b092fc..0da0815 100644 --- a/bsp/coreip-s76-rtl/metal.h +++ b/bsp/coreip-s76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,12 +69,12 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_memory_80000000; diff --git a/bsp/coreip-s76-rtl/metal.ramrodata.lds b/bsp/coreip-s76-rtl/metal.ramrodata.lds index 11169de..f989496 100644 --- a/bsp/coreip-s76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-rtl/metal.scratchpad.lds b/bsp/coreip-s76-rtl/metal.scratchpad.lds index f1317d6..85640c7 100644 --- a/bsp/coreip-s76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index a25dc18..46377af 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-10 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-7-series COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h index 3d08799..ef0bfb8 100644 --- a/bsp/coreip-u54-rtl/metal-inline.h +++ b/bsp/coreip-u54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h index fb3d3b4..90a8585 100644 --- a/bsp/coreip-u54-rtl/metal-platform.h +++ b/bsp/coreip-u54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ #ifndef COREIP_U54_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds index 93fc5a8..76c79e3 100644 --- a/bsp/coreip-u54-rtl/metal.default.lds +++ b/bsp/coreip-u54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h index 7e793bc..59cf0f9 100644 --- a/bsp/coreip-u54-rtl/metal.h +++ b/bsp/coreip-u54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,13 +69,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,fu540-c000,l2.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_fu540-c000_l2.h> struct metal_memory __metal_dt_mem_itim_1800000; diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds index 57b767a..d65ac02 100644 --- a/bsp/coreip-u54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds index 93fc5a8..76c79e3 100644 --- a/bsp/coreip-u54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk index 4cf87cb..2f1a8b2 100644 --- a/bsp/coreip-u54-rtl/settings.mk +++ b/bsp/coreip-u54-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-50 # +# [XXXXX] 28-05-2019 10-06-15 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series COREIP_MEM_WIDTH=128 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h index 34e4d33..ca4fc82 100644 --- a/bsp/coreip-u54mc-rtl/metal-inline.h +++ b/bsp/coreip-u54mc-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-13 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h index 7045d23..332c8bb 100644 --- a/bsp/coreip-u54mc-rtl/metal-platform.h +++ b/bsp/coreip-u54mc-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-13 */ /* ----------------------------------- */ #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds index a95cc07..1476969 100644 --- a/bsp/coreip-u54mc-rtl/metal.default.lds +++ b/bsp/coreip-u54mc-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-13 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 1); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h index 417332f..f1fa821 100644 --- a/bsp/coreip-u54mc-rtl/metal.h +++ b/bsp/coreip-u54mc-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-13 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,13 +69,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,fu540-c000,l2.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_fu540-c000_l2.h> struct metal_memory __metal_dt_mem_dtim_1000000; diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds index b5f35f7..532321d 100644 --- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-13 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 1); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds index a95cc07..1476969 100644 --- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-13 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 1); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk index ae9e038..c751abc 100644 --- a/bsp/coreip-u54mc-rtl/settings.mk +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-13 # # ----------------------------------- # -RISCV_ARCH=rv64imac -RISCV_ABI=lp64 +RISCV_ARCH=rv64imafdc +RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series COREIP_MEM_WIDTH=128 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 diff --git a/bsp/freedom-e310-arty/metal-inline.h b/bsp/freedom-e310-arty/metal-inline.h index fafb3ec..7d8fa14 100644 --- a/bsp/freedom-e310-arty/metal-inline.h +++ b/bsp/freedom-e310-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-21 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/freedom-e310-arty/metal-platform.h b/bsp/freedom-e310-arty/metal-platform.h index 35d7e0a..5b0bfdc 100644 --- a/bsp/freedom-e310-arty/metal-platform.h +++ b/bsp/freedom-e310-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ #ifndef FREEDOM_E310_ARTY__METAL_PLATFORM_H diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index f9dcdbd..2e769fc 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-21 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h index c1c3dca..74865cb 100644 --- a/bsp/freedom-e310-arty/metal.h +++ b/bsp/freedom-e310-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-21 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -73,14 +73,14 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_uart0.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index d5d7b5b..74a982f 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-21 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index dfdf485..7bf4a03 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-21 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index d3d0bfc..cd417c4 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-50 # +# [XXXXX] 28-05-2019 10-06-21 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h index dcc51cb..a66241b 100644 --- a/bsp/sifive-hifive-unleashed/metal-inline.h +++ b/bsp/sifive-hifive-unleashed/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h index 4bfe75b..699cf77 100644 --- a/bsp/sifive-hifive-unleashed/metal-platform.h +++ b/bsp/sifive-hifive-unleashed/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds index 23351d2..55b8c3a 100644 --- a/bsp/sifive-hifive-unleashed/metal.default.lds +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h index 4154037..196d5a0 100644 --- a/bsp/sifive-hifive-unleashed/metal.h +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -74,15 +74,15 @@ #include <metal/drivers/fixed-clock.h> #include <metal/drivers/fixed-factor-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> -#include <metal/drivers/sifive,fu540-c000,l2.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> +#include <metal/drivers/sifive_fu540-c000_l2.h> /* From refclk */ struct __metal_driver_fixed_clock __metal_dt_refclk; diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds index 4b31408..1592c34 100644 --- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds index 48d397f..80b5ca1 100644 --- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-22 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -30,6 +30,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive-unleashed/settings.mk b/bsp/sifive-hifive-unleashed/settings.mk index 2745538..de5ceef 100644 --- a/bsp/sifive-hifive-unleashed/settings.mk +++ b/bsp/sifive-hifive-unleashed/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-50 # +# [XXXXX] 28-05-2019 10-06-22 # # ----------------------------------- # RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series TARGET_TAGS=board openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/sifive-hifive1-revb/metal-inline.h b/bsp/sifive-hifive1-revb/metal-inline.h index 5f341a0..39ff7a4 100644 --- a/bsp/sifive-hifive1-revb/metal-inline.h +++ b/bsp/sifive-hifive1-revb/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-20 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/sifive-hifive1-revb/metal-platform.h b/bsp/sifive-hifive1-revb/metal-platform.h index 3e0f3b9..37ab73c 100644 --- a/bsp/sifive-hifive1-revb/metal-platform.h +++ b/bsp/sifive-hifive1-revb/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-20 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index dcbff03..379e9a7 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-20 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h index 7a111a2..132ef37 100644 --- a/bsp/sifive-hifive1-revb/metal.h +++ b/bsp/sifive-hifive1-revb/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-20 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -73,19 +73,19 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,uart0.h> -#include <metal/drivers/sifive,fe310-g000,hfrosc.h> -#include <metal/drivers/sifive,fe310-g000,hfxosc.h> -#include <metal/drivers/sifive,fe310-g000,pll.h> -#include <metal/drivers/sifive,fe310-g000,prci.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_uart0.h> +#include <metal/drivers/sifive_fe310-g000_hfrosc.h> +#include <metal/drivers/sifive_fe310-g000_hfxosc.h> +#include <metal/drivers/sifive_fe310-g000_pll.h> +#include <metal/drivers/sifive_fe310-g000_prci.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index 014fe70..1044d9e 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-20 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index 13a357e..10e1c64 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-20 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index d793c1d..ef40e42 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-50 # +# [XXXXX] 28-05-2019 10-06-20 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series TARGET_TAGS=board jlink TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 diff --git a/bsp/sifive-hifive1/metal-inline.h b/bsp/sifive-hifive1/metal-inline.h index 10470c7..cf122a8 100644 --- a/bsp/sifive-hifive1/metal-inline.h +++ b/bsp/sifive-hifive1/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-17 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/sifive-hifive1/metal-platform.h b/bsp/sifive-hifive1/metal-platform.h index 0bda7f1..eaa722e 100644 --- a/bsp/sifive-hifive1/metal-platform.h +++ b/bsp/sifive-hifive1/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-17 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index 3b27dd0..e43ada6 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-17 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h index 29f6127..b17884d 100644 --- a/bsp/sifive-hifive1/metal.h +++ b/bsp/sifive-hifive1/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-17 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -73,19 +73,19 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,uart0.h> -#include <metal/drivers/sifive,fe310-g000,hfrosc.h> -#include <metal/drivers/sifive,fe310-g000,hfxosc.h> -#include <metal/drivers/sifive,fe310-g000,pll.h> -#include <metal/drivers/sifive,fe310-g000,prci.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_uart0.h> +#include <metal/drivers/sifive_fe310-g000_hfrosc.h> +#include <metal/drivers/sifive_fe310-g000_hfxosc.h> +#include <metal/drivers/sifive_fe310-g000_pll.h> +#include <metal/drivers/sifive_fe310-g000_prci.h> /* From clock@0 */ struct __metal_driver_fixed_clock __metal_dt_clock_0; diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 2f49231..7a0c40d 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-17 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index cb27d7e..592e68c 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-17 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index 6b305de..eedf871 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-50 # +# [XXXXX] 28-05-2019 10-06-17 # # ----------------------------------- # RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-3-series TARGET_TAGS=board openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 |