diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-09 10:53:46 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-12 13:47:41 -0700 |
| commit | 16f09468427d7d338e75d69522e1a8c806c61eea (patch) | |
| tree | 9deffd064899f3ca46b9b38764ba9d7d35bc9673 /bsp | |
| parent | 2aa264a54b3aa1e3257805b55401718786939e47 (diff) | |
Fixup U54(MC) DTS
Add PMP nodes and the global-external-interrupts compat string
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/coreip-u54-rtl/design.dts | 5 | ||||
| -rw-r--r-- | bsp/coreip-u54mc-rtl/design.dts | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/bsp/coreip-u54-rtl/design.dts b/bsp/coreip-u54-rtl/design.dts index 4a7aedd..b773072 100644 --- a/bsp/coreip-u54-rtl/design.dts +++ b/bsp/coreip-u54-rtl/design.dts @@ -46,6 +46,10 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L13: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; @@ -97,6 +101,7 @@ reg = <0x0 0x3000 0x0 0x1000>; }; L10: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; interrupt-parent = <&L2>; interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>; }; diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index 504c0c4..27a3c94 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -150,6 +150,10 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L30: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; @@ -234,6 +238,7 @@ reg = <0x0 0x3000 0x0 0x1000>; }; L27: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; interrupt-parent = <&L2>; interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>; }; |