Add corrected formatting for bullet lists

Markdown bullet lists should: (1) have a blank line before and after
the list; (2) start each list item at the beginning of the line (no leading white-space)

The markdown processor in Freedom Studio enforces these standards and does
not render correctly otherwise.

7 files changed, 52 insertions, 47 deletions

diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md
index 5e19221..4c9fe1a 100644
--- a/bsp/coreip-e20/README.md
+++ b/bsp/coreip-e20/README.md
@@ -1,6 +1,7 @@
 The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.
 
 This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV32IMC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 4 regions
+
+- 1 hart with RV32IMC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 4 regions
diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md
index 31719b3..a2f1a61 100644
--- a/bsp/coreip-e21/README.md
+++ b/bsp/coreip-e21/README.md
@@ -1,6 +1,7 @@
 The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements.
 
 This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV32IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 4 regions
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 4 regions
diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md
index 1ae8739..eeb3502 100644
--- a/bsp/coreip-e31-arty/README.md
+++ b/bsp/coreip-e31-arty/README.md
@@ -1,14 +1,14 @@
 The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.
 
 This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV32IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 8 regions
-        - 16 local interrupts signal that can be connected to off core complex devices
-        - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
-        - GPIO memory with 16 interrupt lines
-        - SPI memory with 1 intterupt line
-        - Serial port with 1 interrupt line
-        - 4 RGB LEDS
-        - 4 Buttons and 4 Switches
-~                                            
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 intterupt line
+- Serial port with 1 interrupt line
+- 4 RGB LEDS
+- 4 Buttons and 4 Switches
diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md
index 02f7723..ebfe371 100644
--- a/bsp/coreip-e31/README.md
+++ b/bsp/coreip-e31/README.md
@@ -1,9 +1,9 @@
 The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.
 
 This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV32IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 8 regions
-        - 16 local interrupts signal that can be connected to off core complex devices
-        - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
-~                                            
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md
index 6d6c04f..be9d317 100644
--- a/bsp/coreip-s51-arty/README.md
+++ b/bsp/coreip-s51-arty/README.md
@@ -1,13 +1,14 @@
 The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications
 
 This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV64IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 8 regions
-        - 16 local interrupts signal that can be connected to off core complex devices
-        - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
-	- GPIO memory with 16 interrupt lines
-	- SPI memory with 1 intterupt line
-	- Serial port with 1 interrupt line
-	- 4 RGB LEDS
-	- 4 Buttons and 4 Switches
+
+- 1 hart with RV64IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 intterupt line
+- Serial port with 1 interrupt line
+- 4 RGB LEDS
+- 4 Buttons and 4 Switches
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md
index 3aa021f..a640a47 100644
--- a/bsp/coreip-s51/README.md
+++ b/bsp/coreip-s51/README.md
@@ -1,8 +1,9 @@
 The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications.
 
 This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV64IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 8 regions
-        - 16 local interrupts signal that can be connected to off core complex devices
-        - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+
+- 1 hart with RV64IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md
index 1cc077e..faca2eb 100644
--- a/bsp/sifive-hifive1/README.md
+++ b/bsp/sifive-hifive1/README.md
@@ -1,12 +1,13 @@
 HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications.
 
 his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV32IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 8 regions
-        - 16 local interrupts signal that can be connected to off core complex devices
-        - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
-        - GPIO memory with 16 interrupt lines
-        - SPI memory with 1 intterupt line
-        - Serial port with 1 interrupt line
-        - 1 RGB LEDS
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 intterupt line
+- Serial port with 1 interrupt line
+- 1 RGB LEDS