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authorNathaniel Graff <nathaniel.graff@sifive.com>2018-12-17 16:25:19 -0800
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-01-03 13:22:14 -0800
commit4745766517d984d75b85d5497a9f2c68e8a39ce7 (patch)
tree2f15fb7f126a9e577e81cff47d069cad4761689f /bsp
parent093255eb95393d945d4e321d1dfa614669f8834b (diff)
HiFive 1 does not have an ITIM
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp')
-rw-r--r--bsp/sifive-hifive1/design.dts6
1 files changed, 0 insertions, 6 deletions
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts
index a71956a..26e4048 100644
--- a/bsp/sifive-hifive1/design.dts
+++ b/bsp/sifive-hifive1/design.dts
@@ -26,7 +26,6 @@
reg = <0>;
riscv,isa = "rv32imac";
sifive,dtim = <&dtim>;
- sifive,itim = <&itim>;
status = "okay";
timebase-frequency = <1000000>;
hlic: interrupt-controller {
@@ -147,11 +146,6 @@
reg = <0x80000000 0x4000>;
reg-names = "mem";
};
- itim: itim@8000000 {
- compatible = "sifive,itim0";
- reg = <0x8000000 0x4000>;
- reg-names = "mem";
- };
pwm@10015000 {
compatible = "sifive,pwm0";