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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-06 13:07:42 -0800
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-03-06 13:13:09 -0800
commit5a2e4697fc2e9a9e648188e53fe469256689f83f (patch)
treee094cac8d44317d2b731fe28f50dd04498f6a53f /bsp
parentc71689996d85011f3d493b8cbe75e1379bdbc932 (diff)
Fix HiFive1 Rev B BSP
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp')
-rw-r--r--bsp/sifive-hifive1-revb/design.dts4
-rw-r--r--bsp/sifive-hifive1-revb/metal.lds2
-rw-r--r--bsp/sifive-hifive1-revb/settings.mk2
3 files changed, 4 insertions, 4 deletions
diff --git a/bsp/sifive-hifive1-revb/design.dts b/bsp/sifive-hifive1-revb/design.dts
index 5f1797d..6c7da04 100644
--- a/bsp/sifive-hifive1-revb/design.dts
+++ b/bsp/sifive-hifive1-revb/design.dts
@@ -8,7 +8,7 @@
chosen {
stdout-path = "/soc/serial@10013000:115200";
- metal,entry = <&spi0 0x100000>;
+ metal,entry = <&spi0 0x10000>;
};
cpus {
@@ -180,7 +180,7 @@
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <6>;
- reg = <0x10014000 0x1000 0x20000000 0x20000000>;
+ reg = <0x10014000 0x1000 0x20000000 0x7A120>;
reg-names = "control", "mem";
clocks = <&hfclk>;
pinmux = <&gpio0 0x0003C 0x0003C>;
diff --git a/bsp/sifive-hifive1-revb/metal.lds b/bsp/sifive-hifive1-revb/metal.lds
index fdd23c7..f7050c4 100644
--- a/bsp/sifive-hifive1-revb/metal.lds
+++ b/bsp/sifive-hifive1-revb/metal.lds
@@ -5,7 +5,7 @@ ENTRY(_enter)
MEMORY
{
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
- flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x20000000
+ flash (rxai!w) : ORIGIN = 0x20010000, LENGTH = 0x6a120
}
PHDRS
diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk
index d84238b..61e2b02 100644
--- a/bsp/sifive-hifive1-revb/settings.mk
+++ b/bsp/sifive-hifive1-revb/settings.mk
@@ -1,4 +1,4 @@
RISCV_ARCH = rv32imac
RISCV_ABI = ilp32
RISCV_CMODEL = medlow
-COREIP_MEM_WIDTH = 32
+SEGGER_JLINK_OB = 1