added vectored interrupt example

3 files changed, 335 insertions, 2 deletions

diff --git a/bsp/env/coreplexip-e31-arty/init.c b/bsp/env/coreplexip-e31-arty/init.c
index 84ae09e..888f04f 100644
--- a/bsp/env/coreplexip-e31-arty/init.c
+++ b/bsp/env/coreplexip-e31-arty/init.c
@@ -10,8 +10,14 @@
 #define XSTR(x) #x
 #define STR(x) XSTR(x)
 
+#ifndef VECT_IRQ
+  #define TRAP_ENTRY trap_entry
+#else
+  #define TRAP_ENTRY vtrap_entry
+#endif
+
 extern int main(int argc, char** argv);
-extern void trap_entry();
+extern void TRAP_ENTRY();
 
 static unsigned long get_cpu_freq()
 {
@@ -57,6 +63,7 @@ typedef void (*my_interrupt_function_ptr_t) (void);
 extern my_interrupt_function_ptr_t localISR[];
 #endif
 
+#ifndef VECT_IRQ
 uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
 {
   if (0){
@@ -81,6 +88,7 @@ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
   }
   return epc;
 }
+#endif 
 
 void _init()
 {
@@ -89,7 +97,8 @@ void _init()
 
   puts("core freq at " STR(CPU_FREQ) " Hz\n");
 
-  write_csr(mtvec, &trap_entry);
+  write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED));
+
   #endif
 }
 
diff --git a/bsp/env/coreplexip-e31-arty/platform.h b/bsp/env/coreplexip-e31-arty/platform.h
index 42c8887..307a0c6 100644
--- a/bsp/env/coreplexip-e31-arty/platform.h
+++ b/bsp/env/coreplexip-e31-arty/platform.h
@@ -13,6 +13,11 @@
 #define MCAUSE_CAUSE       0x7FFFFFFFFFFFFFFFUL
 #endif
 
+#ifdef VECT_IRQ
+    #define MTVEC_VECTORED     0x01
+#else 
+    #define MTVEC_VECTORED     0x00
+#endif
 #define IRQ_M_LOCAL        16
 #define MIP_MLIP(x)        (1 << (IRQ_M_LOCAL + x))
 
diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S
new file mode 100644
index 0000000..9c2f118
--- /dev/null
+++ b/bsp/env/ventry.S
@@ -0,0 +1,319 @@
+// See LICENSE for license details
+
+#ifndef VENTRY_S
+#define VENTRY_S
+
+#include "encoding.h"
+#include "sifive/bits.h"
+
+.macro TRAP_ENTRY
+  addi sp, sp, -32*REGBYTES
+
+  STORE x1, 1*REGBYTES(sp)
+  STORE x2, 2*REGBYTES(sp)
+  STORE x3, 3*REGBYTES(sp)
+  STORE x4, 4*REGBYTES(sp)
+  STORE x5, 5*REGBYTES(sp)
+  STORE x6, 6*REGBYTES(sp)
+  STORE x7, 7*REGBYTES(sp)
+  STORE x8, 8*REGBYTES(sp)
+  STORE x9, 9*REGBYTES(sp)
+  STORE x10, 10*REGBYTES(sp)
+  STORE x11, 11*REGBYTES(sp)
+  STORE x12, 12*REGBYTES(sp)
+  STORE x13, 13*REGBYTES(sp)
+  STORE x14, 14*REGBYTES(sp)
+  STORE x15, 15*REGBYTES(sp)
+  STORE x16, 16*REGBYTES(sp)
+  STORE x17, 17*REGBYTES(sp)
+  STORE x18, 18*REGBYTES(sp)
+  STORE x19, 19*REGBYTES(sp)
+  STORE x20, 20*REGBYTES(sp)
+  STORE x21, 21*REGBYTES(sp)
+  STORE x22, 22*REGBYTES(sp)
+  STORE x23, 23*REGBYTES(sp)
+  STORE x24, 24*REGBYTES(sp)
+  STORE x25, 25*REGBYTES(sp)
+  STORE x26, 26*REGBYTES(sp)
+  STORE x27, 27*REGBYTES(sp)
+  STORE x28, 28*REGBYTES(sp)
+  STORE x29, 29*REGBYTES(sp)
+  STORE x30, 30*REGBYTES(sp)
+  STORE x31, 31*REGBYTES(sp)
+.endm
+
+# Remain in M-mode after mret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+.macro TRAP_EXIT
+  LOAD x1, 1*REGBYTES(sp)
+  LOAD x2, 2*REGBYTES(sp)
+  LOAD x3, 3*REGBYTES(sp)
+  LOAD x4, 4*REGBYTES(sp)
+  LOAD x5, 5*REGBYTES(sp)
+  LOAD x6, 6*REGBYTES(sp)
+  LOAD x7, 7*REGBYTES(sp)
+  LOAD x8, 8*REGBYTES(sp)
+  LOAD x9, 9*REGBYTES(sp)
+  LOAD x10, 10*REGBYTES(sp)
+  LOAD x11, 11*REGBYTES(sp)
+  LOAD x12, 12*REGBYTES(sp)
+  LOAD x13, 13*REGBYTES(sp)
+  LOAD x14, 14*REGBYTES(sp)
+  LOAD x15, 15*REGBYTES(sp)
+  LOAD x16, 16*REGBYTES(sp)
+  LOAD x17, 17*REGBYTES(sp)
+  LOAD x18, 18*REGBYTES(sp)
+  LOAD x19, 19*REGBYTES(sp)
+  LOAD x20, 20*REGBYTES(sp)
+  LOAD x21, 21*REGBYTES(sp)
+  LOAD x22, 22*REGBYTES(sp)
+  LOAD x23, 23*REGBYTES(sp)
+  LOAD x24, 24*REGBYTES(sp)
+  LOAD x25, 25*REGBYTES(sp)
+  LOAD x26, 26*REGBYTES(sp)
+  LOAD x27, 27*REGBYTES(sp)
+  LOAD x28, 28*REGBYTES(sp)
+  LOAD x29, 29*REGBYTES(sp)
+  LOAD x30, 30*REGBYTES(sp)
+  LOAD x31, 31*REGBYTES(sp)
+
+  addi sp, sp, 32*REGBYTES
+  mret
+.endm
+
+#Vector table for E31/E51
+
+  .section      .text.entry	
+  .align 8
+  .global vtrap_entry
+vtrap_entry:
+  j sync_trap
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+  .align 2
+  j vmsi_Handler
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+  .align 2
+  j vmti_Handler
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+  .align 2
+  j vmei_Handler
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+  .align 2
+  j reserved
+   .align 2
+  j reserved
+  .align 2
+  j vlip_Handler0
+  .align 2
+  j vlip_Handler1
+  .align 2
+  j vlip_Handler2
+  .align 2
+  j vlip_Handler3
+  .align 2
+  j vlip_Handler4
+  .align 2
+  .align 2
+  j vlip_Handler5
+  .align 2
+  j vlip_Handler6
+  .align 2
+  j vlip_Handler7
+  .align 2
+  j vlip_Handler8
+  .align 2
+  j vlip_Handler9
+  .align 2
+  j vlip_Handler10
+  .align 2
+  j vlip_Handler11
+  .align 2
+  j vlip_Handler12
+  .align 2
+  j vlip_Handler13
+  .align 2
+  j vlip_Handler14
+  .align 2
+  j vlip_Handler15
+  
+#synchronous trap
+sync_trap:
+  TRAP_ENTRY
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  jal handle_sync_trap
+  csrw mepc, a0
+  TRAP_EXIT
+
+#Machine Software Interrupt
+vmsi_Handler:
+  TRAP_ENTRY
+  jal reserved
+  TRAP_EXIT
+
+#Machine Timer Interrupt
+vmti_Handler:
+  TRAP_ENTRY
+  jal handle_m_time_interrupt
+  TRAP_EXIT
+
+#Machine External Interrupt
+vmei_Handler:
+  TRAP_ENTRY
+  jal handle_m_external_interrupt
+  TRAP_EXIT
+
+#LIP0
+vlip_Handler0:
+  TRAP_ENTRY
+  jal handle_local_interrupt0
+  TRAP_EXIT
+
+#LIP1
+vlip_Handler1:
+  TRAP_ENTRY
+  jal handle_local_interrupt1
+  TRAP_EXIT
+
+#LIP2
+vlip_Handler2:
+  TRAP_ENTRY
+  jal handle_local_interrupt2
+  TRAP_EXIT
+
+#LIP3
+vlip_Handler3:
+  TRAP_ENTRY
+  jal handle_local_interrupt3
+  TRAP_EXIT
+
+#LIP4
+vlip_Handler4:
+  TRAP_ENTRY
+  jal handle_local_interrupt4
+  TRAP_EXIT
+
+#LIP5
+vlip_Handler5:
+  TRAP_ENTRY
+  jal handle_local_interrupt5
+  TRAP_EXIT
+
+#LIP6
+vlip_Handler6:
+  TRAP_ENTRY
+  jal handle_local_interrupt6
+  TRAP_EXIT
+
+#LIP7
+vlip_Handler7:
+  TRAP_ENTRY
+  jal handle_local_interrupt7
+  TRAP_EXIT
+
+#LIP8
+vlip_Handler8:
+  TRAP_ENTRY
+  jal handle_local_interrupt8
+  TRAP_EXIT
+
+#LIP9
+vlip_Handler9:
+  TRAP_ENTRY
+  jal handle_local_interrupt9
+  TRAP_EXIT
+
+#LIP10
+vlip_Handler10:
+  TRAP_ENTRY
+  jal handle_local_interrupt10
+  TRAP_EXIT
+
+#LIP11
+vlip_Handler11:
+  TRAP_ENTRY
+  jal handle_local_interrupt11
+  TRAP_EXIT
+
+#LIP12
+vlip_Handler12:
+  TRAP_ENTRY
+  jal handle_local_interrupt12
+  TRAP_EXIT
+
+#LIP13
+vlip_Handler13:
+  TRAP_ENTRY
+  jal handle_local_interrupt13
+  TRAP_EXIT
+
+#LIP14
+vlip_Handler14:
+  TRAP_ENTRY
+  jal handle_local_interrupt14
+  TRAP_EXIT
+
+#LIP15
+vlip_Handler15:
+  TRAP_ENTRY
+  jal handle_local_interrupt15
+  TRAP_EXIT
+
+#unimplemented ISRs trap here
+.weak reserved
+reserved:
+.weak handle_local_interrupt0
+handle_local_interrupt0:
+.weak handle_local_interrupt1
+handle_local_interrupt1:
+.weak handle_local_interrupt2
+handle_local_interrupt2:
+.weak handle_local_interrupt3
+handle_local_interrupt3:
+.weak handle_local_interrupt4
+handle_local_interrupt4:
+.weak handle_local_interrupt5
+handle_local_interrupt5:
+.weak handle_local_interrupt6
+handle_local_interrupt6:
+.weak handle_local_interrupt7
+handle_local_interrupt7:
+.weak handle_local_interrupt8
+handle_local_interrupt8:
+.weak handle_local_interrupt9
+handle_local_interrupt9:
+.weak handle_local_interrupt10
+handle_local_interrupt10:
+.weak handle_local_interrupt11
+handle_local_interrupt11:
+.weak handle_local_interrupt12
+handle_local_interrupt12:
+.weak handle_local_interrupt13
+handle_local_interrupt13:
+.weak handle_local_interrupt14
+handle_local_interrupt14:
+.weak handle_local_interrupt15
+handle_local_interrupt15:
+1:
+  j 1b
+	
+#endif