Update BSP files to pickup inline support

168 files changed, 24255 insertions, 7262 deletions

diff --git a/bsp/coreip-e20-arty/metal-inline.h b/bsp/coreip-e20-arty/metal-inline.h
new file mode 100644
index 0000000..8170f13
--- /dev/null
+++ b/bsp/coreip-e20-arty/metal-inline.h
@@ -0,0 +1,260 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E20_ARTY__METAL_INLINE_H
+#define COREIP_E20_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller);
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@2000000 */
+struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_E20_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e20-arty/metal-platform.h b/bsp/coreip-e20-arty/metal-platform.h
index e952dd4..0e58533 100644
--- a/bsp/coreip-e20-arty/metal-platform.h
+++ b/bsp/coreip-e20-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E20_ARTY__METAL_PLATFORM_H
 #define COREIP_E20_ARTY__METAL_PLATFORM_H
 
@@ -8,10 +14,15 @@
 
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_0_SIZE 16777216UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 58UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTS 58UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMLEVELS 16UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTBITS 2UL
 
 #define METAL_SIFIVE_CLIC0
 #define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
@@ -26,9 +37,15 @@
 #define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
 #define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -49,9 +66,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -73,14 +139,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-e20-arty/metal.default.lds b/bsp/coreip-e20-arty/metal.default.lds
index 7b20841..2516d37 100644
--- a/bsp/coreip-e20-arty/metal.default.lds
+++ b/bsp/coreip-e20-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h
index 0517c64..5e182ab 100644
--- a/bsp/coreip-e20-arty/metal.h
+++ b/bsp/coreip-e20-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E20_ARTY__METAL_H
-#define COREIP_E20_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E20_ARTY__METAL_H
+#define MACROS_IF_COREIP_E20_ARTY__METAL_H
+
 #ifndef __METAL_CLINT_NUM_PARENTS
 #define __METAL_CLINT_NUM_PARENTS 0
 #endif
@@ -22,8 +28,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E20_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E20_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_E20_ARTY__METAL_H
+
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
 #define __METAL_CLINT_NUM_PARENTS 0
@@ -72,403 +83,837 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_sys_sram_0_80000000");
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@2000000 */
-asm (".weak __metal_dt_interrupt_controller_2000000");
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 32000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 32000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+static inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_MAX_CLIC_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 3;
+	}
+	else if (idx == 2) {
+		return 7;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 26;
+	}
+	else if (idx == 1) {
+		return 27;
+	}
+	else if (idx == 2) {
+		return 28;
+	}
+	else if (idx == 3) {
+		return 29;
+	}
+	else if (idx == 4) {
+		return 30;
+	}
+	else if (idx == 5) {
+		return 31;
+	}
+	else if (idx == 6) {
+		return 32;
+	}
+	else if (idx == 7) {
+		return 33;
+	}
+	else if (idx == 8) {
+		return 34;
+	}
+	else if (idx == 9) {
+		return 35;
+	}
+	else if (idx == 10) {
+		return 36;
+	}
+	else if (idx == 11) {
+		return 37;
+	}
+	else if (idx == 12) {
+		return 38;
+	}
+	else if (idx == 13) {
+		return 39;
+	}
+	else if (idx == 14) {
+		return 40;
+	}
+	else if (idx == 15) {
+		return 41;
+	}
+	else if (idx == 16) {
+		return 42;
+	}
+	else if (idx == 17) {
+		return 43;
+	}
+	else if (idx == 18) {
+		return 44;
+	}
+	else if (idx == 19) {
+		return 45;
+	}
+	else if (idx == 20) {
+		return 46;
+	}
+	else if (idx == 21) {
+		return 47;
+	}
+	else if (idx == 22) {
+		return 48;
+	}
+	else if (idx == 23) {
+		return 49;
+	}
+	else if (idx == 24) {
+		return 50;
+	}
+	else if (idx == 25) {
+		return 51;
+	}
+	else if (idx == 26) {
+		return 52;
+	}
+	else if (idx == 27) {
+		return 53;
+	}
+	else if (idx == 28) {
+		return 54;
+	}
+	else if (idx == 29) {
+		return 55;
+	}
+	else if (idx == 30) {
+		return 56;
+	}
+	else if (idx == 31) {
+		return 57;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 22;
+	}
+	else if (idx == 1) {
+		return 23;
+	}
+	else if (idx == 2) {
+		return 24;
+	}
+	else if (idx == 3) {
+		return 25;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 0;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 15;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 20;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 21;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 22;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 23;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 16;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 17;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 18;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 19;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From interrupt_controller@2000000 */
-struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
-    .vtable = &__metal_driver_vtable_sifive_clic0,
-    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_lines[1] = 7,
-    .interrupt_lines[2] = 11,
-    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
-    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
-    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
-    .interrupt_controller = 1,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 16;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 26,
-    .interrupt_lines[1] = 27,
-    .interrupt_lines[2] = 28,
-    .interrupt_lines[3] = 29,
-    .interrupt_lines[4] = 30,
-    .interrupt_lines[5] = 31,
-    .interrupt_lines[6] = 32,
-    .interrupt_lines[7] = 33,
-    .interrupt_lines[8] = 34,
-    .interrupt_lines[9] = 35,
-    .interrupt_lines[10] = 36,
-    .interrupt_lines[11] = 37,
-    .interrupt_lines[12] = 38,
-    .interrupt_lines[13] = 39,
-    .interrupt_lines[14] = 40,
-    .interrupt_lines[15] = 41,
-    .interrupt_lines[16] = 42,
-    .interrupt_lines[17] = 43,
-    .interrupt_lines[18] = 44,
-    .interrupt_lines[19] = 45,
-    .interrupt_lines[20] = 46,
-    .interrupt_lines[21] = 47,
-    .interrupt_lines[22] = 48,
-    .interrupt_lines[23] = 49,
-    .interrupt_lines[24] = 50,
-    .interrupt_lines[25] = 51,
-    .interrupt_lines[26] = 52,
-    .interrupt_lines[27] = 53,
-    .interrupt_lines[28] = 54,
-    .interrupt_lines[29] = 55,
-    .interrupt_lines[30] = 56,
-    .interrupt_lines[31] = 57,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 22,
-    .interrupt_lines[1] = 23,
-    .interrupt_lines[2] = 24,
-    .interrupt_lines[3] = 25,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 0,
-    .interrupt_lines[1] = 1,
-    .interrupt_lines[2] = 2,
-    .interrupt_lines[3] = 3,
-    .interrupt_lines[4] = 4,
-    .interrupt_lines[5] = 5,
-    .interrupt_lines[6] = 6,
-    .interrupt_lines[7] = 7,
-    .interrupt_lines[8] = 8,
-    .interrupt_lines[9] = 9,
-    .interrupt_lines[10] = 10,
-    .interrupt_lines[11] = 11,
-    .interrupt_lines[12] = 12,
-    .interrupt_lines[13] = 13,
-    .interrupt_lines[14] = 14,
-    .interrupt_lines[15] = 15,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 20UL,
-    .label = "BTN0",
-};
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 21UL,
-    .label = "BTN1",
-};
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 22UL,
-    .label = "BTN2",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 23UL,
-    .label = "BTN3",
-};
-
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
-
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
-
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 16UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 17UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 18UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 19UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 16UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 2
@@ -549,7 +994,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E20_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E20_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds
index 5fc1e00..0290158 100644
--- a/bsp/coreip-e20-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e20-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e20-arty/metal.scratchpad.lds b/bsp/coreip-e20-arty/metal.scratchpad.lds
index 4aa5569..5d4cd7b 100644
--- a/bsp/coreip-e20-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e20-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk
index c28ec0c..5a405fe 100644
--- a/bsp/coreip-e20-arty/settings.mk
+++ b/bsp/coreip-e20-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-09        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imc
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e20-rtl/metal-inline.h b/bsp/coreip-e20-rtl/metal-inline.h
new file mode 100644
index 0000000..1f2399d
--- /dev/null
+++ b/bsp/coreip-e20-rtl/metal-inline.h
@@ -0,0 +1,131 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E20_RTL__METAL_INLINE_H
+#define COREIP_E20_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller);
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 134217728UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@2000000 */
+struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_E20_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h
index 109562d..b4f13ec 100644
--- a/bsp/coreip-e20-rtl/metal-platform.h
+++ b/bsp/coreip-e20-rtl/metal-platform.h
@@ -1,12 +1,23 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E20_RTL__METAL_PLATFORM_H
 #define COREIP_E20_RTL__METAL_PLATFORM_H
 
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_0_SIZE 16777216UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 48UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTS 48UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMLEVELS 16UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTBITS 2UL
 
 #define METAL_SIFIVE_CLIC0
 #define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
@@ -21,9 +32,15 @@
 #define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
 #define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
 
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-e20-rtl/metal.default.lds b/bsp/coreip-e20-rtl/metal.default.lds
index 73490a3..c95e179 100644
--- a/bsp/coreip-e20-rtl/metal.default.lds
+++ b/bsp/coreip-e20-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h
index f031a28..68d33ad 100644
--- a/bsp/coreip-e20-rtl/metal.h
+++ b/bsp/coreip-e20-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E20_RTL__METAL_H
-#define COREIP_E20_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E20_RTL__METAL_H
+#define MACROS_IF_COREIP_E20_RTL__METAL_H
+
 #ifndef __METAL_CLINT_NUM_PARENTS
 #define __METAL_CLINT_NUM_PARENTS 0
 #endif
@@ -22,8 +28,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E20_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E20_RTL__METAL_H
+#define MACROS_ELSE_COREIP_E20_RTL__METAL_H
+
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
 #define __METAL_CLINT_NUM_PARENTS 0
@@ -58,123 +69,324 @@
 #include <metal/drivers/sifive,local-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@2000000 */
-asm (".weak __metal_dt_interrupt_controller_2000000");
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 134217728UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+static inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_MAX_CLIC_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 3;
+	}
+	else if (idx == 2) {
+		return 7;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 0;
+	}
+	else if (idx == 1) {
+		return 1;
+	}
+	else if (idx == 2) {
+		return 2;
+	}
+	else if (idx == 3) {
+		return 3;
+	}
+	else if (idx == 4) {
+		return 4;
+	}
+	else if (idx == 5) {
+		return 5;
+	}
+	else if (idx == 6) {
+		return 6;
+	}
+	else if (idx == 7) {
+		return 7;
+	}
+	else if (idx == 8) {
+		return 8;
+	}
+	else if (idx == 9) {
+		return 9;
+	}
+	else if (idx == 10) {
+		return 10;
+	}
+	else if (idx == 11) {
+		return 11;
+	}
+	else if (idx == 12) {
+		return 12;
+	}
+	else if (idx == 13) {
+		return 13;
+	}
+	else if (idx == 14) {
+		return 14;
+	}
+	else if (idx == 15) {
+		return 15;
+	}
+	else if (idx == 16) {
+		return 16;
+	}
+	else if (idx == 17) {
+		return 17;
+	}
+	else if (idx == 18) {
+		return 18;
+	}
+	else if (idx == 19) {
+		return 19;
+	}
+	else if (idx == 20) {
+		return 20;
+	}
+	else if (idx == 21) {
+		return 21;
+	}
+	else if (idx == 22) {
+		return 22;
+	}
+	else if (idx == 23) {
+		return 23;
+	}
+	else if (idx == 24) {
+		return 24;
+	}
+	else if (idx == 25) {
+		return 25;
+	}
+	else if (idx == 26) {
+		return 26;
+	}
+	else if (idx == 27) {
+		return 27;
+	}
+	else if (idx == 28) {
+		return 28;
+	}
+	else if (idx == 29) {
+		return 29;
+	}
+	else if (idx == 30) {
+		return 30;
+	}
+	else if (idx == 31) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
 
-/* From interrupt_controller@2000000 */
-struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
-    .vtable = &__metal_driver_vtable_sifive_clic0,
-    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_lines[1] = 7,
-    .interrupt_lines[2] = 11,
-    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
-    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
-    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
-    .interrupt_controller = 1,
-};
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 0,
-    .interrupt_lines[1] = 1,
-    .interrupt_lines[2] = 2,
-    .interrupt_lines[3] = 3,
-    .interrupt_lines[4] = 4,
-    .interrupt_lines[5] = 5,
-    .interrupt_lines[6] = 6,
-    .interrupt_lines[7] = 7,
-    .interrupt_lines[8] = 8,
-    .interrupt_lines[9] = 9,
-    .interrupt_lines[10] = 10,
-    .interrupt_lines[11] = 11,
-    .interrupt_lines[12] = 12,
-    .interrupt_lines[13] = 13,
-    .interrupt_lines[14] = 14,
-    .interrupt_lines[15] = 15,
-    .interrupt_lines[16] = 16,
-    .interrupt_lines[17] = 17,
-    .interrupt_lines[18] = 18,
-    .interrupt_lines[19] = 19,
-    .interrupt_lines[20] = 20,
-    .interrupt_lines[21] = 21,
-    .interrupt_lines[22] = 22,
-    .interrupt_lines[23] = 23,
-    .interrupt_lines[24] = 24,
-    .interrupt_lines[25] = 25,
-    .interrupt_lines[26] = 26,
-    .interrupt_lines[27] = 27,
-    .interrupt_lines[28] = 28,
-    .interrupt_lines[29] = 29,
-    .interrupt_lines[30] = 30,
-    .interrupt_lines[31] = 31,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 1
@@ -229,7 +441,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E20_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E20_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e20-rtl/metal.ramrodata.lds b/bsp/coreip-e20-rtl/metal.ramrodata.lds
index 4feb009..02f50c8 100644
--- a/bsp/coreip-e20-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e20-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -160,18 +166,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e20-rtl/metal.scratchpad.lds b/bsp/coreip-e20-rtl/metal.scratchpad.lds
index 73490a3..c95e179 100644
--- a/bsp/coreip-e20-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e20-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-09        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk
index 699498e..6520e6d 100644
--- a/bsp/coreip-e20-rtl/settings.mk
+++ b/bsp/coreip-e20-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-09        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imc
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e21-arty/metal-inline.h b/bsp/coreip-e21-arty/metal-inline.h
new file mode 100644
index 0000000..0f167d5
--- /dev/null
+++ b/bsp/coreip-e21-arty/metal-inline.h
@@ -0,0 +1,276 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E21_ARTY__METAL_INLINE_H
+#define COREIP_E21_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller);
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
+    ._base_address = 2147516416UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From interrupt_controller@2000000 */
+struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_E21_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h
index 3daf97d..75dc2dd 100644
--- a/bsp/coreip-e21-arty/metal-platform.h
+++ b/bsp/coreip-e21-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E21_ARTY__METAL_PLATFORM_H
 #define COREIP_E21_ARTY__METAL_PLATFORM_H
 
@@ -13,10 +19,15 @@
 
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_0_SIZE 16777216UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 153UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTS 153UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMLEVELS 16UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTBITS 2UL
 
 #define METAL_SIFIVE_CLIC0
 #define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
@@ -31,9 +42,15 @@
 #define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
 #define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -54,9 +71,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -78,14 +144,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds
index 3358fbe..0b7a37a 100644
--- a/bsp/coreip-e21-arty/metal.default.lds
+++ b/bsp/coreip-e21-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h
index 30fd7ef..89b2931 100644
--- a/bsp/coreip-e21-arty/metal.h
+++ b/bsp/coreip-e21-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E21_ARTY__METAL_H
-#define COREIP_E21_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E21_ARTY__METAL_H
+#define MACROS_IF_COREIP_E21_ARTY__METAL_H
+
 #ifndef __METAL_CLINT_NUM_PARENTS
 #define __METAL_CLINT_NUM_PARENTS 0
 #endif
@@ -22,8 +28,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E21_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E21_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_E21_ARTY__METAL_H
+
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
 #define __METAL_CLINT_NUM_PARENTS 0
@@ -72,520 +83,1126 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_sys_sram_0_80000000");
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000;
 
-asm (".weak __metal_dt_mem_sys_sram_1_80008000");
 struct metal_memory __metal_dt_mem_sys_sram_1_80008000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From interrupt_controller@2000000 */
-asm (".weak __metal_dt_interrupt_controller_2000000");
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
-    ._base_address = 2147516416UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 32000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 32000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+static inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_MAX_CLIC_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 3;
+	}
+	else if (idx == 2) {
+		return 7;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 26;
+	}
+	else if (idx == 1) {
+		return 27;
+	}
+	else if (idx == 2) {
+		return 28;
+	}
+	else if (idx == 3) {
+		return 29;
+	}
+	else if (idx == 4) {
+		return 30;
+	}
+	else if (idx == 5) {
+		return 31;
+	}
+	else if (idx == 6) {
+		return 32;
+	}
+	else if (idx == 7) {
+		return 33;
+	}
+	else if (idx == 8) {
+		return 34;
+	}
+	else if (idx == 9) {
+		return 35;
+	}
+	else if (idx == 10) {
+		return 36;
+	}
+	else if (idx == 11) {
+		return 37;
+	}
+	else if (idx == 12) {
+		return 38;
+	}
+	else if (idx == 13) {
+		return 39;
+	}
+	else if (idx == 14) {
+		return 40;
+	}
+	else if (idx == 15) {
+		return 41;
+	}
+	else if (idx == 16) {
+		return 42;
+	}
+	else if (idx == 17) {
+		return 43;
+	}
+	else if (idx == 18) {
+		return 44;
+	}
+	else if (idx == 19) {
+		return 45;
+	}
+	else if (idx == 20) {
+		return 46;
+	}
+	else if (idx == 21) {
+		return 47;
+	}
+	else if (idx == 22) {
+		return 48;
+	}
+	else if (idx == 23) {
+		return 49;
+	}
+	else if (idx == 24) {
+		return 50;
+	}
+	else if (idx == 25) {
+		return 51;
+	}
+	else if (idx == 26) {
+		return 52;
+	}
+	else if (idx == 27) {
+		return 53;
+	}
+	else if (idx == 28) {
+		return 54;
+	}
+	else if (idx == 29) {
+		return 55;
+	}
+	else if (idx == 30) {
+		return 56;
+	}
+	else if (idx == 31) {
+		return 57;
+	}
+	else if (idx == 32) {
+		return 58;
+	}
+	else if (idx == 33) {
+		return 59;
+	}
+	else if (idx == 34) {
+		return 60;
+	}
+	else if (idx == 35) {
+		return 61;
+	}
+	else if (idx == 36) {
+		return 62;
+	}
+	else if (idx == 37) {
+		return 63;
+	}
+	else if (idx == 38) {
+		return 64;
+	}
+	else if (idx == 39) {
+		return 65;
+	}
+	else if (idx == 40) {
+		return 66;
+	}
+	else if (idx == 41) {
+		return 67;
+	}
+	else if (idx == 42) {
+		return 68;
+	}
+	else if (idx == 43) {
+		return 69;
+	}
+	else if (idx == 44) {
+		return 70;
+	}
+	else if (idx == 45) {
+		return 71;
+	}
+	else if (idx == 46) {
+		return 72;
+	}
+	else if (idx == 47) {
+		return 73;
+	}
+	else if (idx == 48) {
+		return 74;
+	}
+	else if (idx == 49) {
+		return 75;
+	}
+	else if (idx == 50) {
+		return 76;
+	}
+	else if (idx == 51) {
+		return 77;
+	}
+	else if (idx == 52) {
+		return 78;
+	}
+	else if (idx == 53) {
+		return 79;
+	}
+	else if (idx == 54) {
+		return 80;
+	}
+	else if (idx == 55) {
+		return 81;
+	}
+	else if (idx == 56) {
+		return 82;
+	}
+	else if (idx == 57) {
+		return 83;
+	}
+	else if (idx == 58) {
+		return 84;
+	}
+	else if (idx == 59) {
+		return 85;
+	}
+	else if (idx == 60) {
+		return 86;
+	}
+	else if (idx == 61) {
+		return 87;
+	}
+	else if (idx == 62) {
+		return 88;
+	}
+	else if (idx == 63) {
+		return 89;
+	}
+	else if (idx == 64) {
+		return 90;
+	}
+	else if (idx == 65) {
+		return 91;
+	}
+	else if (idx == 66) {
+		return 92;
+	}
+	else if (idx == 67) {
+		return 93;
+	}
+	else if (idx == 68) {
+		return 94;
+	}
+	else if (idx == 69) {
+		return 95;
+	}
+	else if (idx == 70) {
+		return 96;
+	}
+	else if (idx == 71) {
+		return 97;
+	}
+	else if (idx == 72) {
+		return 98;
+	}
+	else if (idx == 73) {
+		return 99;
+	}
+	else if (idx == 74) {
+		return 100;
+	}
+	else if (idx == 75) {
+		return 101;
+	}
+	else if (idx == 76) {
+		return 102;
+	}
+	else if (idx == 77) {
+		return 103;
+	}
+	else if (idx == 78) {
+		return 104;
+	}
+	else if (idx == 79) {
+		return 105;
+	}
+	else if (idx == 80) {
+		return 106;
+	}
+	else if (idx == 81) {
+		return 107;
+	}
+	else if (idx == 82) {
+		return 108;
+	}
+	else if (idx == 83) {
+		return 109;
+	}
+	else if (idx == 84) {
+		return 110;
+	}
+	else if (idx == 85) {
+		return 111;
+	}
+	else if (idx == 86) {
+		return 112;
+	}
+	else if (idx == 87) {
+		return 113;
+	}
+	else if (idx == 88) {
+		return 114;
+	}
+	else if (idx == 89) {
+		return 115;
+	}
+	else if (idx == 90) {
+		return 116;
+	}
+	else if (idx == 91) {
+		return 117;
+	}
+	else if (idx == 92) {
+		return 118;
+	}
+	else if (idx == 93) {
+		return 119;
+	}
+	else if (idx == 94) {
+		return 120;
+	}
+	else if (idx == 95) {
+		return 121;
+	}
+	else if (idx == 96) {
+		return 122;
+	}
+	else if (idx == 97) {
+		return 123;
+	}
+	else if (idx == 98) {
+		return 124;
+	}
+	else if (idx == 99) {
+		return 125;
+	}
+	else if (idx == 100) {
+		return 126;
+	}
+	else if (idx == 101) {
+		return 127;
+	}
+	else if (idx == 102) {
+		return 128;
+	}
+	else if (idx == 103) {
+		return 129;
+	}
+	else if (idx == 104) {
+		return 130;
+	}
+	else if (idx == 105) {
+		return 131;
+	}
+	else if (idx == 106) {
+		return 132;
+	}
+	else if (idx == 107) {
+		return 133;
+	}
+	else if (idx == 108) {
+		return 134;
+	}
+	else if (idx == 109) {
+		return 135;
+	}
+	else if (idx == 110) {
+		return 136;
+	}
+	else if (idx == 111) {
+		return 137;
+	}
+	else if (idx == 112) {
+		return 138;
+	}
+	else if (idx == 113) {
+		return 139;
+	}
+	else if (idx == 114) {
+		return 140;
+	}
+	else if (idx == 115) {
+		return 141;
+	}
+	else if (idx == 116) {
+		return 142;
+	}
+	else if (idx == 117) {
+		return 143;
+	}
+	else if (idx == 118) {
+		return 144;
+	}
+	else if (idx == 119) {
+		return 145;
+	}
+	else if (idx == 120) {
+		return 146;
+	}
+	else if (idx == 121) {
+		return 147;
+	}
+	else if (idx == 122) {
+		return 148;
+	}
+	else if (idx == 123) {
+		return 149;
+	}
+	else if (idx == 124) {
+		return 150;
+	}
+	else if (idx == 125) {
+		return 151;
+	}
+	else if (idx == 126) {
+		return 152;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 22;
+	}
+	else if (idx == 1) {
+		return 23;
+	}
+	else if (idx == 2) {
+		return 24;
+	}
+	else if (idx == 3) {
+		return 25;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 0;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 15;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 20;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 21;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 22;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 23;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 16;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 17;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 18;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 19;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 16;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From interrupt_controller@2000000 */
-struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
-    .vtable = &__metal_driver_vtable_sifive_clic0,
-    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_lines[1] = 7,
-    .interrupt_lines[2] = 11,
-    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
-    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
-    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
-    .interrupt_controller = 1,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 26,
-    .interrupt_lines[1] = 27,
-    .interrupt_lines[2] = 28,
-    .interrupt_lines[3] = 29,
-    .interrupt_lines[4] = 30,
-    .interrupt_lines[5] = 31,
-    .interrupt_lines[6] = 32,
-    .interrupt_lines[7] = 33,
-    .interrupt_lines[8] = 34,
-    .interrupt_lines[9] = 35,
-    .interrupt_lines[10] = 36,
-    .interrupt_lines[11] = 37,
-    .interrupt_lines[12] = 38,
-    .interrupt_lines[13] = 39,
-    .interrupt_lines[14] = 40,
-    .interrupt_lines[15] = 41,
-    .interrupt_lines[16] = 42,
-    .interrupt_lines[17] = 43,
-    .interrupt_lines[18] = 44,
-    .interrupt_lines[19] = 45,
-    .interrupt_lines[20] = 46,
-    .interrupt_lines[21] = 47,
-    .interrupt_lines[22] = 48,
-    .interrupt_lines[23] = 49,
-    .interrupt_lines[24] = 50,
-    .interrupt_lines[25] = 51,
-    .interrupt_lines[26] = 52,
-    .interrupt_lines[27] = 53,
-    .interrupt_lines[28] = 54,
-    .interrupt_lines[29] = 55,
-    .interrupt_lines[30] = 56,
-    .interrupt_lines[31] = 57,
-    .interrupt_lines[32] = 58,
-    .interrupt_lines[33] = 59,
-    .interrupt_lines[34] = 60,
-    .interrupt_lines[35] = 61,
-    .interrupt_lines[36] = 62,
-    .interrupt_lines[37] = 63,
-    .interrupt_lines[38] = 64,
-    .interrupt_lines[39] = 65,
-    .interrupt_lines[40] = 66,
-    .interrupt_lines[41] = 67,
-    .interrupt_lines[42] = 68,
-    .interrupt_lines[43] = 69,
-    .interrupt_lines[44] = 70,
-    .interrupt_lines[45] = 71,
-    .interrupt_lines[46] = 72,
-    .interrupt_lines[47] = 73,
-    .interrupt_lines[48] = 74,
-    .interrupt_lines[49] = 75,
-    .interrupt_lines[50] = 76,
-    .interrupt_lines[51] = 77,
-    .interrupt_lines[52] = 78,
-    .interrupt_lines[53] = 79,
-    .interrupt_lines[54] = 80,
-    .interrupt_lines[55] = 81,
-    .interrupt_lines[56] = 82,
-    .interrupt_lines[57] = 83,
-    .interrupt_lines[58] = 84,
-    .interrupt_lines[59] = 85,
-    .interrupt_lines[60] = 86,
-    .interrupt_lines[61] = 87,
-    .interrupt_lines[62] = 88,
-    .interrupt_lines[63] = 89,
-    .interrupt_lines[64] = 90,
-    .interrupt_lines[65] = 91,
-    .interrupt_lines[66] = 92,
-    .interrupt_lines[67] = 93,
-    .interrupt_lines[68] = 94,
-    .interrupt_lines[69] = 95,
-    .interrupt_lines[70] = 96,
-    .interrupt_lines[71] = 97,
-    .interrupt_lines[72] = 98,
-    .interrupt_lines[73] = 99,
-    .interrupt_lines[74] = 100,
-    .interrupt_lines[75] = 101,
-    .interrupt_lines[76] = 102,
-    .interrupt_lines[77] = 103,
-    .interrupt_lines[78] = 104,
-    .interrupt_lines[79] = 105,
-    .interrupt_lines[80] = 106,
-    .interrupt_lines[81] = 107,
-    .interrupt_lines[82] = 108,
-    .interrupt_lines[83] = 109,
-    .interrupt_lines[84] = 110,
-    .interrupt_lines[85] = 111,
-    .interrupt_lines[86] = 112,
-    .interrupt_lines[87] = 113,
-    .interrupt_lines[88] = 114,
-    .interrupt_lines[89] = 115,
-    .interrupt_lines[90] = 116,
-    .interrupt_lines[91] = 117,
-    .interrupt_lines[92] = 118,
-    .interrupt_lines[93] = 119,
-    .interrupt_lines[94] = 120,
-    .interrupt_lines[95] = 121,
-    .interrupt_lines[96] = 122,
-    .interrupt_lines[97] = 123,
-    .interrupt_lines[98] = 124,
-    .interrupt_lines[99] = 125,
-    .interrupt_lines[100] = 126,
-    .interrupt_lines[101] = 127,
-    .interrupt_lines[102] = 128,
-    .interrupt_lines[103] = 129,
-    .interrupt_lines[104] = 130,
-    .interrupt_lines[105] = 131,
-    .interrupt_lines[106] = 132,
-    .interrupt_lines[107] = 133,
-    .interrupt_lines[108] = 134,
-    .interrupt_lines[109] = 135,
-    .interrupt_lines[110] = 136,
-    .interrupt_lines[111] = 137,
-    .interrupt_lines[112] = 138,
-    .interrupt_lines[113] = 139,
-    .interrupt_lines[114] = 140,
-    .interrupt_lines[115] = 141,
-    .interrupt_lines[116] = 142,
-    .interrupt_lines[117] = 143,
-    .interrupt_lines[118] = 144,
-    .interrupt_lines[119] = 145,
-    .interrupt_lines[120] = 146,
-    .interrupt_lines[121] = 147,
-    .interrupt_lines[122] = 148,
-    .interrupt_lines[123] = 149,
-    .interrupt_lines[124] = 150,
-    .interrupt_lines[125] = 151,
-    .interrupt_lines[126] = 152,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 22,
-    .interrupt_lines[1] = 23,
-    .interrupt_lines[2] = 24,
-    .interrupt_lines[3] = 25,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 0,
-    .interrupt_lines[1] = 1,
-    .interrupt_lines[2] = 2,
-    .interrupt_lines[3] = 3,
-    .interrupt_lines[4] = 4,
-    .interrupt_lines[5] = 5,
-    .interrupt_lines[6] = 6,
-    .interrupt_lines[7] = 7,
-    .interrupt_lines[8] = 8,
-    .interrupt_lines[9] = 9,
-    .interrupt_lines[10] = 10,
-    .interrupt_lines[11] = 11,
-    .interrupt_lines[12] = 12,
-    .interrupt_lines[13] = 13,
-    .interrupt_lines[14] = 14,
-    .interrupt_lines[15] = 15,
-};
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 20UL,
-    .label = "BTN0",
-};
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 21UL,
-    .label = "BTN1",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 22UL,
-    .label = "BTN2",
-};
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 23UL,
-    .label = "BTN3",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 16UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 17UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 18UL,
-    .label = "SW2",
-};
-
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 19UL,
-    .label = "SW3",
-};
-
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
-
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
-
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 16UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -670,7 +1287,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E21_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E21_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds
index 90b3388..e1e793f 100644
--- a/bsp/coreip-e21-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e21-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -165,18 +171,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds
index 01ee127..e986066 100644
--- a/bsp/coreip-e21-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e21-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk
index 0b9c2cb..b9be584 100644
--- a/bsp/coreip-e21-arty/settings.mk
+++ b/bsp/coreip-e21-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e21-rtl/metal-inline.h b/bsp/coreip-e21-rtl/metal-inline.h
new file mode 100644
index 0000000..a117144
--- /dev/null
+++ b/bsp/coreip-e21-rtl/metal-inline.h
@@ -0,0 +1,158 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E21_RTL__METAL_INLINE_H
+#define COREIP_E21_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller);
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
+    ._base_address = 2147516416UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 134217728UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From interrupt_controller@2000000 */
+struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_E21_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e21-rtl/metal-platform.h b/bsp/coreip-e21-rtl/metal-platform.h
index 9785d80..baf85fc 100644
--- a/bsp/coreip-e21-rtl/metal-platform.h
+++ b/bsp/coreip-e21-rtl/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E21_RTL__METAL_PLATFORM_H
 #define COREIP_E21_RTL__METAL_PLATFORM_H
 
@@ -8,10 +14,15 @@
 
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_0_SIZE 16777216UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 143UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTS 143UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMLEVELS 16UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTBITS 2UL
 
 #define METAL_SIFIVE_CLIC0
 #define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
@@ -26,9 +37,15 @@
 #define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
 #define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
 
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-e21-rtl/metal.default.lds b/bsp/coreip-e21-rtl/metal.default.lds
index a3c999a..d021e81 100644
--- a/bsp/coreip-e21-rtl/metal.default.lds
+++ b/bsp/coreip-e21-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h
index d90b0a7..38b19a4 100644
--- a/bsp/coreip-e21-rtl/metal.h
+++ b/bsp/coreip-e21-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E21_RTL__METAL_H
-#define COREIP_E21_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E21_RTL__METAL_H
+#define MACROS_IF_COREIP_E21_RTL__METAL_H
+
 #ifndef __METAL_CLINT_NUM_PARENTS
 #define __METAL_CLINT_NUM_PARENTS 0
 #endif
@@ -22,8 +28,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E21_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E21_RTL__METAL_H
+#define MACROS_ELSE_COREIP_E21_RTL__METAL_H
+
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
 #define __METAL_CLINT_NUM_PARENTS 0
@@ -58,254 +69,615 @@
 #include <metal/drivers/sifive,local-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_sys_sram_0_80000000");
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000;
 
-asm (".weak __metal_dt_mem_sys_sram_1_80008000");
 struct metal_memory __metal_dt_mem_sys_sram_1_80008000;
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From interrupt_controller@2000000 */
-asm (".weak __metal_dt_interrupt_controller_2000000");
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
-    ._base_address = 2147516416UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 134217728UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+static inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_MAX_CLIC_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 3;
+	}
+	else if (idx == 2) {
+		return 7;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 0;
+	}
+	else if (idx == 1) {
+		return 1;
+	}
+	else if (idx == 2) {
+		return 2;
+	}
+	else if (idx == 3) {
+		return 3;
+	}
+	else if (idx == 4) {
+		return 4;
+	}
+	else if (idx == 5) {
+		return 5;
+	}
+	else if (idx == 6) {
+		return 6;
+	}
+	else if (idx == 7) {
+		return 7;
+	}
+	else if (idx == 8) {
+		return 8;
+	}
+	else if (idx == 9) {
+		return 9;
+	}
+	else if (idx == 10) {
+		return 10;
+	}
+	else if (idx == 11) {
+		return 11;
+	}
+	else if (idx == 12) {
+		return 12;
+	}
+	else if (idx == 13) {
+		return 13;
+	}
+	else if (idx == 14) {
+		return 14;
+	}
+	else if (idx == 15) {
+		return 15;
+	}
+	else if (idx == 16) {
+		return 16;
+	}
+	else if (idx == 17) {
+		return 17;
+	}
+	else if (idx == 18) {
+		return 18;
+	}
+	else if (idx == 19) {
+		return 19;
+	}
+	else if (idx == 20) {
+		return 20;
+	}
+	else if (idx == 21) {
+		return 21;
+	}
+	else if (idx == 22) {
+		return 22;
+	}
+	else if (idx == 23) {
+		return 23;
+	}
+	else if (idx == 24) {
+		return 24;
+	}
+	else if (idx == 25) {
+		return 25;
+	}
+	else if (idx == 26) {
+		return 26;
+	}
+	else if (idx == 27) {
+		return 27;
+	}
+	else if (idx == 28) {
+		return 28;
+	}
+	else if (idx == 29) {
+		return 29;
+	}
+	else if (idx == 30) {
+		return 30;
+	}
+	else if (idx == 31) {
+		return 31;
+	}
+	else if (idx == 32) {
+		return 32;
+	}
+	else if (idx == 33) {
+		return 33;
+	}
+	else if (idx == 34) {
+		return 34;
+	}
+	else if (idx == 35) {
+		return 35;
+	}
+	else if (idx == 36) {
+		return 36;
+	}
+	else if (idx == 37) {
+		return 37;
+	}
+	else if (idx == 38) {
+		return 38;
+	}
+	else if (idx == 39) {
+		return 39;
+	}
+	else if (idx == 40) {
+		return 40;
+	}
+	else if (idx == 41) {
+		return 41;
+	}
+	else if (idx == 42) {
+		return 42;
+	}
+	else if (idx == 43) {
+		return 43;
+	}
+	else if (idx == 44) {
+		return 44;
+	}
+	else if (idx == 45) {
+		return 45;
+	}
+	else if (idx == 46) {
+		return 46;
+	}
+	else if (idx == 47) {
+		return 47;
+	}
+	else if (idx == 48) {
+		return 48;
+	}
+	else if (idx == 49) {
+		return 49;
+	}
+	else if (idx == 50) {
+		return 50;
+	}
+	else if (idx == 51) {
+		return 51;
+	}
+	else if (idx == 52) {
+		return 52;
+	}
+	else if (idx == 53) {
+		return 53;
+	}
+	else if (idx == 54) {
+		return 54;
+	}
+	else if (idx == 55) {
+		return 55;
+	}
+	else if (idx == 56) {
+		return 56;
+	}
+	else if (idx == 57) {
+		return 57;
+	}
+	else if (idx == 58) {
+		return 58;
+	}
+	else if (idx == 59) {
+		return 59;
+	}
+	else if (idx == 60) {
+		return 60;
+	}
+	else if (idx == 61) {
+		return 61;
+	}
+	else if (idx == 62) {
+		return 62;
+	}
+	else if (idx == 63) {
+		return 63;
+	}
+	else if (idx == 64) {
+		return 64;
+	}
+	else if (idx == 65) {
+		return 65;
+	}
+	else if (idx == 66) {
+		return 66;
+	}
+	else if (idx == 67) {
+		return 67;
+	}
+	else if (idx == 68) {
+		return 68;
+	}
+	else if (idx == 69) {
+		return 69;
+	}
+	else if (idx == 70) {
+		return 70;
+	}
+	else if (idx == 71) {
+		return 71;
+	}
+	else if (idx == 72) {
+		return 72;
+	}
+	else if (idx == 73) {
+		return 73;
+	}
+	else if (idx == 74) {
+		return 74;
+	}
+	else if (idx == 75) {
+		return 75;
+	}
+	else if (idx == 76) {
+		return 76;
+	}
+	else if (idx == 77) {
+		return 77;
+	}
+	else if (idx == 78) {
+		return 78;
+	}
+	else if (idx == 79) {
+		return 79;
+	}
+	else if (idx == 80) {
+		return 80;
+	}
+	else if (idx == 81) {
+		return 81;
+	}
+	else if (idx == 82) {
+		return 82;
+	}
+	else if (idx == 83) {
+		return 83;
+	}
+	else if (idx == 84) {
+		return 84;
+	}
+	else if (idx == 85) {
+		return 85;
+	}
+	else if (idx == 86) {
+		return 86;
+	}
+	else if (idx == 87) {
+		return 87;
+	}
+	else if (idx == 88) {
+		return 88;
+	}
+	else if (idx == 89) {
+		return 89;
+	}
+	else if (idx == 90) {
+		return 90;
+	}
+	else if (idx == 91) {
+		return 91;
+	}
+	else if (idx == 92) {
+		return 92;
+	}
+	else if (idx == 93) {
+		return 93;
+	}
+	else if (idx == 94) {
+		return 94;
+	}
+	else if (idx == 95) {
+		return 95;
+	}
+	else if (idx == 96) {
+		return 96;
+	}
+	else if (idx == 97) {
+		return 97;
+	}
+	else if (idx == 98) {
+		return 98;
+	}
+	else if (idx == 99) {
+		return 99;
+	}
+	else if (idx == 100) {
+		return 100;
+	}
+	else if (idx == 101) {
+		return 101;
+	}
+	else if (idx == 102) {
+		return 102;
+	}
+	else if (idx == 103) {
+		return 103;
+	}
+	else if (idx == 104) {
+		return 104;
+	}
+	else if (idx == 105) {
+		return 105;
+	}
+	else if (idx == 106) {
+		return 106;
+	}
+	else if (idx == 107) {
+		return 107;
+	}
+	else if (idx == 108) {
+		return 108;
+	}
+	else if (idx == 109) {
+		return 109;
+	}
+	else if (idx == 110) {
+		return 110;
+	}
+	else if (idx == 111) {
+		return 111;
+	}
+	else if (idx == 112) {
+		return 112;
+	}
+	else if (idx == 113) {
+		return 113;
+	}
+	else if (idx == 114) {
+		return 114;
+	}
+	else if (idx == 115) {
+		return 115;
+	}
+	else if (idx == 116) {
+		return 116;
+	}
+	else if (idx == 117) {
+		return 117;
+	}
+	else if (idx == 118) {
+		return 118;
+	}
+	else if (idx == 119) {
+		return 119;
+	}
+	else if (idx == 120) {
+		return 120;
+	}
+	else if (idx == 121) {
+		return 121;
+	}
+	else if (idx == 122) {
+		return 122;
+	}
+	else if (idx == 123) {
+		return 123;
+	}
+	else if (idx == 124) {
+		return 124;
+	}
+	else if (idx == 125) {
+		return 125;
+	}
+	else if (idx == 126) {
+		return 126;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
 
-/* From interrupt_controller@2000000 */
-struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
-    .vtable = &__metal_driver_vtable_sifive_clic0,
-    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_lines[1] = 7,
-    .interrupt_lines[2] = 11,
-    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
-    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
-    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
-    .interrupt_controller = 1,
-};
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 0,
-    .interrupt_lines[1] = 1,
-    .interrupt_lines[2] = 2,
-    .interrupt_lines[3] = 3,
-    .interrupt_lines[4] = 4,
-    .interrupt_lines[5] = 5,
-    .interrupt_lines[6] = 6,
-    .interrupt_lines[7] = 7,
-    .interrupt_lines[8] = 8,
-    .interrupt_lines[9] = 9,
-    .interrupt_lines[10] = 10,
-    .interrupt_lines[11] = 11,
-    .interrupt_lines[12] = 12,
-    .interrupt_lines[13] = 13,
-    .interrupt_lines[14] = 14,
-    .interrupt_lines[15] = 15,
-    .interrupt_lines[16] = 16,
-    .interrupt_lines[17] = 17,
-    .interrupt_lines[18] = 18,
-    .interrupt_lines[19] = 19,
-    .interrupt_lines[20] = 20,
-    .interrupt_lines[21] = 21,
-    .interrupt_lines[22] = 22,
-    .interrupt_lines[23] = 23,
-    .interrupt_lines[24] = 24,
-    .interrupt_lines[25] = 25,
-    .interrupt_lines[26] = 26,
-    .interrupt_lines[27] = 27,
-    .interrupt_lines[28] = 28,
-    .interrupt_lines[29] = 29,
-    .interrupt_lines[30] = 30,
-    .interrupt_lines[31] = 31,
-    .interrupt_lines[32] = 32,
-    .interrupt_lines[33] = 33,
-    .interrupt_lines[34] = 34,
-    .interrupt_lines[35] = 35,
-    .interrupt_lines[36] = 36,
-    .interrupt_lines[37] = 37,
-    .interrupt_lines[38] = 38,
-    .interrupt_lines[39] = 39,
-    .interrupt_lines[40] = 40,
-    .interrupt_lines[41] = 41,
-    .interrupt_lines[42] = 42,
-    .interrupt_lines[43] = 43,
-    .interrupt_lines[44] = 44,
-    .interrupt_lines[45] = 45,
-    .interrupt_lines[46] = 46,
-    .interrupt_lines[47] = 47,
-    .interrupt_lines[48] = 48,
-    .interrupt_lines[49] = 49,
-    .interrupt_lines[50] = 50,
-    .interrupt_lines[51] = 51,
-    .interrupt_lines[52] = 52,
-    .interrupt_lines[53] = 53,
-    .interrupt_lines[54] = 54,
-    .interrupt_lines[55] = 55,
-    .interrupt_lines[56] = 56,
-    .interrupt_lines[57] = 57,
-    .interrupt_lines[58] = 58,
-    .interrupt_lines[59] = 59,
-    .interrupt_lines[60] = 60,
-    .interrupt_lines[61] = 61,
-    .interrupt_lines[62] = 62,
-    .interrupt_lines[63] = 63,
-    .interrupt_lines[64] = 64,
-    .interrupt_lines[65] = 65,
-    .interrupt_lines[66] = 66,
-    .interrupt_lines[67] = 67,
-    .interrupt_lines[68] = 68,
-    .interrupt_lines[69] = 69,
-    .interrupt_lines[70] = 70,
-    .interrupt_lines[71] = 71,
-    .interrupt_lines[72] = 72,
-    .interrupt_lines[73] = 73,
-    .interrupt_lines[74] = 74,
-    .interrupt_lines[75] = 75,
-    .interrupt_lines[76] = 76,
-    .interrupt_lines[77] = 77,
-    .interrupt_lines[78] = 78,
-    .interrupt_lines[79] = 79,
-    .interrupt_lines[80] = 80,
-    .interrupt_lines[81] = 81,
-    .interrupt_lines[82] = 82,
-    .interrupt_lines[83] = 83,
-    .interrupt_lines[84] = 84,
-    .interrupt_lines[85] = 85,
-    .interrupt_lines[86] = 86,
-    .interrupt_lines[87] = 87,
-    .interrupt_lines[88] = 88,
-    .interrupt_lines[89] = 89,
-    .interrupt_lines[90] = 90,
-    .interrupt_lines[91] = 91,
-    .interrupt_lines[92] = 92,
-    .interrupt_lines[93] = 93,
-    .interrupt_lines[94] = 94,
-    .interrupt_lines[95] = 95,
-    .interrupt_lines[96] = 96,
-    .interrupt_lines[97] = 97,
-    .interrupt_lines[98] = 98,
-    .interrupt_lines[99] = 99,
-    .interrupt_lines[100] = 100,
-    .interrupt_lines[101] = 101,
-    .interrupt_lines[102] = 102,
-    .interrupt_lines[103] = 103,
-    .interrupt_lines[104] = 104,
-    .interrupt_lines[105] = 105,
-    .interrupt_lines[106] = 106,
-    .interrupt_lines[107] = 107,
-    .interrupt_lines[108] = 108,
-    .interrupt_lines[109] = 109,
-    .interrupt_lines[110] = 110,
-    .interrupt_lines[111] = 111,
-    .interrupt_lines[112] = 112,
-    .interrupt_lines[113] = 113,
-    .interrupt_lines[114] = 114,
-    .interrupt_lines[115] = 115,
-    .interrupt_lines[116] = 116,
-    .interrupt_lines[117] = 117,
-    .interrupt_lines[118] = 118,
-    .interrupt_lines[119] = 119,
-    .interrupt_lines[120] = 120,
-    .interrupt_lines[121] = 121,
-    .interrupt_lines[122] = 122,
-    .interrupt_lines[123] = 123,
-    .interrupt_lines[124] = 124,
-    .interrupt_lines[125] = 125,
-    .interrupt_lines[126] = 126,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -365,7 +737,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E21_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E21_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e21-rtl/metal.ramrodata.lds b/bsp/coreip-e21-rtl/metal.ramrodata.lds
index b8f126d..199cc1f 100644
--- a/bsp/coreip-e21-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e21-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -165,18 +171,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e21-rtl/metal.scratchpad.lds b/bsp/coreip-e21-rtl/metal.scratchpad.lds
index 44ced9a..8bea50d 100644
--- a/bsp/coreip-e21-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e21-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk
index f60f250..bb8d89a 100644
--- a/bsp/coreip-e21-rtl/settings.mk
+++ b/bsp/coreip-e21-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e24-arty/metal-inline.h b/bsp/coreip-e24-arty/metal-inline.h
new file mode 100644
index 0000000..bbe456e
--- /dev/null
+++ b/bsp/coreip-e24-arty/metal-inline.h
@@ -0,0 +1,276 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E24_ARTY__METAL_INLINE_H
+#define COREIP_E24_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller);
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
+    ._base_address = 2147516416UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From interrupt_controller@2000000 */
+struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_E24_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e24-arty/metal-platform.h b/bsp/coreip-e24-arty/metal-platform.h
index c87c0f5..1a3bd88 100644
--- a/bsp/coreip-e24-arty/metal-platform.h
+++ b/bsp/coreip-e24-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E24_ARTY__METAL_PLATFORM_H
 #define COREIP_E24_ARTY__METAL_PLATFORM_H
 
@@ -13,10 +19,15 @@
 
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_0_SIZE 16777216UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 153UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTS 153UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMLEVELS 16UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 4UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTBITS 4UL
 
 #define METAL_SIFIVE_CLIC0
 #define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
@@ -31,9 +42,15 @@
 #define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
 #define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -54,9 +71,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -78,14 +144,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-e24-arty/metal.default.lds b/bsp/coreip-e24-arty/metal.default.lds
index 3358fbe..0b7a37a 100644
--- a/bsp/coreip-e24-arty/metal.default.lds
+++ b/bsp/coreip-e24-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h
index 44bb118..772ac57 100644
--- a/bsp/coreip-e24-arty/metal.h
+++ b/bsp/coreip-e24-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E24_ARTY__METAL_H
-#define COREIP_E24_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E24_ARTY__METAL_H
+#define MACROS_IF_COREIP_E24_ARTY__METAL_H
+
 #ifndef __METAL_CLINT_NUM_PARENTS
 #define __METAL_CLINT_NUM_PARENTS 0
 #endif
@@ -22,8 +28,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E24_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E24_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_E24_ARTY__METAL_H
+
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
 #define __METAL_CLINT_NUM_PARENTS 0
@@ -72,520 +83,1126 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_sys_sram_0_80000000");
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000;
 
-asm (".weak __metal_dt_mem_sys_sram_1_80008000");
 struct metal_memory __metal_dt_mem_sys_sram_1_80008000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From interrupt_controller@2000000 */
-asm (".weak __metal_dt_interrupt_controller_2000000");
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
-    ._base_address = 2147516416UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 32000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 32000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+static inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_MAX_CLIC_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 3;
+	}
+	else if (idx == 2) {
+		return 7;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 26;
+	}
+	else if (idx == 1) {
+		return 27;
+	}
+	else if (idx == 2) {
+		return 28;
+	}
+	else if (idx == 3) {
+		return 29;
+	}
+	else if (idx == 4) {
+		return 30;
+	}
+	else if (idx == 5) {
+		return 31;
+	}
+	else if (idx == 6) {
+		return 32;
+	}
+	else if (idx == 7) {
+		return 33;
+	}
+	else if (idx == 8) {
+		return 34;
+	}
+	else if (idx == 9) {
+		return 35;
+	}
+	else if (idx == 10) {
+		return 36;
+	}
+	else if (idx == 11) {
+		return 37;
+	}
+	else if (idx == 12) {
+		return 38;
+	}
+	else if (idx == 13) {
+		return 39;
+	}
+	else if (idx == 14) {
+		return 40;
+	}
+	else if (idx == 15) {
+		return 41;
+	}
+	else if (idx == 16) {
+		return 42;
+	}
+	else if (idx == 17) {
+		return 43;
+	}
+	else if (idx == 18) {
+		return 44;
+	}
+	else if (idx == 19) {
+		return 45;
+	}
+	else if (idx == 20) {
+		return 46;
+	}
+	else if (idx == 21) {
+		return 47;
+	}
+	else if (idx == 22) {
+		return 48;
+	}
+	else if (idx == 23) {
+		return 49;
+	}
+	else if (idx == 24) {
+		return 50;
+	}
+	else if (idx == 25) {
+		return 51;
+	}
+	else if (idx == 26) {
+		return 52;
+	}
+	else if (idx == 27) {
+		return 53;
+	}
+	else if (idx == 28) {
+		return 54;
+	}
+	else if (idx == 29) {
+		return 55;
+	}
+	else if (idx == 30) {
+		return 56;
+	}
+	else if (idx == 31) {
+		return 57;
+	}
+	else if (idx == 32) {
+		return 58;
+	}
+	else if (idx == 33) {
+		return 59;
+	}
+	else if (idx == 34) {
+		return 60;
+	}
+	else if (idx == 35) {
+		return 61;
+	}
+	else if (idx == 36) {
+		return 62;
+	}
+	else if (idx == 37) {
+		return 63;
+	}
+	else if (idx == 38) {
+		return 64;
+	}
+	else if (idx == 39) {
+		return 65;
+	}
+	else if (idx == 40) {
+		return 66;
+	}
+	else if (idx == 41) {
+		return 67;
+	}
+	else if (idx == 42) {
+		return 68;
+	}
+	else if (idx == 43) {
+		return 69;
+	}
+	else if (idx == 44) {
+		return 70;
+	}
+	else if (idx == 45) {
+		return 71;
+	}
+	else if (idx == 46) {
+		return 72;
+	}
+	else if (idx == 47) {
+		return 73;
+	}
+	else if (idx == 48) {
+		return 74;
+	}
+	else if (idx == 49) {
+		return 75;
+	}
+	else if (idx == 50) {
+		return 76;
+	}
+	else if (idx == 51) {
+		return 77;
+	}
+	else if (idx == 52) {
+		return 78;
+	}
+	else if (idx == 53) {
+		return 79;
+	}
+	else if (idx == 54) {
+		return 80;
+	}
+	else if (idx == 55) {
+		return 81;
+	}
+	else if (idx == 56) {
+		return 82;
+	}
+	else if (idx == 57) {
+		return 83;
+	}
+	else if (idx == 58) {
+		return 84;
+	}
+	else if (idx == 59) {
+		return 85;
+	}
+	else if (idx == 60) {
+		return 86;
+	}
+	else if (idx == 61) {
+		return 87;
+	}
+	else if (idx == 62) {
+		return 88;
+	}
+	else if (idx == 63) {
+		return 89;
+	}
+	else if (idx == 64) {
+		return 90;
+	}
+	else if (idx == 65) {
+		return 91;
+	}
+	else if (idx == 66) {
+		return 92;
+	}
+	else if (idx == 67) {
+		return 93;
+	}
+	else if (idx == 68) {
+		return 94;
+	}
+	else if (idx == 69) {
+		return 95;
+	}
+	else if (idx == 70) {
+		return 96;
+	}
+	else if (idx == 71) {
+		return 97;
+	}
+	else if (idx == 72) {
+		return 98;
+	}
+	else if (idx == 73) {
+		return 99;
+	}
+	else if (idx == 74) {
+		return 100;
+	}
+	else if (idx == 75) {
+		return 101;
+	}
+	else if (idx == 76) {
+		return 102;
+	}
+	else if (idx == 77) {
+		return 103;
+	}
+	else if (idx == 78) {
+		return 104;
+	}
+	else if (idx == 79) {
+		return 105;
+	}
+	else if (idx == 80) {
+		return 106;
+	}
+	else if (idx == 81) {
+		return 107;
+	}
+	else if (idx == 82) {
+		return 108;
+	}
+	else if (idx == 83) {
+		return 109;
+	}
+	else if (idx == 84) {
+		return 110;
+	}
+	else if (idx == 85) {
+		return 111;
+	}
+	else if (idx == 86) {
+		return 112;
+	}
+	else if (idx == 87) {
+		return 113;
+	}
+	else if (idx == 88) {
+		return 114;
+	}
+	else if (idx == 89) {
+		return 115;
+	}
+	else if (idx == 90) {
+		return 116;
+	}
+	else if (idx == 91) {
+		return 117;
+	}
+	else if (idx == 92) {
+		return 118;
+	}
+	else if (idx == 93) {
+		return 119;
+	}
+	else if (idx == 94) {
+		return 120;
+	}
+	else if (idx == 95) {
+		return 121;
+	}
+	else if (idx == 96) {
+		return 122;
+	}
+	else if (idx == 97) {
+		return 123;
+	}
+	else if (idx == 98) {
+		return 124;
+	}
+	else if (idx == 99) {
+		return 125;
+	}
+	else if (idx == 100) {
+		return 126;
+	}
+	else if (idx == 101) {
+		return 127;
+	}
+	else if (idx == 102) {
+		return 128;
+	}
+	else if (idx == 103) {
+		return 129;
+	}
+	else if (idx == 104) {
+		return 130;
+	}
+	else if (idx == 105) {
+		return 131;
+	}
+	else if (idx == 106) {
+		return 132;
+	}
+	else if (idx == 107) {
+		return 133;
+	}
+	else if (idx == 108) {
+		return 134;
+	}
+	else if (idx == 109) {
+		return 135;
+	}
+	else if (idx == 110) {
+		return 136;
+	}
+	else if (idx == 111) {
+		return 137;
+	}
+	else if (idx == 112) {
+		return 138;
+	}
+	else if (idx == 113) {
+		return 139;
+	}
+	else if (idx == 114) {
+		return 140;
+	}
+	else if (idx == 115) {
+		return 141;
+	}
+	else if (idx == 116) {
+		return 142;
+	}
+	else if (idx == 117) {
+		return 143;
+	}
+	else if (idx == 118) {
+		return 144;
+	}
+	else if (idx == 119) {
+		return 145;
+	}
+	else if (idx == 120) {
+		return 146;
+	}
+	else if (idx == 121) {
+		return 147;
+	}
+	else if (idx == 122) {
+		return 148;
+	}
+	else if (idx == 123) {
+		return 149;
+	}
+	else if (idx == 124) {
+		return 150;
+	}
+	else if (idx == 125) {
+		return 151;
+	}
+	else if (idx == 126) {
+		return 152;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 22;
+	}
+	else if (idx == 1) {
+		return 23;
+	}
+	else if (idx == 2) {
+		return 24;
+	}
+	else if (idx == 3) {
+		return 25;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 0;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 15;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 20;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 21;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 22;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 23;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 16;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 17;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 18;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 19;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 16;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From interrupt_controller@2000000 */
-struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
-    .vtable = &__metal_driver_vtable_sifive_clic0,
-    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_lines[1] = 7,
-    .interrupt_lines[2] = 11,
-    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
-    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
-    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
-    .interrupt_controller = 1,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 26,
-    .interrupt_lines[1] = 27,
-    .interrupt_lines[2] = 28,
-    .interrupt_lines[3] = 29,
-    .interrupt_lines[4] = 30,
-    .interrupt_lines[5] = 31,
-    .interrupt_lines[6] = 32,
-    .interrupt_lines[7] = 33,
-    .interrupt_lines[8] = 34,
-    .interrupt_lines[9] = 35,
-    .interrupt_lines[10] = 36,
-    .interrupt_lines[11] = 37,
-    .interrupt_lines[12] = 38,
-    .interrupt_lines[13] = 39,
-    .interrupt_lines[14] = 40,
-    .interrupt_lines[15] = 41,
-    .interrupt_lines[16] = 42,
-    .interrupt_lines[17] = 43,
-    .interrupt_lines[18] = 44,
-    .interrupt_lines[19] = 45,
-    .interrupt_lines[20] = 46,
-    .interrupt_lines[21] = 47,
-    .interrupt_lines[22] = 48,
-    .interrupt_lines[23] = 49,
-    .interrupt_lines[24] = 50,
-    .interrupt_lines[25] = 51,
-    .interrupt_lines[26] = 52,
-    .interrupt_lines[27] = 53,
-    .interrupt_lines[28] = 54,
-    .interrupt_lines[29] = 55,
-    .interrupt_lines[30] = 56,
-    .interrupt_lines[31] = 57,
-    .interrupt_lines[32] = 58,
-    .interrupt_lines[33] = 59,
-    .interrupt_lines[34] = 60,
-    .interrupt_lines[35] = 61,
-    .interrupt_lines[36] = 62,
-    .interrupt_lines[37] = 63,
-    .interrupt_lines[38] = 64,
-    .interrupt_lines[39] = 65,
-    .interrupt_lines[40] = 66,
-    .interrupt_lines[41] = 67,
-    .interrupt_lines[42] = 68,
-    .interrupt_lines[43] = 69,
-    .interrupt_lines[44] = 70,
-    .interrupt_lines[45] = 71,
-    .interrupt_lines[46] = 72,
-    .interrupt_lines[47] = 73,
-    .interrupt_lines[48] = 74,
-    .interrupt_lines[49] = 75,
-    .interrupt_lines[50] = 76,
-    .interrupt_lines[51] = 77,
-    .interrupt_lines[52] = 78,
-    .interrupt_lines[53] = 79,
-    .interrupt_lines[54] = 80,
-    .interrupt_lines[55] = 81,
-    .interrupt_lines[56] = 82,
-    .interrupt_lines[57] = 83,
-    .interrupt_lines[58] = 84,
-    .interrupt_lines[59] = 85,
-    .interrupt_lines[60] = 86,
-    .interrupt_lines[61] = 87,
-    .interrupt_lines[62] = 88,
-    .interrupt_lines[63] = 89,
-    .interrupt_lines[64] = 90,
-    .interrupt_lines[65] = 91,
-    .interrupt_lines[66] = 92,
-    .interrupt_lines[67] = 93,
-    .interrupt_lines[68] = 94,
-    .interrupt_lines[69] = 95,
-    .interrupt_lines[70] = 96,
-    .interrupt_lines[71] = 97,
-    .interrupt_lines[72] = 98,
-    .interrupt_lines[73] = 99,
-    .interrupt_lines[74] = 100,
-    .interrupt_lines[75] = 101,
-    .interrupt_lines[76] = 102,
-    .interrupt_lines[77] = 103,
-    .interrupt_lines[78] = 104,
-    .interrupt_lines[79] = 105,
-    .interrupt_lines[80] = 106,
-    .interrupt_lines[81] = 107,
-    .interrupt_lines[82] = 108,
-    .interrupt_lines[83] = 109,
-    .interrupt_lines[84] = 110,
-    .interrupt_lines[85] = 111,
-    .interrupt_lines[86] = 112,
-    .interrupt_lines[87] = 113,
-    .interrupt_lines[88] = 114,
-    .interrupt_lines[89] = 115,
-    .interrupt_lines[90] = 116,
-    .interrupt_lines[91] = 117,
-    .interrupt_lines[92] = 118,
-    .interrupt_lines[93] = 119,
-    .interrupt_lines[94] = 120,
-    .interrupt_lines[95] = 121,
-    .interrupt_lines[96] = 122,
-    .interrupt_lines[97] = 123,
-    .interrupt_lines[98] = 124,
-    .interrupt_lines[99] = 125,
-    .interrupt_lines[100] = 126,
-    .interrupt_lines[101] = 127,
-    .interrupt_lines[102] = 128,
-    .interrupt_lines[103] = 129,
-    .interrupt_lines[104] = 130,
-    .interrupt_lines[105] = 131,
-    .interrupt_lines[106] = 132,
-    .interrupt_lines[107] = 133,
-    .interrupt_lines[108] = 134,
-    .interrupt_lines[109] = 135,
-    .interrupt_lines[110] = 136,
-    .interrupt_lines[111] = 137,
-    .interrupt_lines[112] = 138,
-    .interrupt_lines[113] = 139,
-    .interrupt_lines[114] = 140,
-    .interrupt_lines[115] = 141,
-    .interrupt_lines[116] = 142,
-    .interrupt_lines[117] = 143,
-    .interrupt_lines[118] = 144,
-    .interrupt_lines[119] = 145,
-    .interrupt_lines[120] = 146,
-    .interrupt_lines[121] = 147,
-    .interrupt_lines[122] = 148,
-    .interrupt_lines[123] = 149,
-    .interrupt_lines[124] = 150,
-    .interrupt_lines[125] = 151,
-    .interrupt_lines[126] = 152,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 22,
-    .interrupt_lines[1] = 23,
-    .interrupt_lines[2] = 24,
-    .interrupt_lines[3] = 25,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 0,
-    .interrupt_lines[1] = 1,
-    .interrupt_lines[2] = 2,
-    .interrupt_lines[3] = 3,
-    .interrupt_lines[4] = 4,
-    .interrupt_lines[5] = 5,
-    .interrupt_lines[6] = 6,
-    .interrupt_lines[7] = 7,
-    .interrupt_lines[8] = 8,
-    .interrupt_lines[9] = 9,
-    .interrupt_lines[10] = 10,
-    .interrupt_lines[11] = 11,
-    .interrupt_lines[12] = 12,
-    .interrupt_lines[13] = 13,
-    .interrupt_lines[14] = 14,
-    .interrupt_lines[15] = 15,
-};
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 20UL,
-    .label = "BTN0",
-};
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 21UL,
-    .label = "BTN1",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 22UL,
-    .label = "BTN2",
-};
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 23UL,
-    .label = "BTN3",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 16UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 17UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 18UL,
-    .label = "SW2",
-};
-
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 19UL,
-    .label = "SW3",
-};
-
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
-
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
-
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 16UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -670,7 +1287,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E24_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E24_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e24-arty/metal.ramrodata.lds b/bsp/coreip-e24-arty/metal.ramrodata.lds
index 90b3388..e1e793f 100644
--- a/bsp/coreip-e24-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e24-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -165,18 +171,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e24-arty/metal.scratchpad.lds b/bsp/coreip-e24-arty/metal.scratchpad.lds
index 01ee127..e986066 100644
--- a/bsp/coreip-e24-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e24-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk
index 62d3775..115db75 100644
--- a/bsp/coreip-e24-arty/settings.mk
+++ b/bsp/coreip-e24-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e24-rtl/metal-inline.h b/bsp/coreip-e24-rtl/metal-inline.h
new file mode 100644
index 0000000..dd34d93
--- /dev/null
+++ b/bsp/coreip-e24-rtl/metal-inline.h
@@ -0,0 +1,158 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E24_RTL__METAL_INLINE_H
+#define COREIP_E24_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller);
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
+    ._base_address = 2147516416UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 134217728UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From interrupt_controller@2000000 */
+struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_E24_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e24-rtl/metal-platform.h b/bsp/coreip-e24-rtl/metal-platform.h
index c83d491..dabc75f 100644
--- a/bsp/coreip-e24-rtl/metal-platform.h
+++ b/bsp/coreip-e24-rtl/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E24_RTL__METAL_PLATFORM_H
 #define COREIP_E24_RTL__METAL_PLATFORM_H
 
@@ -8,10 +14,15 @@
 
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_0_SIZE 16777216UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 143UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTS 143UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMLEVELS 16UL
 #define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 4UL
+#define METAL_SIFIVE_CLIC0_0_SIFIVE_NUMINTBITS 4UL
 
 #define METAL_SIFIVE_CLIC0
 #define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
@@ -26,9 +37,15 @@
 #define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
 #define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
 
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-e24-rtl/metal.default.lds b/bsp/coreip-e24-rtl/metal.default.lds
index a3c999a..d021e81 100644
--- a/bsp/coreip-e24-rtl/metal.default.lds
+++ b/bsp/coreip-e24-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h
index 5c8776b..6d97dbd 100644
--- a/bsp/coreip-e24-rtl/metal.h
+++ b/bsp/coreip-e24-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E24_RTL__METAL_H
-#define COREIP_E24_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E24_RTL__METAL_H
+#define MACROS_IF_COREIP_E24_RTL__METAL_H
+
 #ifndef __METAL_CLINT_NUM_PARENTS
 #define __METAL_CLINT_NUM_PARENTS 0
 #endif
@@ -22,8 +28,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E24_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E24_RTL__METAL_H
+#define MACROS_ELSE_COREIP_E24_RTL__METAL_H
+
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
 #define __METAL_CLINT_NUM_PARENTS 0
@@ -58,254 +69,615 @@
 #include <metal/drivers/sifive,local-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_sys_sram_0_80000000");
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000;
 
-asm (".weak __metal_dt_mem_sys_sram_1_80008000");
 struct metal_memory __metal_dt_mem_sys_sram_1_80008000;
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From interrupt_controller@2000000 */
-asm (".weak __metal_dt_interrupt_controller_2000000");
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
-    ._base_address = 2147516416UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 134217728UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+
+
+/* --------------------- sifive_clic0 ------------ */
+static inline unsigned long __metal_driver_sifive_clic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_MAX_CLIC_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clic0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 3;
+	}
+	else if (idx == 2) {
+		return 7;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_max_levels(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_subinterrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clic0_num_intbits(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_2000000) {
+		return METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_2000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 0;
+	}
+	else if (idx == 1) {
+		return 1;
+	}
+	else if (idx == 2) {
+		return 2;
+	}
+	else if (idx == 3) {
+		return 3;
+	}
+	else if (idx == 4) {
+		return 4;
+	}
+	else if (idx == 5) {
+		return 5;
+	}
+	else if (idx == 6) {
+		return 6;
+	}
+	else if (idx == 7) {
+		return 7;
+	}
+	else if (idx == 8) {
+		return 8;
+	}
+	else if (idx == 9) {
+		return 9;
+	}
+	else if (idx == 10) {
+		return 10;
+	}
+	else if (idx == 11) {
+		return 11;
+	}
+	else if (idx == 12) {
+		return 12;
+	}
+	else if (idx == 13) {
+		return 13;
+	}
+	else if (idx == 14) {
+		return 14;
+	}
+	else if (idx == 15) {
+		return 15;
+	}
+	else if (idx == 16) {
+		return 16;
+	}
+	else if (idx == 17) {
+		return 17;
+	}
+	else if (idx == 18) {
+		return 18;
+	}
+	else if (idx == 19) {
+		return 19;
+	}
+	else if (idx == 20) {
+		return 20;
+	}
+	else if (idx == 21) {
+		return 21;
+	}
+	else if (idx == 22) {
+		return 22;
+	}
+	else if (idx == 23) {
+		return 23;
+	}
+	else if (idx == 24) {
+		return 24;
+	}
+	else if (idx == 25) {
+		return 25;
+	}
+	else if (idx == 26) {
+		return 26;
+	}
+	else if (idx == 27) {
+		return 27;
+	}
+	else if (idx == 28) {
+		return 28;
+	}
+	else if (idx == 29) {
+		return 29;
+	}
+	else if (idx == 30) {
+		return 30;
+	}
+	else if (idx == 31) {
+		return 31;
+	}
+	else if (idx == 32) {
+		return 32;
+	}
+	else if (idx == 33) {
+		return 33;
+	}
+	else if (idx == 34) {
+		return 34;
+	}
+	else if (idx == 35) {
+		return 35;
+	}
+	else if (idx == 36) {
+		return 36;
+	}
+	else if (idx == 37) {
+		return 37;
+	}
+	else if (idx == 38) {
+		return 38;
+	}
+	else if (idx == 39) {
+		return 39;
+	}
+	else if (idx == 40) {
+		return 40;
+	}
+	else if (idx == 41) {
+		return 41;
+	}
+	else if (idx == 42) {
+		return 42;
+	}
+	else if (idx == 43) {
+		return 43;
+	}
+	else if (idx == 44) {
+		return 44;
+	}
+	else if (idx == 45) {
+		return 45;
+	}
+	else if (idx == 46) {
+		return 46;
+	}
+	else if (idx == 47) {
+		return 47;
+	}
+	else if (idx == 48) {
+		return 48;
+	}
+	else if (idx == 49) {
+		return 49;
+	}
+	else if (idx == 50) {
+		return 50;
+	}
+	else if (idx == 51) {
+		return 51;
+	}
+	else if (idx == 52) {
+		return 52;
+	}
+	else if (idx == 53) {
+		return 53;
+	}
+	else if (idx == 54) {
+		return 54;
+	}
+	else if (idx == 55) {
+		return 55;
+	}
+	else if (idx == 56) {
+		return 56;
+	}
+	else if (idx == 57) {
+		return 57;
+	}
+	else if (idx == 58) {
+		return 58;
+	}
+	else if (idx == 59) {
+		return 59;
+	}
+	else if (idx == 60) {
+		return 60;
+	}
+	else if (idx == 61) {
+		return 61;
+	}
+	else if (idx == 62) {
+		return 62;
+	}
+	else if (idx == 63) {
+		return 63;
+	}
+	else if (idx == 64) {
+		return 64;
+	}
+	else if (idx == 65) {
+		return 65;
+	}
+	else if (idx == 66) {
+		return 66;
+	}
+	else if (idx == 67) {
+		return 67;
+	}
+	else if (idx == 68) {
+		return 68;
+	}
+	else if (idx == 69) {
+		return 69;
+	}
+	else if (idx == 70) {
+		return 70;
+	}
+	else if (idx == 71) {
+		return 71;
+	}
+	else if (idx == 72) {
+		return 72;
+	}
+	else if (idx == 73) {
+		return 73;
+	}
+	else if (idx == 74) {
+		return 74;
+	}
+	else if (idx == 75) {
+		return 75;
+	}
+	else if (idx == 76) {
+		return 76;
+	}
+	else if (idx == 77) {
+		return 77;
+	}
+	else if (idx == 78) {
+		return 78;
+	}
+	else if (idx == 79) {
+		return 79;
+	}
+	else if (idx == 80) {
+		return 80;
+	}
+	else if (idx == 81) {
+		return 81;
+	}
+	else if (idx == 82) {
+		return 82;
+	}
+	else if (idx == 83) {
+		return 83;
+	}
+	else if (idx == 84) {
+		return 84;
+	}
+	else if (idx == 85) {
+		return 85;
+	}
+	else if (idx == 86) {
+		return 86;
+	}
+	else if (idx == 87) {
+		return 87;
+	}
+	else if (idx == 88) {
+		return 88;
+	}
+	else if (idx == 89) {
+		return 89;
+	}
+	else if (idx == 90) {
+		return 90;
+	}
+	else if (idx == 91) {
+		return 91;
+	}
+	else if (idx == 92) {
+		return 92;
+	}
+	else if (idx == 93) {
+		return 93;
+	}
+	else if (idx == 94) {
+		return 94;
+	}
+	else if (idx == 95) {
+		return 95;
+	}
+	else if (idx == 96) {
+		return 96;
+	}
+	else if (idx == 97) {
+		return 97;
+	}
+	else if (idx == 98) {
+		return 98;
+	}
+	else if (idx == 99) {
+		return 99;
+	}
+	else if (idx == 100) {
+		return 100;
+	}
+	else if (idx == 101) {
+		return 101;
+	}
+	else if (idx == 102) {
+		return 102;
+	}
+	else if (idx == 103) {
+		return 103;
+	}
+	else if (idx == 104) {
+		return 104;
+	}
+	else if (idx == 105) {
+		return 105;
+	}
+	else if (idx == 106) {
+		return 106;
+	}
+	else if (idx == 107) {
+		return 107;
+	}
+	else if (idx == 108) {
+		return 108;
+	}
+	else if (idx == 109) {
+		return 109;
+	}
+	else if (idx == 110) {
+		return 110;
+	}
+	else if (idx == 111) {
+		return 111;
+	}
+	else if (idx == 112) {
+		return 112;
+	}
+	else if (idx == 113) {
+		return 113;
+	}
+	else if (idx == 114) {
+		return 114;
+	}
+	else if (idx == 115) {
+		return 115;
+	}
+	else if (idx == 116) {
+		return 116;
+	}
+	else if (idx == 117) {
+		return 117;
+	}
+	else if (idx == 118) {
+		return 118;
+	}
+	else if (idx == 119) {
+		return 119;
+	}
+	else if (idx == 120) {
+		return 120;
+	}
+	else if (idx == 121) {
+		return 121;
+	}
+	else if (idx == 122) {
+		return 122;
+	}
+	else if (idx == 123) {
+		return 123;
+	}
+	else if (idx == 124) {
+		return 124;
+	}
+	else if (idx == 125) {
+		return 125;
+	}
+	else if (idx == 126) {
+		return 126;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
 
-/* From interrupt_controller@2000000 */
-struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
-    .vtable = &__metal_driver_vtable_sifive_clic0,
-    .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_lines[1] = 7,
-    .interrupt_lines[2] = 11,
-    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
-    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
-    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
-    .interrupt_controller = 1,
-};
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@2000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 0,
-    .interrupt_lines[1] = 1,
-    .interrupt_lines[2] = 2,
-    .interrupt_lines[3] = 3,
-    .interrupt_lines[4] = 4,
-    .interrupt_lines[5] = 5,
-    .interrupt_lines[6] = 6,
-    .interrupt_lines[7] = 7,
-    .interrupt_lines[8] = 8,
-    .interrupt_lines[9] = 9,
-    .interrupt_lines[10] = 10,
-    .interrupt_lines[11] = 11,
-    .interrupt_lines[12] = 12,
-    .interrupt_lines[13] = 13,
-    .interrupt_lines[14] = 14,
-    .interrupt_lines[15] = 15,
-    .interrupt_lines[16] = 16,
-    .interrupt_lines[17] = 17,
-    .interrupt_lines[18] = 18,
-    .interrupt_lines[19] = 19,
-    .interrupt_lines[20] = 20,
-    .interrupt_lines[21] = 21,
-    .interrupt_lines[22] = 22,
-    .interrupt_lines[23] = 23,
-    .interrupt_lines[24] = 24,
-    .interrupt_lines[25] = 25,
-    .interrupt_lines[26] = 26,
-    .interrupt_lines[27] = 27,
-    .interrupt_lines[28] = 28,
-    .interrupt_lines[29] = 29,
-    .interrupt_lines[30] = 30,
-    .interrupt_lines[31] = 31,
-    .interrupt_lines[32] = 32,
-    .interrupt_lines[33] = 33,
-    .interrupt_lines[34] = 34,
-    .interrupt_lines[35] = 35,
-    .interrupt_lines[36] = 36,
-    .interrupt_lines[37] = 37,
-    .interrupt_lines[38] = 38,
-    .interrupt_lines[39] = 39,
-    .interrupt_lines[40] = 40,
-    .interrupt_lines[41] = 41,
-    .interrupt_lines[42] = 42,
-    .interrupt_lines[43] = 43,
-    .interrupt_lines[44] = 44,
-    .interrupt_lines[45] = 45,
-    .interrupt_lines[46] = 46,
-    .interrupt_lines[47] = 47,
-    .interrupt_lines[48] = 48,
-    .interrupt_lines[49] = 49,
-    .interrupt_lines[50] = 50,
-    .interrupt_lines[51] = 51,
-    .interrupt_lines[52] = 52,
-    .interrupt_lines[53] = 53,
-    .interrupt_lines[54] = 54,
-    .interrupt_lines[55] = 55,
-    .interrupt_lines[56] = 56,
-    .interrupt_lines[57] = 57,
-    .interrupt_lines[58] = 58,
-    .interrupt_lines[59] = 59,
-    .interrupt_lines[60] = 60,
-    .interrupt_lines[61] = 61,
-    .interrupt_lines[62] = 62,
-    .interrupt_lines[63] = 63,
-    .interrupt_lines[64] = 64,
-    .interrupt_lines[65] = 65,
-    .interrupt_lines[66] = 66,
-    .interrupt_lines[67] = 67,
-    .interrupt_lines[68] = 68,
-    .interrupt_lines[69] = 69,
-    .interrupt_lines[70] = 70,
-    .interrupt_lines[71] = 71,
-    .interrupt_lines[72] = 72,
-    .interrupt_lines[73] = 73,
-    .interrupt_lines[74] = 74,
-    .interrupt_lines[75] = 75,
-    .interrupt_lines[76] = 76,
-    .interrupt_lines[77] = 77,
-    .interrupt_lines[78] = 78,
-    .interrupt_lines[79] = 79,
-    .interrupt_lines[80] = 80,
-    .interrupt_lines[81] = 81,
-    .interrupt_lines[82] = 82,
-    .interrupt_lines[83] = 83,
-    .interrupt_lines[84] = 84,
-    .interrupt_lines[85] = 85,
-    .interrupt_lines[86] = 86,
-    .interrupt_lines[87] = 87,
-    .interrupt_lines[88] = 88,
-    .interrupt_lines[89] = 89,
-    .interrupt_lines[90] = 90,
-    .interrupt_lines[91] = 91,
-    .interrupt_lines[92] = 92,
-    .interrupt_lines[93] = 93,
-    .interrupt_lines[94] = 94,
-    .interrupt_lines[95] = 95,
-    .interrupt_lines[96] = 96,
-    .interrupt_lines[97] = 97,
-    .interrupt_lines[98] = 98,
-    .interrupt_lines[99] = 99,
-    .interrupt_lines[100] = 100,
-    .interrupt_lines[101] = 101,
-    .interrupt_lines[102] = 102,
-    .interrupt_lines[103] = 103,
-    .interrupt_lines[104] = 104,
-    .interrupt_lines[105] = 105,
-    .interrupt_lines[106] = 106,
-    .interrupt_lines[107] = 107,
-    .interrupt_lines[108] = 108,
-    .interrupt_lines[109] = 109,
-    .interrupt_lines[110] = 110,
-    .interrupt_lines[111] = 111,
-    .interrupt_lines[112] = 112,
-    .interrupt_lines[113] = 113,
-    .interrupt_lines[114] = 114,
-    .interrupt_lines[115] = 115,
-    .interrupt_lines[116] = 116,
-    .interrupt_lines[117] = 117,
-    .interrupt_lines[118] = 118,
-    .interrupt_lines[119] = 119,
-    .interrupt_lines[120] = 120,
-    .interrupt_lines[121] = 121,
-    .interrupt_lines[122] = 122,
-    .interrupt_lines[123] = 123,
-    .interrupt_lines[124] = 124,
-    .interrupt_lines[125] = 125,
-    .interrupt_lines[126] = 126,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -365,7 +737,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E24_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E24_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e24-rtl/metal.ramrodata.lds b/bsp/coreip-e24-rtl/metal.ramrodata.lds
index b8f126d..199cc1f 100644
--- a/bsp/coreip-e24-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e24-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -165,18 +171,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e24-rtl/metal.scratchpad.lds b/bsp/coreip-e24-rtl/metal.scratchpad.lds
index 44ced9a..8bea50d 100644
--- a/bsp/coreip-e24-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e24-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk
index 880c000..4d6b13e 100644
--- a/bsp/coreip-e24-rtl/settings.mk
+++ b/bsp/coreip-e24-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e31-arty/metal-inline.h b/bsp/coreip-e31-arty/metal-inline.h
new file mode 100644
index 0000000..fe89e39
--- /dev/null
+++ b/bsp/coreip-e31-arty/metal-inline.h
@@ -0,0 +1,285 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E31_ARTY__METAL_INLINE_H
+#define COREIP_E31_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_E31_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e31-arty/metal-inline1.h b/bsp/coreip-e31-arty/metal-inline1.h
new file mode 100644
index 0000000..7cd8b1f
--- /dev/null
+++ b/bsp/coreip-e31-arty/metal-inline1.h
@@ -0,0 +1,44 @@
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E31_ARTY1_INLINE_H
+#define COREIP_E31_ARTY1_INLINE_H
+
+#include <metal/machine.h>
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+#endif /* COREIP_E31_ARTY1_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e31-arty/metal-platform.h b/bsp/coreip-e31-arty/metal-platform.h
index 21689a3..c4c1b37 100644
--- a/bsp/coreip-e31-arty/metal-platform.h
+++ b/bsp/coreip-e31-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E31_ARTY__METAL_PLATFORM_H
 #define COREIP_E31_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -33,9 +45,15 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -56,9 +74,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -80,14 +147,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-e31-arty/metal.default.lds b/bsp/coreip-e31-arty/metal.default.lds
index 87bc213..82a199e 100644
--- a/bsp/coreip-e31-arty/metal.default.lds
+++ b/bsp/coreip-e31-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h
index 10df223..f3a6fb3 100644
--- a/bsp/coreip-e31-arty/metal.h
+++ b/bsp/coreip-e31-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E31_ARTY__METAL_H
-#define COREIP_E31_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E31_ARTY__METAL_H
+#define MACROS_IF_COREIP_E31_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E31_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E31_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_E31_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -79,422 +90,829 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 65000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
-
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 23,
-    .interrupt_lines[1] = 24,
-    .interrupt_lines[2] = 25,
-    .interrupt_lines[3] = 26,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 65000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 23;
+	}
+	else if (idx == 1) {
+		return 24;
+	}
+	else if (idx == 2) {
+		return 25;
+	}
+	else if (idx == 3) {
+		return 26;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 16;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 1;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 2;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 17;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 4UL,
-    .label = "BTN0",
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 5UL,
-    .label = "BTN1",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 6UL,
-    .label = "BTN2",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 7UL,
-    .label = "BTN3",
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 3UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 17UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -584,7 +1002,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E31_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E31_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e31-arty/metal.ramrodata.lds b/bsp/coreip-e31-arty/metal.ramrodata.lds
index 2056624..22eeb0a 100644
--- a/bsp/coreip-e31-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e31-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e31-arty/metal.scratchpad.lds b/bsp/coreip-e31-arty/metal.scratchpad.lds
index fe62b3a..808429b 100644
--- a/bsp/coreip-e31-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e31-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk
index 0b9c2cb..b9be584 100644
--- a/bsp/coreip-e31-arty/settings.mk
+++ b/bsp/coreip-e31-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e31-rtl/metal-inline.h b/bsp/coreip-e31-rtl/metal-inline.h
new file mode 100644
index 0000000..173385b
--- /dev/null
+++ b/bsp/coreip-e31-rtl/metal-inline.h
@@ -0,0 +1,177 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E31_RTL__METAL_INLINE_H
+#define COREIP_E31_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 134217728UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_E31_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e31-rtl/metal-platform.h b/bsp/coreip-e31-rtl/metal-platform.h
index d5bf04d..43c8148 100644
--- a/bsp/coreip-e31-rtl/metal-platform.h
+++ b/bsp/coreip-e31-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E31_RTL__METAL_PLATFORM_H
 #define COREIP_E31_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 128UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,19 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-e31-rtl/metal.default.lds b/bsp/coreip-e31-rtl/metal.default.lds
index 4999528..d4a124f 100644
--- a/bsp/coreip-e31-rtl/metal.default.lds
+++ b/bsp/coreip-e31-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h
index fe465a9..22fc0eb 100644
--- a/bsp/coreip-e31-rtl/metal.h
+++ b/bsp/coreip-e31-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E31_RTL__METAL_H
-#define COREIP_E31_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E31_RTL__METAL_H
+#define MACROS_IF_COREIP_E31_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E31_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E31_RTL__METAL_H
+#define MACROS_ELSE_COREIP_E31_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -68,297 +79,734 @@
 #include <metal/drivers/sifive,global-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 134217728UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -428,7 +876,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E31_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E31_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e31-rtl/metal.ramrodata.lds b/bsp/coreip-e31-rtl/metal.ramrodata.lds
index c8b82a2..6f9d52e 100644
--- a/bsp/coreip-e31-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e31-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e31-rtl/metal.scratchpad.lds b/bsp/coreip-e31-rtl/metal.scratchpad.lds
index f7da1bc..d711300 100644
--- a/bsp/coreip-e31-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e31-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk
index f60f250..bb8d89a 100644
--- a/bsp/coreip-e31-rtl/settings.mk
+++ b/bsp/coreip-e31-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e34-arty/metal-inline.h b/bsp/coreip-e34-arty/metal-inline.h
new file mode 100644
index 0000000..1ba2da5
--- /dev/null
+++ b/bsp/coreip-e34-arty/metal-inline.h
@@ -0,0 +1,285 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E34_ARTY__METAL_INLINE_H
+#define COREIP_E34_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_E34_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e34-arty/metal-platform.h b/bsp/coreip-e34-arty/metal-platform.h
index 76f2494..c2cacc4 100644
--- a/bsp/coreip-e34-arty/metal-platform.h
+++ b/bsp/coreip-e34-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E34_ARTY__METAL_PLATFORM_H
 #define COREIP_E34_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -33,9 +45,15 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -56,9 +74,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -80,14 +147,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-e34-arty/metal.default.lds b/bsp/coreip-e34-arty/metal.default.lds
index 87bc213..82a199e 100644
--- a/bsp/coreip-e34-arty/metal.default.lds
+++ b/bsp/coreip-e34-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h
index c5da8fa..949a75c 100644
--- a/bsp/coreip-e34-arty/metal.h
+++ b/bsp/coreip-e34-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E34_ARTY__METAL_H
-#define COREIP_E34_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E34_ARTY__METAL_H
+#define MACROS_IF_COREIP_E34_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E34_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E34_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_E34_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -79,422 +90,829 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 65000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
-
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 23,
-    .interrupt_lines[1] = 24,
-    .interrupt_lines[2] = 25,
-    .interrupt_lines[3] = 26,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 65000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 23;
+	}
+	else if (idx == 1) {
+		return 24;
+	}
+	else if (idx == 2) {
+		return 25;
+	}
+	else if (idx == 3) {
+		return 26;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 16;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 1;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 2;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 17;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 4UL,
-    .label = "BTN0",
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 5UL,
-    .label = "BTN1",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 6UL,
-    .label = "BTN2",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 7UL,
-    .label = "BTN3",
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 3UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 17UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -584,7 +1002,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E34_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E34_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e34-arty/metal.ramrodata.lds b/bsp/coreip-e34-arty/metal.ramrodata.lds
index 2056624..22eeb0a 100644
--- a/bsp/coreip-e34-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e34-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e34-arty/metal.scratchpad.lds b/bsp/coreip-e34-arty/metal.scratchpad.lds
index fe62b3a..808429b 100644
--- a/bsp/coreip-e34-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e34-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk
index 62d3775..115db75 100644
--- a/bsp/coreip-e34-arty/settings.mk
+++ b/bsp/coreip-e34-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e34-rtl/metal-inline.h b/bsp/coreip-e34-rtl/metal-inline.h
new file mode 100644
index 0000000..6ebb5a0
--- /dev/null
+++ b/bsp/coreip-e34-rtl/metal-inline.h
@@ -0,0 +1,177 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E34_RTL__METAL_INLINE_H
+#define COREIP_E34_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 134217728UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_E34_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e34-rtl/metal-platform.h b/bsp/coreip-e34-rtl/metal-platform.h
index 9b9e13c..8ac399d 100644
--- a/bsp/coreip-e34-rtl/metal-platform.h
+++ b/bsp/coreip-e34-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E34_RTL__METAL_PLATFORM_H
 #define COREIP_E34_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 128UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,19 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-e34-rtl/metal.default.lds b/bsp/coreip-e34-rtl/metal.default.lds
index 4999528..d4a124f 100644
--- a/bsp/coreip-e34-rtl/metal.default.lds
+++ b/bsp/coreip-e34-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h
index 4039765..de80e1b 100644
--- a/bsp/coreip-e34-rtl/metal.h
+++ b/bsp/coreip-e34-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E34_RTL__METAL_H
-#define COREIP_E34_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E34_RTL__METAL_H
+#define MACROS_IF_COREIP_E34_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E34_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E34_RTL__METAL_H
+#define MACROS_ELSE_COREIP_E34_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -68,297 +79,734 @@
 #include <metal/drivers/sifive,global-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 134217728UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -428,7 +876,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E34_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E34_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e34-rtl/metal.ramrodata.lds b/bsp/coreip-e34-rtl/metal.ramrodata.lds
index c8b82a2..6f9d52e 100644
--- a/bsp/coreip-e34-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e34-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e34-rtl/metal.scratchpad.lds b/bsp/coreip-e34-rtl/metal.scratchpad.lds
index f7da1bc..d711300 100644
--- a/bsp/coreip-e34-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e34-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk
index 880c000..4d6b13e 100644
--- a/bsp/coreip-e34-rtl/settings.mk
+++ b/bsp/coreip-e34-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h
new file mode 100644
index 0000000..bd8e58b
--- /dev/null
+++ b/bsp/coreip-e76-arty/metal-inline.h
@@ -0,0 +1,270 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E76_ARTY__METAL_INLINE_H
+#define COREIP_E76_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From tlclk */
+struct __metal_driver_fixed_clock __metal_dt_tlclk = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 268435456UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@10060000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_E76_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h
index f99ea6f..d99248d 100644
--- a/bsp/coreip-e76-arty/metal-platform.h
+++ b/bsp/coreip-e76-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H
 #define COREIP_E76_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 31UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 31UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -33,13 +45,21 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@10060000 */
 #define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268828672UL
 #define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_1_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_1_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -60,9 +80,54 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -84,14 +149,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds
index ccd5fb0..5f18721 100644
--- a/bsp/coreip-e76-arty/metal.default.lds
+++ b/bsp/coreip-e76-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h
index 7115c2a..21a9416 100644
--- a/bsp/coreip-e76-arty/metal.h
+++ b/bsp/coreip-e76-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E76_ARTY__METAL_H
-#define COREIP_E76_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E76_ARTY__METAL_H
+#define MACROS_IF_COREIP_E76_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E76_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E76_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_E76_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -78,399 +89,776 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From tlclk */
-asm (".weak __metal_dt_tlclk");
 struct __metal_driver_fixed_clock __metal_dt_tlclk;
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@10060000 */
-asm (".weak __metal_dt_gpio_10060000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From tlclk */
-struct __metal_driver_fixed_clock __metal_dt_tlclk = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 268435456UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 65000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_tlclk) {
+		return METAL_FIXED_CLOCK__CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 65000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 21;
+	}
+	else if (idx == 1) {
+		return 22;
+	}
+	else if (idx == 2) {
+		return 23;
+	}
+	else if (idx == 3) {
+		return 24;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_SIZE;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 0)) {
+		return 27;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 1))) {
+		return 28;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 2))) {
+		return 29;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 3))) {
+		return 30;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0))) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 16;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 1;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 2;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 1;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 2;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 25;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 21,
-    .interrupt_lines[1] = 22,
-    .interrupt_lines[2] = 23,
-    .interrupt_lines[3] = 24,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From gpio@10060000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 27,
-    .interrupt_lines[1] = 28,
-    .interrupt_lines[2] = 29,
-    .interrupt_lines[3] = 30,
-};
-
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-};
-
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 4UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "BTN0",
-};
-
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 5UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "BTN1",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 6UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "BTN2",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 7UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 3UL,
-    .label = "BTN3",
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 3UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 25UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 2
@@ -555,7 +943,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E76_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E76_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds
index 2c0d61e..2399c34 100644
--- a/bsp/coreip-e76-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e76-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds
index fe384ff..f218377 100644
--- a/bsp/coreip-e76-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e76-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk
index 62d3775..115db75 100644
--- a/bsp/coreip-e76-arty/settings.mk
+++ b/bsp/coreip-e76-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-e76-rtl/metal-inline.h b/bsp/coreip-e76-rtl/metal-inline.h
new file mode 100644
index 0000000..fe18ce9
--- /dev/null
+++ b/bsp/coreip-e76-rtl/metal-inline.h
@@ -0,0 +1,146 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_E76_RTL__METAL_INLINE_H
+#define COREIP_E76_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_E76_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h
index 0e9e786..fc2e618 100644
--- a/bsp/coreip-e76-rtl/metal-platform.h
+++ b/bsp/coreip-e76-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_E76_RTL__METAL_PLATFORM_H
 #define COREIP_E76_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 128UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,15 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds
index e21f7c0..84b0c14 100644
--- a/bsp/coreip-e76-rtl/metal.default.lds
+++ b/bsp/coreip-e76-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h
index 5865710..84e5823 100644
--- a/bsp/coreip-e76-rtl/metal.h
+++ b/bsp/coreip-e76-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_E76_RTL__METAL_H
-#define COREIP_E76_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_E76_RTL__METAL_H
+#define MACROS_IF_COREIP_E76_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_E76_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_E76_RTL__METAL_H
+#define MACROS_ELSE_COREIP_E76_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -65,240 +76,652 @@
 #include <metal/drivers/sifive,global-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 1
@@ -361,7 +784,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_E76_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_E76_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds
index 901ac13..60429dd 100644
--- a/bsp/coreip-e76-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -160,18 +166,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds
index e21f7c0..84b0c14 100644
--- a/bsp/coreip-e76-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk
index 4d7cae7..18bea9e 100644
--- a/bsp/coreip-e76-rtl/settings.mk
+++ b/bsp/coreip-e76-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
diff --git a/bsp/coreip-s51-arty/metal-inline.h b/bsp/coreip-s51-arty/metal-inline.h
new file mode 100644
index 0000000..7fe8125
--- /dev/null
+++ b/bsp/coreip-s51-arty/metal-inline.h
@@ -0,0 +1,285 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_S51_ARTY__METAL_INLINE_H
+#define COREIP_S51_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_S51_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s51-arty/metal-platform.h b/bsp/coreip-s51-arty/metal-platform.h
index b6301ea..2d97f6c 100644
--- a/bsp/coreip-s51-arty/metal-platform.h
+++ b/bsp/coreip-s51-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_S51_ARTY__METAL_PLATFORM_H
 #define COREIP_S51_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -33,9 +45,15 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -56,9 +74,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -80,14 +147,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-s51-arty/metal.default.lds b/bsp/coreip-s51-arty/metal.default.lds
index 87bc213..82a199e 100644
--- a/bsp/coreip-s51-arty/metal.default.lds
+++ b/bsp/coreip-s51-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h
index 1e17084..9d1a901 100644
--- a/bsp/coreip-s51-arty/metal.h
+++ b/bsp/coreip-s51-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_S51_ARTY__METAL_H
-#define COREIP_S51_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_S51_ARTY__METAL_H
+#define MACROS_IF_COREIP_S51_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_S51_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_S51_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_S51_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -79,422 +90,829 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 65000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
-
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 23,
-    .interrupt_lines[1] = 24,
-    .interrupt_lines[2] = 25,
-    .interrupt_lines[3] = 26,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 65000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 23;
+	}
+	else if (idx == 1) {
+		return 24;
+	}
+	else if (idx == 2) {
+		return 25;
+	}
+	else if (idx == 3) {
+		return 26;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 16;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 1;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 2;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 17;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 4UL,
-    .label = "BTN0",
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 5UL,
-    .label = "BTN1",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 6UL,
-    .label = "BTN2",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 7UL,
-    .label = "BTN3",
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 3UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 17UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -584,7 +1002,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_S51_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_S51_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s51-arty/metal.ramrodata.lds b/bsp/coreip-s51-arty/metal.ramrodata.lds
index 2056624..22eeb0a 100644
--- a/bsp/coreip-s51-arty/metal.ramrodata.lds
+++ b/bsp/coreip-s51-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s51-arty/metal.scratchpad.lds b/bsp/coreip-s51-arty/metal.scratchpad.lds
index fe62b3a..808429b 100644
--- a/bsp/coreip-s51-arty/metal.scratchpad.lds
+++ b/bsp/coreip-s51-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk
index 2832d7c..19205af 100644
--- a/bsp/coreip-s51-arty/settings.mk
+++ b/bsp/coreip-s51-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imac
 RISCV_ABI=lp64
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-s51-rtl/metal-inline.h b/bsp/coreip-s51-rtl/metal-inline.h
new file mode 100644
index 0000000..06b7384
--- /dev/null
+++ b/bsp/coreip-s51-rtl/metal-inline.h
@@ -0,0 +1,177 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_S51_RTL__METAL_INLINE_H
+#define COREIP_S51_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 67108864UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_S51_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s51-rtl/metal-platform.h b/bsp/coreip-s51-rtl/metal-platform.h
index b1cf1a6..009cad9 100644
--- a/bsp/coreip-s51-rtl/metal-platform.h
+++ b/bsp/coreip-s51-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_S51_RTL__METAL_PLATFORM_H
 #define COREIP_S51_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 128UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,19 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-s51-rtl/metal.default.lds b/bsp/coreip-s51-rtl/metal.default.lds
index e616f3d..e68e937 100644
--- a/bsp/coreip-s51-rtl/metal.default.lds
+++ b/bsp/coreip-s51-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h
index d9b198f..6cf2856 100644
--- a/bsp/coreip-s51-rtl/metal.h
+++ b/bsp/coreip-s51-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_S51_RTL__METAL_H
-#define COREIP_S51_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_S51_RTL__METAL_H
+#define MACROS_IF_COREIP_S51_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_S51_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_S51_RTL__METAL_H
+#define MACROS_ELSE_COREIP_S51_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -68,297 +79,734 @@
 #include <metal/drivers/sifive,global-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 67108864UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -428,7 +876,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_S51_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_S51_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s51-rtl/metal.ramrodata.lds b/bsp/coreip-s51-rtl/metal.ramrodata.lds
index 9aa142b..448d7ed 100644
--- a/bsp/coreip-s51-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-s51-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s51-rtl/metal.scratchpad.lds b/bsp/coreip-s51-rtl/metal.scratchpad.lds
index 3d4d966..4d43737 100644
--- a/bsp/coreip-s51-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-s51-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk
index 4d48fc1..6af5958 100644
--- a/bsp/coreip-s51-rtl/settings.mk
+++ b/bsp/coreip-s51-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imac
 RISCV_ABI=lp64
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-s54-arty/metal-inline.h b/bsp/coreip-s54-arty/metal-inline.h
new file mode 100644
index 0000000..fee9bcd
--- /dev/null
+++ b/bsp/coreip-s54-arty/metal-inline.h
@@ -0,0 +1,285 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_S54_ARTY__METAL_INLINE_H
+#define COREIP_S54_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_S54_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s54-arty/metal-platform.h b/bsp/coreip-s54-arty/metal-platform.h
index e715d34..7f1e2d0 100644
--- a/bsp/coreip-s54-arty/metal-platform.h
+++ b/bsp/coreip-s54-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_S54_ARTY__METAL_PLATFORM_H
 #define COREIP_S54_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -33,9 +45,15 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -56,9 +74,58 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -80,14 +147,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-s54-arty/metal.default.lds b/bsp/coreip-s54-arty/metal.default.lds
index 87bc213..82a199e 100644
--- a/bsp/coreip-s54-arty/metal.default.lds
+++ b/bsp/coreip-s54-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h
index 6a6dbb7..fd36163 100644
--- a/bsp/coreip-s54-arty/metal.h
+++ b/bsp/coreip-s54-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_S54_ARTY__METAL_H
-#define COREIP_S54_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_S54_ARTY__METAL_H
+#define MACROS_IF_COREIP_S54_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_S54_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_S54_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_S54_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -79,422 +90,829 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 65000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
-
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 23,
-    .interrupt_lines[1] = 24,
-    .interrupt_lines[2] = 25,
-    .interrupt_lines[3] = 26,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 65000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 23;
+	}
+	else if (idx == 1) {
+		return 24;
+	}
+	else if (idx == 2) {
+		return 25;
+	}
+	else if (idx == 3) {
+		return 26;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0)) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 16;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_20002000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_local_external_interrupts_0;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 1;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 2;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 17;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 4UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 4UL,
-    .label = "BTN0",
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 5UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 5UL,
-    .label = "BTN1",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 6UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 6UL,
-    .label = "BTN2",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 7UL,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 7UL,
-    .label = "BTN3",
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@20002000 */
-    .gpio = &__metal_dt_gpio_20002000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From local_external_interrupts_0 */
-    .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc,
-    .interrupt_line = 3UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 17UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -584,7 +1002,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_S54_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_S54_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s54-arty/metal.ramrodata.lds b/bsp/coreip-s54-arty/metal.ramrodata.lds
index 2056624..22eeb0a 100644
--- a/bsp/coreip-s54-arty/metal.ramrodata.lds
+++ b/bsp/coreip-s54-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s54-arty/metal.scratchpad.lds b/bsp/coreip-s54-arty/metal.scratchpad.lds
index fe62b3a..808429b 100644
--- a/bsp/coreip-s54-arty/metal.scratchpad.lds
+++ b/bsp/coreip-s54-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk
index d001dee..4ce0f71 100644
--- a/bsp/coreip-s54-arty/settings.mk
+++ b/bsp/coreip-s54-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imafdc
 RISCV_ABI=lp64d
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-s54-rtl/metal-inline.h b/bsp/coreip-s54-rtl/metal-inline.h
new file mode 100644
index 0000000..402ee7e
--- /dev/null
+++ b/bsp/coreip-s54-rtl/metal-inline.h
@@ -0,0 +1,177 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_S54_RTL__METAL_INLINE_H
+#define COREIP_S54_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 67108864UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 65536UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_S54_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s54-rtl/metal-platform.h b/bsp/coreip-s54-rtl/metal-platform.h
index 78b3b50..3906b83 100644
--- a/bsp/coreip-s54-rtl/metal-platform.h
+++ b/bsp/coreip-s54-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_S54_RTL__METAL_PLATFORM_H
 #define COREIP_S54_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 128UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,19 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-s54-rtl/metal.default.lds b/bsp/coreip-s54-rtl/metal.default.lds
index e616f3d..e68e937 100644
--- a/bsp/coreip-s54-rtl/metal.default.lds
+++ b/bsp/coreip-s54-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s54-rtl/metal.h b/bsp/coreip-s54-rtl/metal.h
index fcb10c4..6d8e8e1 100644
--- a/bsp/coreip-s54-rtl/metal.h
+++ b/bsp/coreip-s54-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_S54_RTL__METAL_H
-#define COREIP_S54_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_S54_RTL__METAL_H
+#define MACROS_IF_COREIP_S54_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_S54_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_S54_RTL__METAL_H
+#define MACROS_ELSE_COREIP_S54_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -68,297 +79,734 @@
 #include <metal/drivers/sifive,global-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_testram_20000000");
 struct metal_memory __metal_dt_mem_testram_20000000;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_testram_20000000 = {
-    ._base_address = 536870912UL,
-    ._size = 67108864UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 65536UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -428,7 +876,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_S54_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_S54_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s54-rtl/metal.ramrodata.lds b/bsp/coreip-s54-rtl/metal.ramrodata.lds
index 9aa142b..448d7ed 100644
--- a/bsp/coreip-s54-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-s54-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s54-rtl/metal.scratchpad.lds b/bsp/coreip-s54-rtl/metal.scratchpad.lds
index 3d4d966..4d43737 100644
--- a/bsp/coreip-s54-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-s54-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk
index 37a07af..c7a4614 100644
--- a/bsp/coreip-s54-rtl/settings.mk
+++ b/bsp/coreip-s54-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imafdc
 RISCV_ABI=lp64d
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-s76-arty/metal-inline.h b/bsp/coreip-s76-arty/metal-inline.h
new file mode 100644
index 0000000..6d4d486
--- /dev/null
+++ b/bsp/coreip-s76-arty/metal-inline.h
@@ -0,0 +1,270 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_S76_ARTY__METAL_INLINE_H
+#define COREIP_S76_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button);
+extern inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button);
+extern inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button);
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip);
+extern inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip);
+extern inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip);
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From tlclk */
+struct __metal_driver_fixed_clock __metal_dt_tlclk = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 268435456UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_20004000 = {
+    ._base_address = 1073741824UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@10060000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From gpio@20002000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From button@0 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@1 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@2 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From button@3 */
+struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
+    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From switch@0 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@1 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@2 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From switch@3 */
+struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
+    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
+};
+
+/* From spi@20004000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@20000000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* COREIP_S76_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h
index 3be1bb1..eda81f7 100644
--- a/bsp/coreip-s76-arty/metal-platform.h
+++ b/bsp/coreip-s76-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_S76_ARTY__METAL_PLATFORM_H
 #define COREIP_S76_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 31UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 31UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -33,13 +45,21 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From gpio@10060000 */
 #define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268828672UL
 #define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 /* From gpio@20002000 */
 #define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_1_BASE_ADDRESS 536879104UL
 #define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_1_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -60,9 +80,54 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From button@0 */
+
+/* From button@1 */
+
+/* From button@2 */
+
+/* From button@3 */
+
+#define METAL_SIFIVE_GPIO_BUTTONS
+
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From switch@0 */
+
+/* From switch@1 */
+
+/* From switch@2 */
+
+/* From switch@3 */
+
+#define METAL_SIFIVE_GPIO_SWITCHES
+
+/* From pwm@20005000 */
+#define METAL_SIFIVE_PWM0_20005000_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 536891392UL
+#define METAL_SIFIVE_PWM0_20005000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@20004000 */
 #define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 536887296UL
 #define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -84,14 +149,18 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@20000000 */
 #define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 536870912UL
 #define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds
index ccd5fb0..5f18721 100644
--- a/bsp/coreip-s76-arty/metal.default.lds
+++ b/bsp/coreip-s76-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h
index f42456d..7c64fc7 100644
--- a/bsp/coreip-s76-arty/metal.h
+++ b/bsp/coreip-s76-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_S76_ARTY__METAL_H
-#define COREIP_S76_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_S76_ARTY__METAL_H
+#define MACROS_IF_COREIP_S76_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_S76_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_S76_ARTY__METAL_H
+#define MACROS_ELSE_COREIP_S76_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -78,399 +89,776 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From tlclk */
-asm (".weak __metal_dt_tlclk");
 struct __metal_driver_fixed_clock __metal_dt_tlclk;
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
-asm (".weak __metal_dt_mem_spi_20004000");
 struct metal_memory __metal_dt_mem_spi_20004000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From gpio@10060000 */
-asm (".weak __metal_dt_gpio_10060000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000;
 
 /* From gpio@20002000 */
-asm (".weak __metal_dt_gpio_20002000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000;
 
 /* From button@0 */
-asm (".weak __metal_dt_button_0");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_0;
 
 /* From button@1 */
-asm (".weak __metal_dt_button_1");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_1;
 
 /* From button@2 */
-asm (".weak __metal_dt_button_2");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_2;
 
 /* From button@3 */
-asm (".weak __metal_dt_button_3");
 struct __metal_driver_sifive_gpio_button __metal_dt_button_3;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From switch@0 */
-asm (".weak __metal_dt_switch_0");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0;
 
 /* From switch@1 */
-asm (".weak __metal_dt_switch_1");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1;
 
 /* From switch@2 */
-asm (".weak __metal_dt_switch_2");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2;
 
 /* From switch@3 */
-asm (".weak __metal_dt_switch_3");
 struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3;
 
 /* From spi@20004000 */
-asm (".weak __metal_dt_spi_20004000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@20000000 */
-asm (".weak __metal_dt_serial_20000000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 
 
-/* From tlclk */
-struct __metal_driver_fixed_clock __metal_dt_tlclk = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 268435456UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_20004000 = {
-    ._base_address = 1073741824UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 65000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_tlclk) {
+		return METAL_FIXED_CLOCK__CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 65000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 21;
+	}
+	else if (idx == 1) {
+		return 22;
+	}
+	else if (idx == 2) {
+		return 23;
+	}
+	else if (idx == 3) {
+		return 24;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_SIZE;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_SIFIVE_GPIO0_20002000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 0)) {
+		return 27;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 1))) {
+		return 28;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 2))) {
+		return 29;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 3))) {
+		return 30;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 0))) {
+		return 1;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 1))) {
+		return 2;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 2))) {
+		return 3;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 3))) {
+		return 4;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 4))) {
+		return 5;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 5))) {
+		return 6;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 6))) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 7))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 8))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 9))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 10))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 11))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 12))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 13))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 14))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_20002000) && (idx == 15))) {
+		return 16;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_button_gpio(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_pin(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 4;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 5;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 6;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_button_interrupt_controller(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_button_interrupt_line(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return 0;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return 1;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return 2;
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_button_label(struct metal_button *button)
+{
+	if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_0) {
+		return "BTN0";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_1) {
+		return "BTN1";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_2) {
+		return "BTN2";
+	}
+	else if ((uintptr_t)button == (uintptr_t)&__metal_dt_button_3) {
+		return "BTN3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10060000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 0;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 1;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 2;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_switch_gpio(struct metal_switch *flip)
+{
+		return NULL;
+}
+
+static inline int __metal_driver_sifive_gpio_switch_pin(struct metal_switch *flip)
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio_switch_interrupt_controller(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return (struct metal_interrupt *)&__metal_dt_global_external_interrupts;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_switch_interrupt_line(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return 0;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return 1;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return 2;
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return 3;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_switch_label(struct metal_switch *flip)
+{
+	if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_0) {
+		return "SW0";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_1) {
+		return "SW1";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_2) {
+		return "SW2";
+	}
+	else if ((uintptr_t)flip == (uintptr_t)&__metal_dt_switch_3) {
+		return "SW3";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_20004000) {
+		return METAL_SIFIVE_SPI0_20004000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_SIFIVE_UART0_20000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_20000000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 25;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 21,
-    .interrupt_lines[1] = 22,
-    .interrupt_lines[2] = 23,
-    .interrupt_lines[3] = 24,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From gpio@10060000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 27,
-    .interrupt_lines[1] = 28,
-    .interrupt_lines[2] = 29,
-    .interrupt_lines[3] = 30,
-};
-
-/* From gpio@20002000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-};
-
-/* From button@0 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 4UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "BTN0",
-};
-
-/* From button@1 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 5UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "BTN1",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@2 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 6UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "BTN2",
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From button@3 */
-struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = {
-    .vtable = &__metal_driver_vtable_sifive_button,
-    .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 7UL,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 3UL,
-    .label = "BTN3",
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 0UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 1UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10060000 */
-    .gpio = &__metal_dt_gpio_10060000,
-    .pin = 2UL,
-    .label = "LD0blue",
-};
 
-/* From switch@0 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 0UL,
-    .label = "SW0",
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From switch@1 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 1UL,
-    .label = "SW1",
-};
 
-/* From switch@2 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 2UL,
-    .label = "SW2",
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From switch@3 */
-struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
-    .vtable = &__metal_driver_vtable_sifive_switch,
-    .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable,
-    .gpio = NULL,
-    .pin = 0,
-/* From global_external_interrupts */
-    .interrupt_parent = &__metal_dt_global_external_interrupts.irc,
-    .interrupt_line = 3UL,
-    .label = "SW3",
-};
 
-/* From spi@20004000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
 
-/* From serial@20000000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 25UL,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 2
@@ -555,7 +943,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_S76_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_S76_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds
index 2c0d61e..2399c34 100644
--- a/bsp/coreip-s76-arty/metal.ramrodata.lds
+++ b/bsp/coreip-s76-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds
index fe384ff..f218377 100644
--- a/bsp/coreip-s76-arty/metal.scratchpad.lds
+++ b/bsp/coreip-s76-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk
index d001dee..4ce0f71 100644
--- a/bsp/coreip-s76-arty/settings.mk
+++ b/bsp/coreip-s76-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imafdc
 RISCV_ABI=lp64d
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-s76-rtl/metal-inline.h b/bsp/coreip-s76-rtl/metal-inline.h
new file mode 100644
index 0000000..1d139e1
--- /dev/null
+++ b/bsp/coreip-s76-rtl/metal-inline.h
@@ -0,0 +1,146 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_S76_RTL__METAL_INLINE_H
+#define COREIP_S76_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+
+#endif /* COREIP_S76_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s76-rtl/metal-platform.h b/bsp/coreip-s76-rtl/metal-platform.h
index d3ecc4c..2d911a5 100644
--- a/bsp/coreip-s76-rtl/metal-platform.h
+++ b/bsp/coreip-s76-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 #ifndef COREIP_S76_RTL__METAL_PLATFORM_H
 #define COREIP_S76_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 128UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,15 @@
 
 #define METAL_RISCV_PMP
 
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-s76-rtl/metal.default.lds b/bsp/coreip-s76-rtl/metal.default.lds
index e21f7c0..84b0c14 100644
--- a/bsp/coreip-s76-rtl/metal.default.lds
+++ b/bsp/coreip-s76-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h
index 1187b69..3221ed3 100644
--- a/bsp/coreip-s76-rtl/metal.h
+++ b/bsp/coreip-s76-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
 
-#ifndef COREIP_S76_RTL__METAL_H
-#define COREIP_S76_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_S76_RTL__METAL_H
+#define MACROS_IF_COREIP_S76_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_S76_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_S76_RTL__METAL_H
+#define MACROS_ELSE_COREIP_S76_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -65,240 +76,652 @@
 #include <metal/drivers/sifive,global-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 1
@@ -361,7 +784,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+#endif /* MACROS_ELSE_COREIP_S76_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_S76_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-s76-rtl/metal.ramrodata.lds b/bsp/coreip-s76-rtl/metal.ramrodata.lds
index 901ac13..60429dd 100644
--- a/bsp/coreip-s76-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-s76-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -160,18 +166,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s76-rtl/metal.scratchpad.lds b/bsp/coreip-s76-rtl/metal.scratchpad.lds
index e21f7c0..84b0c14 100644
--- a/bsp/coreip-s76-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-s76-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-10        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk
index 37a07af..c7a4614 100644
--- a/bsp/coreip-s76-rtl/settings.mk
+++ b/bsp/coreip-s76-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-10        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imafdc
 RISCV_ABI=lp64d
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h
new file mode 100644
index 0000000..03d29e6
--- /dev/null
+++ b/bsp/coreip-u54-rtl/metal-inline.h
@@ -0,0 +1,162 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_U54_RTL__METAL_INLINE_H
+#define COREIP_U54_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_itim_1800000 = {
+    ._base_address = 25165824UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From cache_controller@2010000 */
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
+    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
+};
+
+
+#endif /* COREIP_U54_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h
index 79432cd..562f263 100644
--- a/bsp/coreip-u54-rtl/metal-platform.h
+++ b/bsp/coreip-u54-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 #ifndef COREIP_U54_RTL__METAL_PLATFORM_H
 #define COREIP_U54_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 133UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 133UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,25 @@
 
 #define METAL_RISCV_PMP
 
+/* From cache_controller@2010000 */
+#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL
+#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL
+
+#define METAL_SIFIVE_FU540_C000_L2
+#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL
+#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL
+
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds
index ae24b07..3a5705a 100644
--- a/bsp/coreip-u54-rtl/metal.default.lds
+++ b/bsp/coreip-u54-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h
index 38e231f..0621896 100644
--- a/bsp/coreip-u54-rtl/metal.h
+++ b/bsp/coreip-u54-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef COREIP_U54_RTL__METAL_H
-#define COREIP_U54_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_U54_RTL__METAL_H
+#define MACROS_IF_COREIP_U54_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_U54_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_U54_RTL__METAL_H
+#define MACROS_ELSE_COREIP_U54_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -66,266 +77,663 @@
 #include <metal/drivers/sifive,test0.h>
 #include <metal/drivers/sifive,fu540-c000,l2.h>
 
-asm (".weak __metal_dt_mem_itim_1800000");
 struct metal_memory __metal_dt_mem_itim_1800000;
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From cache_controller@2010000 */
-asm (".weak __metal_dt_cache_controller_2010000");
 struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
 
 
-struct metal_memory __metal_dt_mem_itim_1800000 = {
-    ._base_address = 25165824UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 1) {
+		return 9;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 9,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
-    .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2,
-    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 2
@@ -389,7 +797,13 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+/* From cache_controller@2010000 */
+#define __METAL_DT_SIFIVE_FU540_C000_L2_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#define __METAL_DT_CACHE_CONTROLLER_2010000_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#endif /* MACROS_ELSE_COREIP_U54_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_U54_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds
index 306ba19..2873493 100644
--- a/bsp/coreip-u54-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -160,18 +166,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds
index ae24b07..3a5705a 100644
--- a/bsp/coreip-u54-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk
index d6b3a83..6c25a1f 100644
--- a/bsp/coreip-u54-rtl/settings.mk
+++ b/bsp/coreip-u54-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-11        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imafdc
 RISCV_ABI=lp64d
 RISCV_CMODEL=medany
diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h
new file mode 100644
index 0000000..58f8acc
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/metal-inline.h
@@ -0,0 +1,261 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef COREIP_U54MC_RTL__METAL_INLINE_H
+#define COREIP_U54MC_RTL__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
+extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+struct metal_memory __metal_dt_mem_dtim_1000000 = {
+    ._base_address = 16777216UL,
+    ._size = 8192UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1800000 = {
+    ._base_address = 25165824UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1808000 = {
+    ._base_address = 25198592UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1810000 = {
+    ._base_address = 25231360UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1818000 = {
+    ._base_address = 25264128UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1820000 = {
+    ._base_address = 25296896UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@1 */
+struct __metal_driver_cpu __metal_dt_cpu_1 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@2 */
+struct __metal_driver_cpu __metal_dt_cpu_2 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@3 */
+struct __metal_driver_cpu __metal_dt_cpu_3 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@4 */
+struct __metal_driver_cpu __metal_dt_cpu_4 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From global_external_interrupts */
+struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
+    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
+    .init_done = 0,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From cache_controller@2010000 */
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
+    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
+};
+
+
+#endif /* COREIP_U54MC_RTL__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h
index a2ef2dc..6df003f 100644
--- a/bsp/coreip-u54mc-rtl/metal-platform.h
+++ b/bsp/coreip-u54mc-rtl/metal-platform.h
@@ -1,9 +1,17 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H
 #define COREIP_U54MC_RTL__METAL_PLATFORM_H
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -12,9 +20,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 137UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 137UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -28,9 +40,25 @@
 
 #define METAL_RISCV_PMP
 
+/* From cache_controller@2010000 */
+#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL
+#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL
+
+#define METAL_SIFIVE_FU540_C000_L2
+#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL
+#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL
+
+/* From global_external_interrupts */
+
+#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
+
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds
index 0d12f67..ea7c853 100644
--- a/bsp/coreip-u54mc-rtl/metal.default.lds
+++ b/bsp/coreip-u54mc-rtl/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h
index 935e165..dab7ff4 100644
--- a/bsp/coreip-u54mc-rtl/metal.h
+++ b/bsp/coreip-u54mc-rtl/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef COREIP_U54MC_RTL__METAL_H
-#define COREIP_U54MC_RTL__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_COREIP_U54MC_RTL__METAL_H
+#define MACROS_IF_COREIP_U54MC_RTL__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 10
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_COREIP_U54MC_RTL__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_COREIP_U54MC_RTL__METAL_H
+#define MACROS_ELSE_COREIP_U54MC_RTL__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 10
 
 #define METAL_MAX_CLINT_INTERRUPTS 10
@@ -66,458 +77,807 @@
 #include <metal/drivers/sifive,test0.h>
 #include <metal/drivers/sifive,fu540-c000,l2.h>
 
-asm (".weak __metal_dt_mem_dtim_1000000");
 struct metal_memory __metal_dt_mem_dtim_1000000;
 
-asm (".weak __metal_dt_mem_itim_1800000");
 struct metal_memory __metal_dt_mem_itim_1800000;
 
-asm (".weak __metal_dt_mem_itim_1808000");
 struct metal_memory __metal_dt_mem_itim_1808000;
 
-asm (".weak __metal_dt_mem_itim_1810000");
 struct metal_memory __metal_dt_mem_itim_1810000;
 
-asm (".weak __metal_dt_mem_itim_1818000");
 struct metal_memory __metal_dt_mem_itim_1818000;
 
-asm (".weak __metal_dt_mem_itim_1820000");
 struct metal_memory __metal_dt_mem_itim_1820000;
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
 /* From cpu@1 */
-asm (".weak __metal_dt_cpu_1");
 struct __metal_driver_cpu __metal_dt_cpu_1;
 
 /* From cpu@2 */
-asm (".weak __metal_dt_cpu_2");
 struct __metal_driver_cpu __metal_dt_cpu_2;
 
 /* From cpu@3 */
-asm (".weak __metal_dt_cpu_3");
 struct __metal_driver_cpu __metal_dt_cpu_3;
 
 /* From cpu@4 */
-asm (".weak __metal_dt_cpu_4");
 struct __metal_driver_cpu __metal_dt_cpu_4;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_1_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_2_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_3_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_4_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From global_external_interrupts */
-asm (".weak __metal_dt_global_external_interrupts");
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From cache_controller@2010000 */
-asm (".weak __metal_dt_cache_controller_2010000");
 struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
 
 
-struct metal_memory __metal_dt_mem_dtim_1000000 = {
-    ._base_address = 16777216UL,
-    ._size = 8192UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1800000 = {
-    ._base_address = 25165824UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1808000 = {
-    ._base_address = 25198592UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1810000 = {
-    ._base_address = 25231360UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1818000 = {
-    ._base_address = 25264128UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1820000 = {
-    ._base_address = 25296896UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[2] = 3,
-    .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[3] = 7,
-    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[4] = 3,
-    .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[5] = 7,
-    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[6] = 3,
-    .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[7] = 7,
-    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[8] = 3,
-    .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[9] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 2) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 3) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 4) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 5) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 6) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 7) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 8) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else if (idx == 9) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 7;
+	}
+	else if (idx == 4) {
+		return 3;
+	}
+	else if (idx == 5) {
+		return 7;
+	}
+	else if (idx == 6) {
+		return 3;
+	}
+	else if (idx == 7) {
+		return 7;
+	}
+	else if (idx == 8) {
+		return 3;
+	}
+	else if (idx == 9) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+		return &__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+		return &__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+		return &__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 2) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 3) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 4) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 5) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 6) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 7) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else if (idx == 8) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 1) {
+		return 11;
+	}
+	else if (idx == 2) {
+		return 9;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else if (idx == 4) {
+		return 9;
+	}
+	else if (idx == 5) {
+		return 11;
+	}
+	else if (idx == 6) {
+		return 9;
+	}
+	else if (idx == 7) {
+		return 11;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
+{
+		return 0;
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
+		return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 1;
+	}
+	else if (idx == 1) {
+		return 2;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 4;
+	}
+	else if (idx == 4) {
+		return 5;
+	}
+	else if (idx == 5) {
+		return 6;
+	}
+	else if (idx == 6) {
+		return 7;
+	}
+	else if (idx == 7) {
+		return 8;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else if (idx == 9) {
+		return 10;
+	}
+	else if (idx == 10) {
+		return 11;
+	}
+	else if (idx == 11) {
+		return 12;
+	}
+	else if (idx == 12) {
+		return 13;
+	}
+	else if (idx == 13) {
+		return 14;
+	}
+	else if (idx == 14) {
+		return 15;
+	}
+	else if (idx == 15) {
+		return 16;
+	}
+	else if (idx == 16) {
+		return 17;
+	}
+	else if (idx == 17) {
+		return 18;
+	}
+	else if (idx == 18) {
+		return 19;
+	}
+	else if (idx == 19) {
+		return 20;
+	}
+	else if (idx == 20) {
+		return 21;
+	}
+	else if (idx == 21) {
+		return 22;
+	}
+	else if (idx == 22) {
+		return 23;
+	}
+	else if (idx == 23) {
+		return 24;
+	}
+	else if (idx == 24) {
+		return 25;
+	}
+	else if (idx == 25) {
+		return 26;
+	}
+	else if (idx == 26) {
+		return 27;
+	}
+	else if (idx == 27) {
+		return 28;
+	}
+	else if (idx == 28) {
+		return 29;
+	}
+	else if (idx == 29) {
+		return 30;
+	}
+	else if (idx == 30) {
+		return 31;
+	}
+	else if (idx == 31) {
+		return 32;
+	}
+	else if (idx == 32) {
+		return 33;
+	}
+	else if (idx == 33) {
+		return 34;
+	}
+	else if (idx == 34) {
+		return 35;
+	}
+	else if (idx == 35) {
+		return 36;
+	}
+	else if (idx == 36) {
+		return 37;
+	}
+	else if (idx == 37) {
+		return 38;
+	}
+	else if (idx == 38) {
+		return 39;
+	}
+	else if (idx == 39) {
+		return 40;
+	}
+	else if (idx == 40) {
+		return 41;
+	}
+	else if (idx == 41) {
+		return 42;
+	}
+	else if (idx == 42) {
+		return 43;
+	}
+	else if (idx == 43) {
+		return 44;
+	}
+	else if (idx == 44) {
+		return 45;
+	}
+	else if (idx == 45) {
+		return 46;
+	}
+	else if (idx == 46) {
+		return 47;
+	}
+	else if (idx == 47) {
+		return 48;
+	}
+	else if (idx == 48) {
+		return 49;
+	}
+	else if (idx == 49) {
+		return 50;
+	}
+	else if (idx == 50) {
+		return 51;
+	}
+	else if (idx == 51) {
+		return 52;
+	}
+	else if (idx == 52) {
+		return 53;
+	}
+	else if (idx == 53) {
+		return 54;
+	}
+	else if (idx == 54) {
+		return 55;
+	}
+	else if (idx == 55) {
+		return 56;
+	}
+	else if (idx == 56) {
+		return 57;
+	}
+	else if (idx == 57) {
+		return 58;
+	}
+	else if (idx == 58) {
+		return 59;
+	}
+	else if (idx == 59) {
+		return 60;
+	}
+	else if (idx == 60) {
+		return 61;
+	}
+	else if (idx == 61) {
+		return 62;
+	}
+	else if (idx == 62) {
+		return 63;
+	}
+	else if (idx == 63) {
+		return 64;
+	}
+	else if (idx == 64) {
+		return 65;
+	}
+	else if (idx == 65) {
+		return 66;
+	}
+	else if (idx == 66) {
+		return 67;
+	}
+	else if (idx == 67) {
+		return 68;
+	}
+	else if (idx == 68) {
+		return 69;
+	}
+	else if (idx == 69) {
+		return 70;
+	}
+	else if (idx == 70) {
+		return 71;
+	}
+	else if (idx == 71) {
+		return 72;
+	}
+	else if (idx == 72) {
+		return 73;
+	}
+	else if (idx == 73) {
+		return 74;
+	}
+	else if (idx == 74) {
+		return 75;
+	}
+	else if (idx == 75) {
+		return 76;
+	}
+	else if (idx == 76) {
+		return 77;
+	}
+	else if (idx == 77) {
+		return 78;
+	}
+	else if (idx == 78) {
+		return 79;
+	}
+	else if (idx == 79) {
+		return 80;
+	}
+	else if (idx == 80) {
+		return 81;
+	}
+	else if (idx == 81) {
+		return 82;
+	}
+	else if (idx == 82) {
+		return 83;
+	}
+	else if (idx == 83) {
+		return 84;
+	}
+	else if (idx == 84) {
+		return 85;
+	}
+	else if (idx == 85) {
+		return 86;
+	}
+	else if (idx == 86) {
+		return 87;
+	}
+	else if (idx == 87) {
+		return 88;
+	}
+	else if (idx == 88) {
+		return 89;
+	}
+	else if (idx == 89) {
+		return 90;
+	}
+	else if (idx == 90) {
+		return 91;
+	}
+	else if (idx == 91) {
+		return 92;
+	}
+	else if (idx == 92) {
+		return 93;
+	}
+	else if (idx == 93) {
+		return 94;
+	}
+	else if (idx == 94) {
+		return 95;
+	}
+	else if (idx == 95) {
+		return 96;
+	}
+	else if (idx == 96) {
+		return 97;
+	}
+	else if (idx == 97) {
+		return 98;
+	}
+	else if (idx == 98) {
+		return 99;
+	}
+	else if (idx == 99) {
+		return 100;
+	}
+	else if (idx == 100) {
+		return 101;
+	}
+	else if (idx == 101) {
+		return 102;
+	}
+	else if (idx == 102) {
+		return 103;
+	}
+	else if (idx == 103) {
+		return 104;
+	}
+	else if (idx == 104) {
+		return 105;
+	}
+	else if (idx == 105) {
+		return 106;
+	}
+	else if (idx == 106) {
+		return 107;
+	}
+	else if (idx == 107) {
+		return 108;
+	}
+	else if (idx == 108) {
+		return 109;
+	}
+	else if (idx == 109) {
+		return 110;
+	}
+	else if (idx == 110) {
+		return 111;
+	}
+	else if (idx == 111) {
+		return 112;
+	}
+	else if (idx == 112) {
+		return 113;
+	}
+	else if (idx == 113) {
+		return 114;
+	}
+	else if (idx == 114) {
+		return 115;
+	}
+	else if (idx == 115) {
+		return 116;
+	}
+	else if (idx == 116) {
+		return 117;
+	}
+	else if (idx == 117) {
+		return 118;
+	}
+	else if (idx == 118) {
+		return 119;
+	}
+	else if (idx == 119) {
+		return 120;
+	}
+	else if (idx == 120) {
+		return 121;
+	}
+	else if (idx == 121) {
+		return 122;
+	}
+	else if (idx == 122) {
+		return 123;
+	}
+	else if (idx == 123) {
+		return 124;
+	}
+	else if (idx == 124) {
+		return 125;
+	}
+	else if (idx == 125) {
+		return 126;
+	}
+	else if (idx == 126) {
+		return 127;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio0 ------------ */
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
+/* --------------------- sifive_uart0 ------------ */
 
-/* From cpu@1 */
-struct __metal_driver_cpu __metal_dt_cpu_1 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller,
-};
 
-/* From cpu@2 */
-struct __metal_driver_cpu __metal_dt_cpu_2 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From cpu@3 */
-struct __metal_driver_cpu __metal_dt_cpu_3 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller,
-};
 
-/* From cpu@4 */
-struct __metal_driver_cpu __metal_dt_cpu_4 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[1] = 11,
-    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[2] = 9,
-    .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[3] = 11,
-    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[4] = 9,
-    .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[5] = 11,
-    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[6] = 9,
-    .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[7] = 11,
-    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[8] = 9,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
-    .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
-    .init_done = 0,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 1,
-    .interrupt_lines[1] = 2,
-    .interrupt_lines[2] = 3,
-    .interrupt_lines[3] = 4,
-    .interrupt_lines[4] = 5,
-    .interrupt_lines[5] = 6,
-    .interrupt_lines[6] = 7,
-    .interrupt_lines[7] = 8,
-    .interrupt_lines[8] = 9,
-    .interrupt_lines[9] = 10,
-    .interrupt_lines[10] = 11,
-    .interrupt_lines[11] = 12,
-    .interrupt_lines[12] = 13,
-    .interrupt_lines[13] = 14,
-    .interrupt_lines[14] = 15,
-    .interrupt_lines[15] = 16,
-    .interrupt_lines[16] = 17,
-    .interrupt_lines[17] = 18,
-    .interrupt_lines[18] = 19,
-    .interrupt_lines[19] = 20,
-    .interrupt_lines[20] = 21,
-    .interrupt_lines[21] = 22,
-    .interrupt_lines[22] = 23,
-    .interrupt_lines[23] = 24,
-    .interrupt_lines[24] = 25,
-    .interrupt_lines[25] = 26,
-    .interrupt_lines[26] = 27,
-    .interrupt_lines[27] = 28,
-    .interrupt_lines[28] = 29,
-    .interrupt_lines[29] = 30,
-    .interrupt_lines[30] = 31,
-    .interrupt_lines[31] = 32,
-    .interrupt_lines[32] = 33,
-    .interrupt_lines[33] = 34,
-    .interrupt_lines[34] = 35,
-    .interrupt_lines[35] = 36,
-    .interrupt_lines[36] = 37,
-    .interrupt_lines[37] = 38,
-    .interrupt_lines[38] = 39,
-    .interrupt_lines[39] = 40,
-    .interrupt_lines[40] = 41,
-    .interrupt_lines[41] = 42,
-    .interrupt_lines[42] = 43,
-    .interrupt_lines[43] = 44,
-    .interrupt_lines[44] = 45,
-    .interrupt_lines[45] = 46,
-    .interrupt_lines[46] = 47,
-    .interrupt_lines[47] = 48,
-    .interrupt_lines[48] = 49,
-    .interrupt_lines[49] = 50,
-    .interrupt_lines[50] = 51,
-    .interrupt_lines[51] = 52,
-    .interrupt_lines[52] = 53,
-    .interrupt_lines[53] = 54,
-    .interrupt_lines[54] = 55,
-    .interrupt_lines[55] = 56,
-    .interrupt_lines[56] = 57,
-    .interrupt_lines[57] = 58,
-    .interrupt_lines[58] = 59,
-    .interrupt_lines[59] = 60,
-    .interrupt_lines[60] = 61,
-    .interrupt_lines[61] = 62,
-    .interrupt_lines[62] = 63,
-    .interrupt_lines[63] = 64,
-    .interrupt_lines[64] = 65,
-    .interrupt_lines[65] = 66,
-    .interrupt_lines[66] = 67,
-    .interrupt_lines[67] = 68,
-    .interrupt_lines[68] = 69,
-    .interrupt_lines[69] = 70,
-    .interrupt_lines[70] = 71,
-    .interrupt_lines[71] = 72,
-    .interrupt_lines[72] = 73,
-    .interrupt_lines[73] = 74,
-    .interrupt_lines[74] = 75,
-    .interrupt_lines[75] = 76,
-    .interrupt_lines[76] = 77,
-    .interrupt_lines[77] = 78,
-    .interrupt_lines[78] = 79,
-    .interrupt_lines[79] = 80,
-    .interrupt_lines[80] = 81,
-    .interrupt_lines[81] = 82,
-    .interrupt_lines[82] = 83,
-    .interrupt_lines[83] = 84,
-    .interrupt_lines[84] = 85,
-    .interrupt_lines[85] = 86,
-    .interrupt_lines[86] = 87,
-    .interrupt_lines[87] = 88,
-    .interrupt_lines[88] = 89,
-    .interrupt_lines[89] = 90,
-    .interrupt_lines[90] = 91,
-    .interrupt_lines[91] = 92,
-    .interrupt_lines[92] = 93,
-    .interrupt_lines[93] = 94,
-    .interrupt_lines[94] = 95,
-    .interrupt_lines[95] = 96,
-    .interrupt_lines[96] = 97,
-    .interrupt_lines[97] = 98,
-    .interrupt_lines[98] = 99,
-    .interrupt_lines[99] = 100,
-    .interrupt_lines[100] = 101,
-    .interrupt_lines[101] = 102,
-    .interrupt_lines[102] = 103,
-    .interrupt_lines[103] = 104,
-    .interrupt_lines[104] = 105,
-    .interrupt_lines[105] = 106,
-    .interrupt_lines[106] = 107,
-    .interrupt_lines[107] = 108,
-    .interrupt_lines[108] = 109,
-    .interrupt_lines[109] = 110,
-    .interrupt_lines[110] = 111,
-    .interrupt_lines[111] = 112,
-    .interrupt_lines[112] = 113,
-    .interrupt_lines[113] = 114,
-    .interrupt_lines[114] = 115,
-    .interrupt_lines[115] = 116,
-    .interrupt_lines[116] = 117,
-    .interrupt_lines[117] = 118,
-    .interrupt_lines[118] = 119,
-    .interrupt_lines[119] = 120,
-    .interrupt_lines[120] = 121,
-    .interrupt_lines[121] = 122,
-    .interrupt_lines[122] = 123,
-    .interrupt_lines[123] = 124,
-    .interrupt_lines[124] = 125,
-    .interrupt_lines[125] = 126,
-    .interrupt_lines[126] = 127,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
-    .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2,
-    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 7
@@ -590,7 +950,13 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+/* From cache_controller@2010000 */
+#define __METAL_DT_SIFIVE_FU540_C000_L2_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#define __METAL_DT_CACHE_CONTROLLER_2010000_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#endif /* MACROS_ELSE_COREIP_U54MC_RTL__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* COREIP_U54MC_RTL__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
index 7b1cf8e..2dca5ed 100644
--- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -160,18 +166,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
index 0d12f67..ea7c853 100644
--- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -57,6 +63,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -169,12 +181,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk
index 0fe5f84..e59f66a 100644
--- a/bsp/coreip-u54mc-rtl/settings.mk
+++ b/bsp/coreip-u54mc-rtl/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-11        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imac
 RISCV_ABI=lp64
 RISCV_CMODEL=medany
diff --git a/bsp/freedom-e310-arty/metal-inline.h b/bsp/freedom-e310-arty/metal-inline.h
new file mode 100644
index 0000000..b2f329f
--- /dev/null
+++ b/bsp/freedom-e310-arty/metal-inline.h
@@ -0,0 +1,195 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef FREEDOM_E310_ARTY__METAL_INLINE_H
+#define FREEDOM_E310_ARTY__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_8000000 = {
+    ._base_address = 134217728UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10014000 = {
+    ._base_address = 536870912UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@10012000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From spi@10014000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From serial@10013000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+
+#endif /* FREEDOM_E310_ARTY__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/freedom-e310-arty/metal-platform.h b/bsp/freedom-e310-arty/metal-platform.h
index 7fb01e7..6ef2099 100644
--- a/bsp/freedom-e310-arty/metal-platform.h
+++ b/bsp/freedom-e310-arty/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 #ifndef FREEDOM_E310_ARTY__METAL_PLATFORM_H
 #define FREEDOM_E310_ARTY__METAL_PLATFORM_H
 
@@ -8,7 +14,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -17,9 +25,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -30,7 +42,9 @@
 
 /* From gpio@10012000 */
 #define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268509184UL
 #define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -51,9 +65,30 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@10015000 */
+#define METAL_SIFIVE_PWM0_10015000_BASE_ADDRESS 268521472UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 268521472UL
+#define METAL_SIFIVE_PWM0_10015000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@10014000 */
 #define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 268517376UL
 #define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -75,7 +110,9 @@
 
 /* From serial@10013000 */
 #define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268513280UL
 #define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds
index 4b90f06..d331a7b 100644
--- a/bsp/freedom-e310-arty/metal.default.lds
+++ b/bsp/freedom-e310-arty/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h
index 5a726e0..50c05a4 100644
--- a/bsp/freedom-e310-arty/metal.h
+++ b/bsp/freedom-e310-arty/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef FREEDOM_E310_ARTY__METAL_H
-#define FREEDOM_E310_ARTY__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_FREEDOM_E310_ARTY__METAL_H
+#define MACROS_IF_FREEDOM_E310_ARTY__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_FREEDOM_E310_ARTY__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_FREEDOM_E310_ARTY__METAL_H
+#define MACROS_ELSE_FREEDOM_E310_ARTY__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -72,213 +83,524 @@
 #include <metal/drivers/sifive,uart0.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_itim_8000000");
 struct metal_memory __metal_dt_mem_itim_8000000;
 
-asm (".weak __metal_dt_mem_spi_10014000");
 struct metal_memory __metal_dt_mem_spi_10014000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From gpio@10012000 */
-asm (".weak __metal_dt_gpio_10012000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000;
 
 /* From spi@10014000 */
-asm (".weak __metal_dt_spi_10014000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000;
 
 /* From serial@10013000 */
-asm (".weak __metal_dt_serial_10013000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_8000000 = {
-    ._base_address = 134217728UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10014000 = {
-    ._base_address = 536870912UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_SIFIVE_GPIO0_10012000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 0)) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 1))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 2))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 3))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 4))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 5))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 6))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 7))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 8))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 9))) {
+		return 16;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 10))) {
+		return 17;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 11))) {
+		return 18;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 12))) {
+		return 19;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 13))) {
+		return 20;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 14))) {
+		return 21;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 15))) {
+		return 22;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10014000) {
+		return METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10014000) {
+		return METAL_SIFIVE_SPI0_10014000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_SIFIVE_UART0_10013000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_SIFIVE_UART0_10013000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 5;
+}
 
-/* From gpio@10012000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 7,
-    .interrupt_lines[1] = 8,
-    .interrupt_lines[2] = 9,
-    .interrupt_lines[3] = 10,
-    .interrupt_lines[4] = 11,
-    .interrupt_lines[5] = 12,
-    .interrupt_lines[6] = 13,
-    .interrupt_lines[7] = 14,
-    .interrupt_lines[8] = 15,
-    .interrupt_lines[9] = 16,
-    .interrupt_lines[10] = 17,
-    .interrupt_lines[11] = 18,
-    .interrupt_lines[12] = 19,
-    .interrupt_lines[13] = 20,
-    .interrupt_lines[14] = 21,
-    .interrupt_lines[15] = 22,
-};
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
 
-/* From spi@10014000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
-    .clock = NULL,
-    .pinmux = NULL,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return (struct __metal_driver_sifive_gpio0 *)&__metal_dt_gpio_10012000;
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 196608;
+}
 
-/* From serial@10013000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
-/* From clock@0 */
-    .clock = &__metal_dt_clock_0.clock,
-/* From gpio@10012000 */
-    .pinmux = &__metal_dt_gpio_10012000,
-    .pinmux_output_selector = 196608UL,
-    .pinmux_source_selector = 196608UL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 5UL,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 196608;
+}
+
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- sifive_fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 3
@@ -344,7 +666,8 @@ asm (".weak __metal_spi_table");
 struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 					&__metal_dt_spi_10014000};
 
+#endif /* MACROS_ELSE_FREEDOM_E310_ARTY__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* FREEDOM_E310_ARTY__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds
index b24d83f..ee6ae00 100644
--- a/bsp/freedom-e310-arty/metal.ramrodata.lds
+++ b/bsp/freedom-e310-arty/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds
index 711bc3c..5a6d82d 100644
--- a/bsp/freedom-e310-arty/metal.scratchpad.lds
+++ b/bsp/freedom-e310-arty/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk
index 0b9c2cb..6307e3a 100644
--- a/bsp/freedom-e310-arty/settings.mk
+++ b/bsp/freedom-e310-arty/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-11        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h
new file mode 100644
index 0000000..6968bab
--- /dev/null
+++ b/bsp/sifive-hifive-unleashed/metal-inline.h
@@ -0,0 +1,345 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_INLINE_H
+#define SIFIVE_HIFIVE_UNLEASHED__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+extern inline struct metal_clock * __metal_driver_fixed_factor_clock_parent(struct metal_clock *clock);
+extern inline unsigned long __metal_driver_fixed_factor_clock_mult(struct metal_clock *clock);
+extern inline unsigned long __metal_driver_fixed_factor_clock_div(struct metal_clock *clock);
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+extern inline unsigned long __metal_driver_sifive_test0_base( );
+extern inline unsigned long __metal_driver_sifive_test0_size( );
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+
+
+/* --------------------- fe310_g000_prci ------------ */
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From refclk */
+struct __metal_driver_fixed_clock __metal_dt_refclk = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+/* From tlclk */
+struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = {
+    .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_1000000 = {
+    ._base_address = 16777216UL,
+    ._size = 8192UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1800000 = {
+    ._base_address = 25165824UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1808000 = {
+    ._base_address = 25198592UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1810000 = {
+    ._base_address = 25231360UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1818000 = {
+    ._base_address = 25264128UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_itim_1820000 = {
+    ._base_address = 25296896UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_memory_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 135291469824UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10040000 = {
+    ._base_address = 536870912UL,
+    ._size = 268435456UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10041000 = {
+    ._base_address = 805306368UL,
+    ._size = 268435456UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10050000 = {
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@1 */
+struct __metal_driver_cpu __metal_dt_cpu_1 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@2 */
+struct __metal_driver_cpu __metal_dt_cpu_2 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@3 */
+struct __metal_driver_cpu __metal_dt_cpu_3 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From cpu@4 */
+struct __metal_driver_cpu __metal_dt_cpu_4 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From gpio@10060000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From spi@10040000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From spi@10041000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From spi@10050000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From teststatus@4000 */
+struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
+/* From serial@10010000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+/* From serial@10011000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+/* From cache_controller@2010000 */
+struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
+    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
+};
+
+
+#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h
index db4360e..0a1d909 100644
--- a/bsp/sifive-hifive-unleashed/metal-platform.h
+++ b/bsp/sifive-hifive-unleashed/metal-platform.h
@@ -3,18 +3,23 @@
 
 /* From refclk */
 #define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 33333333UL
 
 #define METAL_FIXED_CLOCK
 
 /* From tlclk */
 #define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL
+#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_DIV 2UL
 #define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL
+#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_MULT 1UL
 
 #define METAL_FIXED_FACTOR_CLOCK
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -23,9 +28,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 54UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 54UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -36,12 +45,25 @@
 
 /* From pmp@0 */
 #define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
+#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
 
 #define METAL_RISCV_PMP
 
+/* From cache_controller@2010000 */
+#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
+#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL
+#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL
+
+#define METAL_SIFIVE_FU540_C000_L2
+#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL
+#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL
+
 /* From gpio@10060000 */
 #define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268828672UL
 #define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -62,17 +84,59 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From i2c@10030000 */
+#define METAL_SIFIVE_I2C0_10030000_BASE_ADDRESS 268632064UL
+#define METAL_SIFIVE_I2C0_0_BASE_ADDRESS 268632064UL
+#define METAL_SIFIVE_I2C0_10030000_SIZE 4096UL
+#define METAL_SIFIVE_I2C0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_I2C0
+#define METAL_SIFIVE_I2C0_PRESCALE_LOW 0UL
+#define METAL_SIFIVE_I2C0_PRESCALE_HIGH 4UL
+#define METAL_SIFIVE_I2C0_CONTROL 8UL
+#define METAL_SIFIVE_I2C0_TRANSMIT 12UL
+#define METAL_SIFIVE_I2C0_RECEIVE 12UL
+#define METAL_SIFIVE_I2C0_COMMAND 16UL
+#define METAL_SIFIVE_I2C0_STATUS 16UL
+
+/* From pwm@10020000 */
+#define METAL_SIFIVE_PWM0_10020000_BASE_ADDRESS 268566528UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 268566528UL
+#define METAL_SIFIVE_PWM0_10020000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+/* From pwm@10021000 */
+#define METAL_SIFIVE_PWM0_10021000_BASE_ADDRESS 268570624UL
+#define METAL_SIFIVE_PWM0_1_BASE_ADDRESS 268570624UL
+#define METAL_SIFIVE_PWM0_10021000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_1_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@10040000 */
 #define METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS 268697600UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 268697600UL
 #define METAL_SIFIVE_SPI0_10040000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 /* From spi@10041000 */
 #define METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS 268701696UL
+#define METAL_SIFIVE_SPI0_1_BASE_ADDRESS 268701696UL
 #define METAL_SIFIVE_SPI0_10041000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_1_SIZE 4096UL
 
 /* From spi@10050000 */
 #define METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS 268763136UL
+#define METAL_SIFIVE_SPI0_2_BASE_ADDRESS 268763136UL
 #define METAL_SIFIVE_SPI0_10050000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_2_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -94,18 +158,24 @@
 
 /* From teststatus@4000 */
 #define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
 #define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_TEST0
 #define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
 
 /* From serial@10010000 */
 #define METAL_SIFIVE_UART0_10010000_BASE_ADDRESS 268500992UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268500992UL
 #define METAL_SIFIVE_UART0_10010000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 /* From serial@10011000 */
 #define METAL_SIFIVE_UART0_10011000_BASE_ADDRESS 268505088UL
+#define METAL_SIFIVE_UART0_1_BASE_ADDRESS 268505088UL
 #define METAL_SIFIVE_UART0_10011000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_1_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds
index 61b2203..b4c68be 100644
--- a/bsp/sifive-hifive-unleashed/metal.default.lds
+++ b/bsp/sifive-hifive-unleashed/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h
index 118bdd3..e72a3db 100644
--- a/bsp/sifive-hifive-unleashed/metal.h
+++ b/bsp/sifive-hifive-unleashed/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H
-#define SIFIVE_HIFIVE_UNLEASHED__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+#define MACROS_IF_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 10
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_SIFIVE_HIFIVE_UNLEASHED__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+#define MACROS_ELSE_SIFIVE_HIFIVE_UNLEASHED__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 10
 
 #define METAL_MAX_CLINT_INTERRUPTS 10
@@ -74,495 +85,655 @@
 #include <metal/drivers/sifive,fu540-c000,l2.h>
 
 /* From refclk */
-asm (".weak __metal_dt_refclk");
 struct __metal_driver_fixed_clock __metal_dt_refclk;
 
 /* From tlclk */
-asm (".weak __metal_dt_tlclk");
 struct __metal_driver_fixed_factor_clock __metal_dt_tlclk;
 
-asm (".weak __metal_dt_mem_dtim_1000000");
 struct metal_memory __metal_dt_mem_dtim_1000000;
 
-asm (".weak __metal_dt_mem_itim_1800000");
 struct metal_memory __metal_dt_mem_itim_1800000;
 
-asm (".weak __metal_dt_mem_itim_1808000");
 struct metal_memory __metal_dt_mem_itim_1808000;
 
-asm (".weak __metal_dt_mem_itim_1810000");
 struct metal_memory __metal_dt_mem_itim_1810000;
 
-asm (".weak __metal_dt_mem_itim_1818000");
 struct metal_memory __metal_dt_mem_itim_1818000;
 
-asm (".weak __metal_dt_mem_itim_1820000");
 struct metal_memory __metal_dt_mem_itim_1820000;
 
-asm (".weak __metal_dt_mem_memory_80000000");
 struct metal_memory __metal_dt_mem_memory_80000000;
 
-asm (".weak __metal_dt_mem_spi_10040000");
 struct metal_memory __metal_dt_mem_spi_10040000;
 
-asm (".weak __metal_dt_mem_spi_10041000");
 struct metal_memory __metal_dt_mem_spi_10041000;
 
-asm (".weak __metal_dt_mem_spi_10050000");
 struct metal_memory __metal_dt_mem_spi_10050000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
 /* From cpu@1 */
-asm (".weak __metal_dt_cpu_1");
 struct __metal_driver_cpu __metal_dt_cpu_1;
 
 /* From cpu@2 */
-asm (".weak __metal_dt_cpu_2");
 struct __metal_driver_cpu __metal_dt_cpu_2;
 
 /* From cpu@3 */
-asm (".weak __metal_dt_cpu_3");
 struct __metal_driver_cpu __metal_dt_cpu_3;
 
 /* From cpu@4 */
-asm (".weak __metal_dt_cpu_4");
 struct __metal_driver_cpu __metal_dt_cpu_4;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_1_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_2_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_3_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller;
 
-asm (".weak __metal_dt_cpu_4_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From gpio@10060000 */
-asm (".weak __metal_dt_gpio_10060000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000;
 
 /* From spi@10040000 */
-asm (".weak __metal_dt_spi_10040000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000;
 
 /* From spi@10041000 */
-asm (".weak __metal_dt_spi_10041000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000;
 
 /* From spi@10050000 */
-asm (".weak __metal_dt_spi_10050000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000;
 
 /* From teststatus@4000 */
-asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 /* From serial@10010000 */
-asm (".weak __metal_dt_serial_10010000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000;
 
 /* From serial@10011000 */
-asm (".weak __metal_dt_serial_10011000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000;
 
 /* From cache_controller@2010000 */
-asm (".weak __metal_dt_cache_controller_2010000");
 struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
 
 
-/* From refclk */
-struct __metal_driver_fixed_clock __metal_dt_refclk = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
-};
 
-/* From tlclk */
-struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = {
-    .vtable = &__metal_driver_vtable_fixed_factor_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock,
-/* From refclk */
-    .parent = &__metal_dt_refclk.clock,
-    .mult = METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT,
-    .div = METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV,
-};
-
-struct metal_memory __metal_dt_mem_dtim_1000000 = {
-    ._base_address = 16777216UL,
-    ._size = 8192UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1800000 = {
-    ._base_address = 25165824UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1808000 = {
-    ._base_address = 25198592UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1810000 = {
-    ._base_address = 25231360UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1818000 = {
-    ._base_address = 25264128UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1820000 = {
-    ._base_address = 25296896UL,
-    ._size = 32768UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 135291469824UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10040000 = {
-    ._base_address = 536870912UL,
-    ._size = 268435456UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10041000 = {
-    ._base_address = 805306368UL,
-    ._size = 268435456UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10050000 = {
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_refclk) {
+		return METAL_FIXED_CLOCK__CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+static inline struct metal_clock * __metal_driver_fixed_factor_clock_parent(struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_refclk.clock;
+}
+
+static inline unsigned long __metal_driver_fixed_factor_clock_mult(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_tlclk) {
+		return METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_fixed_factor_clock_div(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_tlclk) {
+		return METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 2) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 3) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 4) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 5) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 6) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 7) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 8) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else if (idx == 9) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else if (idx == 2) {
+		return 3;
+	}
+	else if (idx == 3) {
+		return 7;
+	}
+	else if (idx == 4) {
+		return 3;
+	}
+	else if (idx == 5) {
+		return 7;
+	}
+	else if (idx == 6) {
+		return 3;
+	}
+	else if (idx == 7) {
+		return 7;
+	}
+	else if (idx == 8) {
+		return 3;
+	}
+	else if (idx == 9) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+		return 1000000;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+		return &__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+		return &__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+		return &__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 2) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
+	}
+	else if (idx == 3) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 4) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
+	}
+	else if (idx == 5) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 6) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
+	}
+	else if (idx == 7) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else if (idx == 8) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 1) {
+		return 11;
+	}
+	else if (idx == 2) {
+		return 9;
+	}
+	else if (idx == 3) {
+		return 11;
+	}
+	else if (idx == 4) {
+		return 9;
+	}
+	else if (idx == 5) {
+		return 11;
+	}
+	else if (idx == 6) {
+		return 9;
+	}
+	else if (idx == 7) {
+		return 11;
+	}
+	else if (idx == 8) {
+		return 9;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_SIFIVE_GPIO0_10060000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 0)) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 1))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 2))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 3))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 4))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 5))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 6))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 7))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 8))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 9))) {
+		return 16;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 10))) {
+		return 17;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 11))) {
+		return 18;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 12))) {
+		return 19;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 13))) {
+		return 20;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 14))) {
+		return 21;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10060000) && (idx == 15))) {
+		return 22;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10040000) {
+		return METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10040000) {
+		return METAL_SIFIVE_SPI0_10040000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return NULL;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 0;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+static inline unsigned long __metal_driver_sifive_test0_base( )
+{
+		return 16384;
+}
+
+static inline unsigned long __metal_driver_sifive_test0_size( )
+{
+		return 4096;
+}
+
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return METAL_SIFIVE_UART0_10010000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return METAL_SIFIVE_UART0_10010000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[2] = 3,
-    .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[3] = 7,
-    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[4] = 3,
-    .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[5] = 7,
-    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[6] = 3,
-    .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[7] = 7,
-    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[8] = 3,
-    .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[9] = 7,
-};
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10010000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
 
-/* From cpu@1 */
-struct __metal_driver_cpu __metal_dt_cpu_1 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller,
-};
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 4;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_tlclk.clock;
+}
 
-/* From cpu@2 */
-struct __metal_driver_cpu __metal_dt_cpu_2 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller,
-};
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return NULL;
+}
 
-/* From cpu@3 */
-struct __metal_driver_cpu __metal_dt_cpu_3 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From cpu@4 */
-struct __metal_driver_cpu __metal_dt_cpu_4 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 0;
+}
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[1] = 11,
-    .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller,
-    .interrupt_lines[2] = 9,
-    .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[3] = 11,
-    .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller,
-    .interrupt_lines[4] = 9,
-    .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[5] = 11,
-    .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller,
-    .interrupt_lines[6] = 9,
-    .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[7] = 11,
-    .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
-    .interrupt_lines[8] = 9,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
 
-/* From gpio@10060000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 7,
-    .interrupt_lines[1] = 8,
-    .interrupt_lines[2] = 9,
-    .interrupt_lines[3] = 10,
-    .interrupt_lines[4] = 11,
-    .interrupt_lines[5] = 12,
-    .interrupt_lines[6] = 13,
-    .interrupt_lines[7] = 14,
-    .interrupt_lines[8] = 15,
-    .interrupt_lines[9] = 16,
-    .interrupt_lines[10] = 17,
-    .interrupt_lines[11] = 18,
-    .interrupt_lines[12] = 19,
-    .interrupt_lines[13] = 20,
-    .interrupt_lines[14] = 21,
-    .interrupt_lines[15] = 22,
-};
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
 
-/* From spi@10040000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10040000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
 
-/* From spi@10041000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10041000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
 
-/* From spi@10050000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10050000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-};
 
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
-    .vtable = &__metal_driver_vtable_sifive_test0,
-    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-    .base = 16384UL,
-    .size = 4096UL,
-};
+/* --------------------- sifive_fe310_g000_pll ------------ */
 
-/* From serial@10010000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10010000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10010000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 4UL,
-};
 
-/* From serial@10011000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10011000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10011000_SIZE,
-/* From tlclk */
-    .clock = &__metal_dt_tlclk.clock,
-    .pinmux = NULL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 5UL,
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
 
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
-    .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2,
-    .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 9
@@ -643,7 +814,13 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
 
+/* From cache_controller@2010000 */
+#define __METAL_DT_SIFIVE_FU540_C000_L2_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#define __METAL_DT_CACHE_CONTROLLER_2010000_HANDLE (&__metal_dt_cache_controller_2010000)
+
+#endif /* MACROS_ELSE_SIFIVE_HIFIVE_UNLEASHED__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
index b57aaf7..3301bb0 100644
--- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
+++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
index f145bc7..cf43226 100644
--- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
+++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/sifive-hifive1-revb/metal-inline.h b/bsp/sifive-hifive1-revb/metal-inline.h
new file mode 100644
index 0000000..f159c90
--- /dev/null
+++ b/bsp/sifive-hifive1-revb/metal-inline.h
@@ -0,0 +1,253 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef SIFIVE_HIFIVE1_REVB__METAL_INLINE_H
+#define SIFIVE_HIFIVE1_REVB__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfrosc_ref(const struct metal_clock *clock);
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_base(const struct metal_clock *clock);
+extern inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_vtable(struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_hfrosc_config_offset(const struct metal_clock *clock);
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfxosc_ref(const struct metal_clock *clock);
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfxosc_config_base(const struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_hfxosc_config_offset(const struct metal_clock *clock);
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllsel0(const struct metal_clock *clock);
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllref(const struct metal_clock *clock);
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_config_base( );
+extern inline long __metal_driver_sifive_fe310_g000_pll_config_offset( );
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_divider_base(const struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_pll_divider_offset(const struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_pll_init_rate( );
+
+
+/* --------------------- fe310_g000_prci ------------ */
+extern inline long __metal_driver_sifive_fe310_g000_prci_base( );
+extern inline long __metal_driver_sifive_fe310_g000_prci_size( );
+extern inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_prci_vtable( );
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+/* From clock@2 */
+struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+/* From clock@5 */
+struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10014000 = {
+    ._base_address = 536870912UL,
+    ._size = 500000UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From pmp@0 */
+struct metal_pmp __metal_dt_pmp_0 = {
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@10012000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From spi@10014000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From serial@10013000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+/* From clock@3 */
+struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
+    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc.clock,
+};
+
+/* From clock@1 */
+struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
+    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc.clock,
+};
+
+/* From clock@4 */
+struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
+    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_pll.clock,
+};
+
+/* From prci@10008000 */
+struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
+};
+
+
+#endif /* SIFIVE_HIFIVE1_REVB__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive1-revb/metal-platform.h b/bsp/sifive-hifive1-revb/metal-platform.h
index ae992ff..1353847 100644
--- a/bsp/sifive-hifive1-revb/metal-platform.h
+++ b/bsp/sifive-hifive1-revb/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 #ifndef SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H
 #define SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H
 
@@ -14,7 +20,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -23,9 +31,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -39,9 +51,77 @@
 
 #define METAL_RISCV_PMP
 
+/* From aon@10000000 */
+#define METAL_SIFIVE_AON0_10000000_BASE_ADDRESS 268435456UL
+#define METAL_SIFIVE_AON0_0_BASE_ADDRESS 268435456UL
+#define METAL_SIFIVE_AON0_10000000_SIZE 32768UL
+#define METAL_SIFIVE_AON0_0_SIZE 32768UL
+
+#define METAL_SIFIVE_AON0
+#define METAL_SIFIVE_AON0_WDOGCFG 0UL
+#define METAL_SIFIVE_AON0_WDOGCOUNT 8UL
+#define METAL_SIFIVE_AON0_WDOGS 16UL
+#define METAL_SIFIVE_AON0_WDOGFEED 24UL
+#define METAL_SIFIVE_AON0_WDOGKEY 28UL
+#define METAL_SIFIVE_AON0_WDOGCMP 32UL
+#define METAL_SIFIVE_AON0_RTCCFG 64UL
+#define METAL_SIFIVE_AON0_RTCLO 72UL
+#define METAL_SIFIVE_AON0_RTCHI 72UL
+#define METAL_SIFIVE_AON0_RTCS 80UL
+#define METAL_SIFIVE_AON0_RTCCMP 96UL
+#define METAL_SIFIVE_AON0_LFROSCCFG 112UL
+#define METAL_SIFIVE_AON0_BACKUP0 128UL
+#define METAL_SIFIVE_AON0_BACKUP1 132UL
+#define METAL_SIFIVE_AON0_BACKUP2 136UL
+#define METAL_SIFIVE_AON0_BACKUP3 140UL
+#define METAL_SIFIVE_AON0_BACKUP4 144UL
+#define METAL_SIFIVE_AON0_BACKUP5 148UL
+#define METAL_SIFIVE_AON0_BACKUP6 152UL
+#define METAL_SIFIVE_AON0_BACKUP7 152UL
+#define METAL_SIFIVE_AON0_BACKUP8 160UL
+#define METAL_SIFIVE_AON0_BACKUP9 164UL
+#define METAL_SIFIVE_AON0_BACKUP10 168UL
+#define METAL_SIFIVE_AON0_BACKUP11 172UL
+#define METAL_SIFIVE_AON0_BACKUP12 176UL
+#define METAL_SIFIVE_AON0_BACKUP13 180UL
+#define METAL_SIFIVE_AON0_BACKUP14 184UL
+#define METAL_SIFIVE_AON0_BACKUP15 188UL
+#define METAL_SIFIVE_AON0_BACKUP16 192UL
+#define METAL_SIFIVE_AON0_BACKUP17 196UL
+#define METAL_SIFIVE_AON0_BACKUP18 200UL
+#define METAL_SIFIVE_AON0_BACKUP19 204UL
+#define METAL_SIFIVE_AON0_BACKUP20 208UL
+#define METAL_SIFIVE_AON0_BACKUP21 212UL
+#define METAL_SIFIVE_AON0_BACKUP22 216UL
+#define METAL_SIFIVE_AON0_BACKUP23 220UL
+#define METAL_SIFIVE_AON0_BACKUP24 224UL
+#define METAL_SIFIVE_AON0_BACKUP25 228UL
+#define METAL_SIFIVE_AON0_BACKUP26 232UL
+#define METAL_SIFIVE_AON0_BACKUP27 236UL
+#define METAL_SIFIVE_AON0_BACKUP28 240UL
+#define METAL_SIFIVE_AON0_BACKUP29 244UL
+#define METAL_SIFIVE_AON0_BACKUP30 248UL
+#define METAL_SIFIVE_AON0_BACKUP31 252UL
+#define METAL_SIFIVE_AON0_PMU_WAKEUP_BASE 256UL
+#define METAL_SIFIVE_AON0_PWM_SLEEP_BASE 288UL
+#define METAL_SIFIVE_AON0_PMUIE 320UL
+#define METAL_SIFIVE_AON0_PMUCAUSE 324UL
+#define METAL_SIFIVE_AON0_PMUSLEEP 328UL
+#define METAL_SIFIVE_AON0_PMUKEY 332UL
+
+/* From clock@3 */
+
+#define METAL_SIFIVE_FE310_G000_HFROSC
+
+/* From clock@1 */
+
+#define METAL_SIFIVE_FE310_G000_HFXOSC
+
 /* From prci@10008000 */
 #define METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS 268468224UL
+#define METAL_SIFIVE_FE310_G000_PRCI_0_BASE_ADDRESS 268468224UL
 #define METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE 32768UL
+#define METAL_SIFIVE_FE310_G000_PRCI_0_SIZE 32768UL
 
 #define METAL_SIFIVE_FE310_G000_PRCI
 #define METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG 0UL
@@ -49,9 +129,16 @@
 #define METAL_SIFIVE_FE310_G000_PRCI_PLLCFG 8UL
 #define METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV 12UL
 
+/* From clock@4 */
+#define METAL_SIFIVE_FE310_G000_PLL_4_CLOCK_FREQUENCY 16000000UL
+
+#define METAL_SIFIVE_FE310_G000_PLL
+
 /* From gpio@10012000 */
 #define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268509184UL
 #define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -72,9 +159,53 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From i2c@10016000 */
+#define METAL_SIFIVE_I2C0_10016000_BASE_ADDRESS 268525568UL
+#define METAL_SIFIVE_I2C0_0_BASE_ADDRESS 268525568UL
+#define METAL_SIFIVE_I2C0_10016000_SIZE 4096UL
+#define METAL_SIFIVE_I2C0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_I2C0
+#define METAL_SIFIVE_I2C0_PRESCALE_LOW 0UL
+#define METAL_SIFIVE_I2C0_PRESCALE_HIGH 4UL
+#define METAL_SIFIVE_I2C0_CONTROL 8UL
+#define METAL_SIFIVE_I2C0_TRANSMIT 12UL
+#define METAL_SIFIVE_I2C0_RECEIVE 12UL
+#define METAL_SIFIVE_I2C0_COMMAND 16UL
+#define METAL_SIFIVE_I2C0_STATUS 16UL
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@10015000 */
+#define METAL_SIFIVE_PWM0_10015000_BASE_ADDRESS 268521472UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 268521472UL
+#define METAL_SIFIVE_PWM0_10015000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@10014000 */
 #define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 268517376UL
 #define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -96,7 +227,9 @@
 
 /* From serial@10013000 */
 #define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268513280UL
 #define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds
index 7a08d34..972ba9c 100644
--- a/bsp/sifive-hifive1-revb/metal.default.lds
+++ b/bsp/sifive-hifive1-revb/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h
index 330f08e..baf508e 100644
--- a/bsp/sifive-hifive1-revb/metal.h
+++ b/bsp/sifive-hifive1-revb/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef SIFIVE_HIFIVE1_REVB__METAL_H
-#define SIFIVE_HIFIVE1_REVB__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_SIFIVE_HIFIVE1_REVB__METAL_H
+#define MACROS_IF_SIFIVE_HIFIVE1_REVB__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_SIFIVE_HIFIVE1_REVB__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_SIFIVE_HIFIVE1_REVB__METAL_H
+#define MACROS_ELSE_SIFIVE_HIFIVE1_REVB__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -77,337 +88,690 @@
 #include <metal/drivers/sifive,fe310-g000,prci.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
 /* From clock@2 */
-asm (".weak __metal_dt_clock_2");
 struct __metal_driver_fixed_clock __metal_dt_clock_2;
 
 /* From clock@5 */
-asm (".weak __metal_dt_clock_5");
 struct __metal_driver_fixed_clock __metal_dt_clock_5;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_spi_10014000");
 struct metal_memory __metal_dt_mem_spi_10014000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From gpio@10012000 */
-asm (".weak __metal_dt_gpio_10012000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From spi@10014000 */
-asm (".weak __metal_dt_spi_10014000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000;
 
 /* From serial@10013000 */
-asm (".weak __metal_dt_serial_10013000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000;
 
 /* From clock@3 */
-asm (".weak __metal_dt_clock_3");
 struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3;
 
 /* From clock@1 */
-asm (".weak __metal_dt_clock_1");
 struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1;
 
 /* From clock@4 */
-asm (".weak __metal_dt_clock_4");
 struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4;
 
 /* From prci@10008000 */
-asm (".weak __metal_dt_prci_10008000");
 struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
 
-/* From clock@2 */
-struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_2) {
+		return METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY;
+	}
+	else if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_5) {
+		return METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_SIFIVE_GPIO0_10012000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 0)) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 1))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 2))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 3))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 4))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 5))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 6))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 7))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 8))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 9))) {
+		return 16;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 10))) {
+		return 17;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 11))) {
+		return 18;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 12))) {
+		return 19;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 13))) {
+		return 20;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 14))) {
+		return 21;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 15))) {
+		return 22;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10012000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10012000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10012000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 22;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 19;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 21;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10014000) {
+		return METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10014000) {
+		return METAL_SIFIVE_SPI0_10014000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return (struct metal_clock *)&__metal_dt_clock_4.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return (struct __metal_driver_sifive_gpio0 *)&__metal_dt_gpio_10012000;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 60;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 60;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_SIFIVE_UART0_10013000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_SIFIVE_UART0_10013000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 5;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_4.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return (struct __metal_driver_sifive_gpio0 *)&__metal_dt_gpio_10012000;
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 196608;
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 196608;
+}
+
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfrosc_ref(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_2.clock;
+}
+
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_base(const struct metal_clock *clock)
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
+
+static inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_vtable(struct metal_clock *clock)
+{
+		return &__metal_driver_vtable_sifive_fe310_g000_prci;
+}
+
+static inline long __metal_driver_sifive_fe310_g000_hfrosc_config_offset(const struct metal_clock *clock)
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG;
+}
+
 
-/* From clock@5 */
-struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10014000 = {
-    ._base_address = 536870912UL,
-    ._size = 500000UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfxosc_ref(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
+
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfxosc_config_base(const struct metal_clock *clock)
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
+
+static inline long __metal_driver_sifive_fe310_g000_hfxosc_config_offset(const struct metal_clock *clock)
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG;
+}
+
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllsel0(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_3.clock;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllref(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_1.clock;
+}
+
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_divider_base(const struct metal_clock *clock)
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+static inline long __metal_driver_sifive_fe310_g000_pll_divider_offset(const struct metal_clock *clock)
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV;
+}
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_config_base( )
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
+static inline long __metal_driver_sifive_fe310_g000_pll_config_offset( )
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_PLLCFG;
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
+static inline long __metal_driver_sifive_fe310_g000_pll_init_rate( )
+{
+		return 16000000;
+}
 
-/* From gpio@10012000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 7,
-    .interrupt_lines[1] = 8,
-    .interrupt_lines[2] = 9,
-    .interrupt_lines[3] = 10,
-    .interrupt_lines[4] = 11,
-    .interrupt_lines[5] = 12,
-    .interrupt_lines[6] = 13,
-    .interrupt_lines[7] = 14,
-    .interrupt_lines[8] = 15,
-    .interrupt_lines[9] = 16,
-    .interrupt_lines[10] = 17,
-    .interrupt_lines[11] = 18,
-    .interrupt_lines[12] = 19,
-    .interrupt_lines[13] = 20,
-    .interrupt_lines[14] = 21,
-    .interrupt_lines[15] = 22,
-};
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10012000 */
-    .gpio = &__metal_dt_gpio_10012000,
-    .pin = 22UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10012000 */
-    .gpio = &__metal_dt_gpio_10012000,
-    .pin = 19UL,
-    .label = "LD0green",
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
+static inline long __metal_driver_sifive_fe310_g000_prci_base( )
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS;
+}
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10012000 */
-    .gpio = &__metal_dt_gpio_10012000,
-    .pin = 21UL,
-    .label = "LD0blue",
-};
+static inline long __metal_driver_sifive_fe310_g000_prci_size( )
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE;
+}
 
-/* From spi@10014000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
-/* From clock@4 */
-    .clock = &__metal_dt_clock_4.clock,
-/* From gpio@10012000 */
-    .pinmux = &__metal_dt_gpio_10012000,
-    .pinmux_output_selector = 60UL,
-    .pinmux_source_selector = 60UL,
-};
+static inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_prci_vtable( )
+{
+		return &__metal_driver_vtable_sifive_fe310_g000_prci;
+}
 
-/* From serial@10013000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
-/* From clock@4 */
-    .clock = &__metal_dt_clock_4.clock,
-/* From gpio@10012000 */
-    .pinmux = &__metal_dt_gpio_10012000,
-    .pinmux_output_selector = 196608UL,
-    .pinmux_source_selector = 196608UL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 5UL,
-};
 
-/* From clock@3 */
-struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc,
-    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc.clock,
-/* From clock@2 */
-    .ref = &__metal_dt_clock_2.clock,
-/* From prci@10008000 */
-    .config_base = &__metal_dt_prci_10008000,
-    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG,
-};
 
-/* From clock@1 */
-struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc,
-    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc.clock,
-/* From clock@0 */
-    .ref = &__metal_dt_clock_0.clock,
-/* From prci@10008000 */
-    .config_base = &__metal_dt_prci_10008000,
-    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG,
-};
-
-/* From clock@4 */
-struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_pll,
-    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_pll.clock,
-/* From clock@3 */
-    .pllsel0 = &__metal_dt_clock_3.clock,
-/* From clock@1 */
-    .pllref = &__metal_dt_clock_1.clock,
-/* From prci@10008000 */
-    .divider_base = &__metal_dt_prci_10008000,
-    .divider_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV,
-/* From prci@10008000 */
-    .config_base = &__metal_dt_prci_10008000,
-    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLCFG,
-    .init_rate = 16000000UL,
-};
-
-/* From prci@10008000 */
-struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_prci,
-    .base = METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 2
@@ -483,7 +847,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_CLOCK_4_HANDLE (&__metal_dt_clock_4)
 
+#endif /* MACROS_ELSE_SIFIVE_HIFIVE1_REVB__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* SIFIVE_HIFIVE1_REVB__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds
index cf49d3b..558b219 100644
--- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds
+++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds
index 8ab46ed..05948a2 100644
--- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds
+++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk
index 4c1f33e..442f2d3 100644
--- a/bsp/sifive-hifive1-revb/settings.mk
+++ b/bsp/sifive-hifive1-revb/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-11        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
diff --git a/bsp/sifive-hifive1/metal-inline.h b/bsp/sifive-hifive1/metal-inline.h
new file mode 100644
index 0000000..117bff9
--- /dev/null
+++ b/bsp/sifive-hifive1/metal-inline.h
@@ -0,0 +1,248 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
+#ifndef ASSEMBLY
+
+#ifndef SIFIVE_HIFIVE1__METAL_INLINE_H
+#define SIFIVE_HIFIVE1__METAL_INLINE_H
+
+#include <metal/machine.h>
+
+
+/* --------------------- fixed_clock ------------ */
+extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock);
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
+extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+
+
+/* --------------------- sifive_plic0 ------------ */
+extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
+extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
+extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
+extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+extern inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
+extern inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+extern inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio);
+extern inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio);
+extern inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio);
+extern inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx);
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+extern inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led);
+extern inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led);
+extern inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led);
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+extern inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi);
+extern inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi);
+
+
+/* --------------------- sifive_test0 ------------ */
+
+
+/* --------------------- sifive_uart0 ------------ */
+extern inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart);
+extern inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart);
+extern inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart);
+extern inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart);
+extern inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart);
+extern inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart);
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfrosc_ref(const struct metal_clock *clock);
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_base(const struct metal_clock *clock);
+extern inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_vtable(struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_hfrosc_config_offset(const struct metal_clock *clock);
+
+
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfxosc_ref(const struct metal_clock *clock);
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfxosc_config_base(const struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_hfxosc_config_offset(const struct metal_clock *clock);
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllsel0(const struct metal_clock *clock);
+extern inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllref(const struct metal_clock *clock);
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_config_base( );
+extern inline long __metal_driver_sifive_fe310_g000_pll_config_offset( );
+extern inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_divider_base(const struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_pll_divider_offset(const struct metal_clock *clock);
+extern inline long __metal_driver_sifive_fe310_g000_pll_init_rate( );
+
+
+/* --------------------- fe310_g000_prci ------------ */
+extern inline long __metal_driver_sifive_fe310_g000_prci_base( );
+extern inline long __metal_driver_sifive_fe310_g000_prci_size( );
+extern inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_prci_vtable( );
+
+
+/* --------------------- sifive_fu540_c000_l2 ------------ */
+
+
+/* From clock@0 */
+struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+/* From clock@2 */
+struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+/* From clock@5 */
+struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
+    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
+};
+
+struct metal_memory __metal_dt_mem_dtim_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 16384UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_spi_10014000 = {
+    ._base_address = 536870912UL,
+    ._size = 536870912UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+/* From clint@2000000 */
+struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
+    .init_done = 0,
+};
+
+/* From cpu@0 */
+struct __metal_driver_cpu __metal_dt_cpu_0 = {
+    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
+};
+
+/* From interrupt_controller */
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
+    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
+    .init_done = 0,
+};
+
+/* From interrupt_controller@c000000 */
+struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
+    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
+    .init_done = 0,
+};
+
+/* From local_external_interrupts_0 */
+struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
+    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
+    .init_done = 0,
+};
+
+/* From gpio@10012000 */
+struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
+    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
+};
+
+/* From led@0red */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0green */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From led@0blue */
+struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
+    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
+};
+
+/* From spi@10014000 */
+struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
+    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
+};
+
+/* From serial@10013000 */
+struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
+    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
+};
+
+/* From clock@3 */
+struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
+    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc.clock,
+};
+
+/* From clock@1 */
+struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
+    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc.clock,
+};
+
+/* From clock@4 */
+struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
+    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_pll.clock,
+};
+
+/* From prci@10008000 */
+struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
+};
+
+
+#endif /* SIFIVE_HIFIVE1__METAL_INLINE_H*/
+#endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive1/metal-platform.h b/bsp/sifive-hifive1/metal-platform.h
index c50e2f9..f63b445 100644
--- a/bsp/sifive-hifive1/metal-platform.h
+++ b/bsp/sifive-hifive1/metal-platform.h
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 #ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H
 #define SIFIVE_HIFIVE1__METAL_PLATFORM_H
 
@@ -14,7 +20,9 @@
 
 /* From clint@2000000 */
 #define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
 #define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+#define METAL_RISCV_CLINT0_0_SIZE 65536UL
 
 #define METAL_RISCV_CLINT0
 #define METAL_RISCV_CLINT0_MSIP_BASE 0UL
@@ -23,9 +31,13 @@
 
 /* From interrupt_controller@c000000 */
 #define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
 #define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
 #define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
 
 #define METAL_RISCV_PLIC0
 #define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
@@ -34,9 +46,77 @@
 #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
 #define METAL_RISCV_PLIC0_CLAIM 2097156UL
 
+/* From aon@10000000 */
+#define METAL_SIFIVE_AON0_10000000_BASE_ADDRESS 268435456UL
+#define METAL_SIFIVE_AON0_0_BASE_ADDRESS 268435456UL
+#define METAL_SIFIVE_AON0_10000000_SIZE 32768UL
+#define METAL_SIFIVE_AON0_0_SIZE 32768UL
+
+#define METAL_SIFIVE_AON0
+#define METAL_SIFIVE_AON0_WDOGCFG 0UL
+#define METAL_SIFIVE_AON0_WDOGCOUNT 8UL
+#define METAL_SIFIVE_AON0_WDOGS 16UL
+#define METAL_SIFIVE_AON0_WDOGFEED 24UL
+#define METAL_SIFIVE_AON0_WDOGKEY 28UL
+#define METAL_SIFIVE_AON0_WDOGCMP 32UL
+#define METAL_SIFIVE_AON0_RTCCFG 64UL
+#define METAL_SIFIVE_AON0_RTCLO 72UL
+#define METAL_SIFIVE_AON0_RTCHI 72UL
+#define METAL_SIFIVE_AON0_RTCS 80UL
+#define METAL_SIFIVE_AON0_RTCCMP 96UL
+#define METAL_SIFIVE_AON0_LFROSCCFG 112UL
+#define METAL_SIFIVE_AON0_BACKUP0 128UL
+#define METAL_SIFIVE_AON0_BACKUP1 132UL
+#define METAL_SIFIVE_AON0_BACKUP2 136UL
+#define METAL_SIFIVE_AON0_BACKUP3 140UL
+#define METAL_SIFIVE_AON0_BACKUP4 144UL
+#define METAL_SIFIVE_AON0_BACKUP5 148UL
+#define METAL_SIFIVE_AON0_BACKUP6 152UL
+#define METAL_SIFIVE_AON0_BACKUP7 152UL
+#define METAL_SIFIVE_AON0_BACKUP8 160UL
+#define METAL_SIFIVE_AON0_BACKUP9 164UL
+#define METAL_SIFIVE_AON0_BACKUP10 168UL
+#define METAL_SIFIVE_AON0_BACKUP11 172UL
+#define METAL_SIFIVE_AON0_BACKUP12 176UL
+#define METAL_SIFIVE_AON0_BACKUP13 180UL
+#define METAL_SIFIVE_AON0_BACKUP14 184UL
+#define METAL_SIFIVE_AON0_BACKUP15 188UL
+#define METAL_SIFIVE_AON0_BACKUP16 192UL
+#define METAL_SIFIVE_AON0_BACKUP17 196UL
+#define METAL_SIFIVE_AON0_BACKUP18 200UL
+#define METAL_SIFIVE_AON0_BACKUP19 204UL
+#define METAL_SIFIVE_AON0_BACKUP20 208UL
+#define METAL_SIFIVE_AON0_BACKUP21 212UL
+#define METAL_SIFIVE_AON0_BACKUP22 216UL
+#define METAL_SIFIVE_AON0_BACKUP23 220UL
+#define METAL_SIFIVE_AON0_BACKUP24 224UL
+#define METAL_SIFIVE_AON0_BACKUP25 228UL
+#define METAL_SIFIVE_AON0_BACKUP26 232UL
+#define METAL_SIFIVE_AON0_BACKUP27 236UL
+#define METAL_SIFIVE_AON0_BACKUP28 240UL
+#define METAL_SIFIVE_AON0_BACKUP29 244UL
+#define METAL_SIFIVE_AON0_BACKUP30 248UL
+#define METAL_SIFIVE_AON0_BACKUP31 252UL
+#define METAL_SIFIVE_AON0_PMU_WAKEUP_BASE 256UL
+#define METAL_SIFIVE_AON0_PWM_SLEEP_BASE 288UL
+#define METAL_SIFIVE_AON0_PMUIE 320UL
+#define METAL_SIFIVE_AON0_PMUCAUSE 324UL
+#define METAL_SIFIVE_AON0_PMUSLEEP 328UL
+#define METAL_SIFIVE_AON0_PMUKEY 332UL
+
+/* From clock@3 */
+
+#define METAL_SIFIVE_FE310_G000_HFROSC
+
+/* From clock@1 */
+
+#define METAL_SIFIVE_FE310_G000_HFXOSC
+
 /* From prci@10008000 */
 #define METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS 268468224UL
+#define METAL_SIFIVE_FE310_G000_PRCI_0_BASE_ADDRESS 268468224UL
 #define METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE 32768UL
+#define METAL_SIFIVE_FE310_G000_PRCI_0_SIZE 32768UL
 
 #define METAL_SIFIVE_FE310_G000_PRCI
 #define METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG 0UL
@@ -44,9 +124,16 @@
 #define METAL_SIFIVE_FE310_G000_PRCI_PLLCFG 8UL
 #define METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV 12UL
 
+/* From clock@4 */
+#define METAL_SIFIVE_FE310_G000_PLL_4_CLOCK_FREQUENCY 16000000UL
+
+#define METAL_SIFIVE_FE310_G000_PLL
+
 /* From gpio@10012000 */
 #define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268509184UL
 #define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_GPIO0
 #define METAL_SIFIVE_GPIO0_VALUE 0UL
@@ -67,9 +154,38 @@
 #define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
 #define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
 
+/* From led@0red */
+
+/* From led@0green */
+
+/* From led@0blue */
+
+#define METAL_SIFIVE_GPIO_LEDS
+
+/* From local_external_interrupts_0 */
+
+#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
+
+/* From pwm@10015000 */
+#define METAL_SIFIVE_PWM0_10015000_BASE_ADDRESS 268521472UL
+#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 268521472UL
+#define METAL_SIFIVE_PWM0_10015000_SIZE 4096UL
+#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_PWM0
+#define METAL_SIFIVE_PWM0_PWMCFG 0UL
+#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
+#define METAL_SIFIVE_PWM0_PWMS 16UL
+#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
+#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
+#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
+#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
+
 /* From spi@10014000 */
 #define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 268517376UL
 #define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_SPI0
 #define METAL_SIFIVE_SPI0_SCKDIV 0UL
@@ -91,7 +207,9 @@
 
 /* From serial@10013000 */
 #define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268513280UL
 #define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+#define METAL_SIFIVE_UART0_0_SIZE 4096UL
 
 #define METAL_SIFIVE_UART0
 #define METAL_SIFIVE_UART0_TXDATA 0UL
diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds
index 3c68d7d..7346fd0 100644
--- a/bsp/sifive-hifive1/metal.default.lds
+++ b/bsp/sifive-hifive1/metal.default.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >flash AT>flash :flash
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h
index 4e96c74..39d733d 100644
--- a/bsp/sifive-hifive1/metal.h
+++ b/bsp/sifive-hifive1/metal.h
@@ -1,12 +1,18 @@
-#ifndef ASSEMBLY
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
 
-#ifndef SIFIVE_HIFIVE1__METAL_H
-#define SIFIVE_HIFIVE1__METAL_H
+#ifndef ASSEMBLY
 
 #include <metal/machine/platform.h>
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef MACROS_IF_SIFIVE_HIFIVE1__METAL_H
+#define MACROS_IF_SIFIVE_HIFIVE1__METAL_H
+
 #define __METAL_CLINT_NUM_PARENTS 2
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -26,8 +32,13 @@
 #define __METAL_CLIC_SUBINTERRUPTS 0
 #endif
 
+#endif /* MACROS_IF_SIFIVE_HIFIVE1__METAL_H*/
+
 #else /* ! __METAL_MACHINE_MACROS */
 
+#ifndef MACROS_ELSE_SIFIVE_HIFIVE1__METAL_H
+#define MACROS_ELSE_SIFIVE_HIFIVE1__METAL_H
+
 #define __METAL_CLINT_2000000_INTERRUPTS 2
 
 #define METAL_MAX_CLINT_INTERRUPTS 2
@@ -77,329 +88,688 @@
 #include <metal/drivers/sifive,fe310-g000,prci.h>
 
 /* From clock@0 */
-asm (".weak __metal_dt_clock_0");
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
 
 /* From clock@2 */
-asm (".weak __metal_dt_clock_2");
 struct __metal_driver_fixed_clock __metal_dt_clock_2;
 
 /* From clock@5 */
-asm (".weak __metal_dt_clock_5");
 struct __metal_driver_fixed_clock __metal_dt_clock_5;
 
-asm (".weak __metal_dt_mem_dtim_80000000");
 struct metal_memory __metal_dt_mem_dtim_80000000;
 
-asm (".weak __metal_dt_mem_spi_10014000");
 struct metal_memory __metal_dt_mem_spi_10014000;
 
 /* From clint@2000000 */
-asm (".weak __metal_dt_clint_2000000");
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
 
 /* From cpu@0 */
-asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-asm (".weak __metal_dt_cpu_0_interrupt_controller");
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 /* From interrupt_controller@c000000 */
-asm (".weak __metal_dt_interrupt_controller_c000000");
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
 /* From local_external_interrupts_0 */
-asm (".weak __metal_dt_local_external_interrupts_0");
 struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0;
 
 /* From gpio@10012000 */
-asm (".weak __metal_dt_gpio_10012000");
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000;
 
 /* From led@0red */
-asm (".weak __metal_dt_led_0red");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0red;
 
 /* From led@0green */
-asm (".weak __metal_dt_led_0green");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0green;
 
 /* From led@0blue */
-asm (".weak __metal_dt_led_0blue");
 struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue;
 
 /* From spi@10014000 */
-asm (".weak __metal_dt_spi_10014000");
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000;
 
 /* From serial@10013000 */
-asm (".weak __metal_dt_serial_10013000");
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000;
 
 /* From clock@3 */
-asm (".weak __metal_dt_clock_3");
 struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3;
 
 /* From clock@1 */
-asm (".weak __metal_dt_clock_1");
 struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1;
 
 /* From clock@4 */
-asm (".weak __metal_dt_clock_4");
 struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4;
 
 /* From prci@10008000 */
-asm (".weak __metal_dt_prci_10008000");
 struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000;
 
 
-/* From clock@0 */
-struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
-};
 
-/* From clock@2 */
-struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY,
-};
+/* --------------------- fixed_clock ------------ */
+static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *clock)
+{
+	if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_0) {
+		return METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY;
+	}
+	else if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_2) {
+		return METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY;
+	}
+	else if ((uintptr_t)clock == (uintptr_t)&__metal_dt_clock_5) {
+		return METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- fixed_factor_clock ------------ */
+
+
+/* --------------------- sifive_clint0 ------------ */
+static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_RISCV_CLINT0_2000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
+		return METAL_MAX_CLINT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 1) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 3;
+	}
+	else if (idx == 1) {
+		return 7;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 1000000;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return &__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+
+
+/* --------------------- sifive_plic0 ------------ */
+static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
+		return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else if (idx == 0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 11;
+	}
+	else if (idx == 0) {
+		return 11;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_clic0 ------------ */
+
+
+/* --------------------- sifive_local_external_interrupts0 ------------ */
+static inline struct metal_interrupt * __metal_driver_sifive_local_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
+{
+	if ((uintptr_t)controller == (uintptr_t)&__metal_dt_local_external_interrupts_0) {
+		return METAL_MAX_LOCAL_EXT_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_local_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
+{
+	if (idx == 0) {
+		return 16;
+	}
+	else if (idx == 1) {
+		return 17;
+	}
+	else if (idx == 2) {
+		return 18;
+	}
+	else if (idx == 3) {
+		return 19;
+	}
+	else if (idx == 4) {
+		return 20;
+	}
+	else if (idx == 5) {
+		return 21;
+	}
+	else if (idx == 6) {
+		return 22;
+	}
+	else if (idx == 7) {
+		return 23;
+	}
+	else if (idx == 8) {
+		return 24;
+	}
+	else if (idx == 9) {
+		return 25;
+	}
+	else if (idx == 10) {
+		return 26;
+	}
+	else if (idx == 11) {
+		return 27;
+	}
+	else if (idx == 12) {
+		return 28;
+	}
+	else if (idx == 13) {
+		return 29;
+	}
+	else if (idx == 14) {
+		return 30;
+	}
+	else if (idx == 15) {
+		return 31;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_global_external_interrupts0 ------------ */
+
+
+/* --------------------- sifive_gpio0 ------------ */
+static inline unsigned long __metal_driver_sifive_gpio0_base(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_gpio0_size(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_SIFIVE_GPIO0_10012000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_num_interrupts(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return METAL_MAX_GPIO_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_gpio0_interrupt_parent(struct metal_gpio *gpio)
+{
+	if ((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio0_interrupt_lines(struct metal_gpio *gpio, int idx)
+{
+	if (((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 0)) {
+		return 7;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 1))) {
+		return 8;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 2))) {
+		return 9;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 3))) {
+		return 10;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 4))) {
+		return 11;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 5))) {
+		return 12;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 6))) {
+		return 13;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 7))) {
+		return 14;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 8))) {
+		return 15;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 9))) {
+		return 16;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 10))) {
+		return 17;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 11))) {
+		return 18;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 12))) {
+		return 19;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 13))) {
+		return 20;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 14))) {
+		return 21;
+	}
+	else if ((((uintptr_t)gpio == (uintptr_t)&__metal_dt_gpio_10012000) && (idx == 15))) {
+		return 22;
+	}
+	else {
+		return 0;
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_button ------------ */
+
+
+/* --------------------- sifive_gpio_led ------------ */
+static inline struct metal_gpio * __metal_driver_sifive_gpio_led_gpio(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10012000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10012000;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return (struct metal_gpio *)&__metal_dt_gpio_10012000;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_gpio_led_pin(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return 22;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return 19;
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return 21;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline char * __metal_driver_sifive_gpio_led_label(struct metal_led *led)
+{
+	if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0red) {
+		return "LD0red";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0green) {
+		return "LD0green";
+	}
+	else if ((uintptr_t)led == (uintptr_t)&__metal_dt_led_0blue) {
+		return "LD0blue";
+	}
+	else {
+		return "";
+	}
+}
+
+
+
+/* --------------------- sifive_gpio_switch ------------ */
+
+
+/* --------------------- sifive_spi0 ------------ */
+static inline unsigned long __metal_driver_sifive_spi0_control_base(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10014000) {
+		return METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_control_size(struct metal_spi *spi)
+{
+	if ((uintptr_t)spi == (uintptr_t)&__metal_dt_spi_10014000) {
+		return METAL_SIFIVE_SPI0_10014000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_clock * __metal_driver_sifive_spi0_clock(struct metal_spi *spi)
+{
+		return (struct metal_clock *)&__metal_dt_clock_4.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_spi0_pinmux(struct metal_spi *spi)
+{
+		return (struct __metal_driver_sifive_gpio0 *)&__metal_dt_gpio_10012000;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_output_selector(struct metal_spi *spi)
+{
+		return 60;
+}
+
+static inline unsigned long __metal_driver_sifive_spi0_pinmux_source_selector(struct metal_spi *spi)
+{
+		return 60;
+}
+
+
+
+/* --------------------- sifive_test0 ------------ */
+
+
+/* --------------------- sifive_uart0 ------------ */
+static inline unsigned long __metal_driver_sifive_uart0_control_base(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_SIFIVE_UART0_10013000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_control_size(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_SIFIVE_UART0_10013000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_num_interrupts(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return METAL_MAX_UART_INTERRUPTS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static inline struct metal_interrupt * __metal_driver_sifive_uart0_interrupt_parent(struct metal_uart *uart)
+{
+	if ((uintptr_t)uart == (uintptr_t)&__metal_dt_serial_10013000) {
+		return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
+	}
+	else {
+		return NULL;
+	}
+}
+
+static inline int __metal_driver_sifive_uart0_interrupt_line(struct metal_uart *uart)
+{
+		return 5;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_uart0_clock(struct metal_uart *uart)
+{
+		return (struct metal_clock *)&__metal_dt_clock_4.clock;
+}
+
+static inline struct __metal_driver_sifive_gpio0 * __metal_driver_sifive_uart0_pinmux(struct metal_uart *uart)
+{
+		return (struct __metal_driver_sifive_gpio0 *)&__metal_dt_gpio_10012000;
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_output_selector(struct metal_uart *uart)
+{
+		return 196608;
+}
+
+static inline unsigned long __metal_driver_sifive_uart0_pinmux_source_selector(struct metal_uart *uart)
+{
+		return 196608;
+}
+
+
+
+/* --------------------- sifive_fe310_g000_hfrosc ------------ */
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfrosc_ref(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_2.clock;
+}
+
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_base(const struct metal_clock *clock)
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
+
+static inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfrosc_config_vtable(struct metal_clock *clock)
+{
+		return &__metal_driver_vtable_sifive_fe310_g000_prci;
+}
+
+static inline long __metal_driver_sifive_fe310_g000_hfrosc_config_offset(const struct metal_clock *clock)
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG;
+}
+
 
-/* From clock@5 */
-struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
-    .vtable = &__metal_driver_vtable_fixed_clock,
-    .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY,
-};
-
-struct metal_memory __metal_dt_mem_dtim_80000000 = {
-    ._base_address = 2147483648UL,
-    ._size = 16384UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_spi_10014000 = {
-    ._base_address = 536870912UL,
-    ._size = 536870912UL,
-    ._attrs = {
-        .R = 1,
-        .W = 1,
-        .X = 1,
-        .C = 1,
-        .A = 1},
-};
 
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
-    .vtable = &__metal_driver_vtable_riscv_clint0,
-    .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
-    .init_done = 0,
-    .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 3,
-    .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[1] = 7,
-};
+/* --------------------- sifive_fe310_g000_hfxosc ------------ */
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_hfxosc_ref(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_0.clock;
+}
+
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_hfxosc_config_base(const struct metal_clock *clock)
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
+
+static inline long __metal_driver_sifive_fe310_g000_hfxosc_config_offset(const struct metal_clock *clock)
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG;
+}
+
+
+
+/* --------------------- sifive_fe310_g000_pll ------------ */
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllsel0(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_3.clock;
+}
+
+static inline struct metal_clock * __metal_driver_sifive_fe310_g000_pll_pllref(const struct metal_clock *clock)
+{
+		return (struct metal_clock *)&__metal_dt_clock_1.clock;
+}
+
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_divider_base(const struct metal_clock *clock)
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
 
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
-    .vtable = &__metal_driver_vtable_cpu,
-    .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-    .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
-    .vtable = &__metal_driver_vtable_riscv_cpu_intc,
-    .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
-    .init_done = 0,
-    .interrupt_controller = 1,
-};
+static inline long __metal_driver_sifive_fe310_g000_pll_divider_offset(const struct metal_clock *clock)
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV;
+}
 
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
-    .vtable = &__metal_driver_vtable_riscv_plic0,
-    .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
-    .init_done = 0,
-    .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .interrupt_lines[0] = 11,
-    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
-    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
-    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
-    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
-    .interrupt_controller = 1,
-};
+static inline struct __metal_driver_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_pll_config_base( )
+{
+		return (struct __metal_driver_sifive_fe310_g000_prci *)&__metal_dt_prci_10008000;
+}
 
-/* From local_external_interrupts_0 */
-struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = {
-    .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0,
-    .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable,
-    .init_done = 0,
-    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
-    .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS,
-    .interrupt_lines[0] = 16,
-    .interrupt_lines[1] = 17,
-    .interrupt_lines[2] = 18,
-    .interrupt_lines[3] = 19,
-    .interrupt_lines[4] = 20,
-    .interrupt_lines[5] = 21,
-    .interrupt_lines[6] = 22,
-    .interrupt_lines[7] = 23,
-    .interrupt_lines[8] = 24,
-    .interrupt_lines[9] = 25,
-    .interrupt_lines[10] = 26,
-    .interrupt_lines[11] = 27,
-    .interrupt_lines[12] = 28,
-    .interrupt_lines[13] = 29,
-    .interrupt_lines[14] = 30,
-    .interrupt_lines[15] = 31,
-};
+static inline long __metal_driver_sifive_fe310_g000_pll_config_offset( )
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_PLLCFG;
+}
 
-/* From gpio@10012000 */
-struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
-    .vtable = &__metal_driver_vtable_sifive_gpio0,
-    .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
-    .interrupt_lines[0] = 7,
-    .interrupt_lines[1] = 8,
-    .interrupt_lines[2] = 9,
-    .interrupt_lines[3] = 10,
-    .interrupt_lines[4] = 11,
-    .interrupt_lines[5] = 12,
-    .interrupt_lines[6] = 13,
-    .interrupt_lines[7] = 14,
-    .interrupt_lines[8] = 15,
-    .interrupt_lines[9] = 16,
-    .interrupt_lines[10] = 17,
-    .interrupt_lines[11] = 18,
-    .interrupt_lines[12] = 19,
-    .interrupt_lines[13] = 20,
-    .interrupt_lines[14] = 21,
-    .interrupt_lines[15] = 22,
-};
+static inline long __metal_driver_sifive_fe310_g000_pll_init_rate( )
+{
+		return 16000000;
+}
 
-/* From led@0red */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10012000 */
-    .gpio = &__metal_dt_gpio_10012000,
-    .pin = 22UL,
-    .label = "LD0red",
-};
 
-/* From led@0green */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10012000 */
-    .gpio = &__metal_dt_gpio_10012000,
-    .pin = 19UL,
-    .label = "LD0green",
-};
 
-/* From led@0blue */
-struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
-    .vtable = &__metal_driver_vtable_sifive_led,
-    .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable,
-/* From gpio@10012000 */
-    .gpio = &__metal_dt_gpio_10012000,
-    .pin = 21UL,
-    .label = "LD0blue",
-};
+/* --------------------- sifive_fe310_g000_prci ------------ */
+static inline long __metal_driver_sifive_fe310_g000_prci_base( )
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS;
+}
 
-/* From spi@10014000 */
-struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
-    .vtable = &__metal_driver_vtable_sifive_spi0,
-    .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
-/* From clock@4 */
-    .clock = &__metal_dt_clock_4.clock,
-/* From gpio@10012000 */
-    .pinmux = &__metal_dt_gpio_10012000,
-    .pinmux_output_selector = 60UL,
-    .pinmux_source_selector = 60UL,
-};
-
-/* From serial@10013000 */
-struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
-    .vtable = &__metal_driver_vtable_sifive_uart0,
-    .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
-    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
-/* From clock@4 */
-    .clock = &__metal_dt_clock_4.clock,
-/* From gpio@10012000 */
-    .pinmux = &__metal_dt_gpio_10012000,
-    .pinmux_output_selector = 196608UL,
-    .pinmux_source_selector = 196608UL,
-/* From interrupt_controller@c000000 */
-    .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
-    .num_interrupts = METAL_MAX_UART_INTERRUPTS,
-    .interrupt_line = 5UL,
-};
+static inline long __metal_driver_sifive_fe310_g000_prci_size( )
+{
+		return METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE;
+}
 
-/* From clock@3 */
-struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc,
-    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc.clock,
-/* From clock@2 */
-    .ref = &__metal_dt_clock_2.clock,
-/* From prci@10008000 */
-    .config_base = &__metal_dt_prci_10008000,
-    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG,
-};
+static inline const struct __metal_driver_vtable_sifive_fe310_g000_prci * __metal_driver_sifive_fe310_g000_prci_vtable( )
+{
+		return &__metal_driver_vtable_sifive_fe310_g000_prci;
+}
 
-/* From clock@1 */
-struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc,
-    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc.clock,
-/* From clock@0 */
-    .ref = &__metal_dt_clock_0.clock,
-/* From prci@10008000 */
-    .config_base = &__metal_dt_prci_10008000,
-    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG,
-};
 
-/* From clock@4 */
-struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_pll,
-    .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_pll.clock,
-/* From clock@3 */
-    .pllsel0 = &__metal_dt_clock_3.clock,
-/* From clock@1 */
-    .pllref = &__metal_dt_clock_1.clock,
-/* From prci@10008000 */
-    .divider_base = &__metal_dt_prci_10008000,
-    .divider_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV,
-/* From prci@10008000 */
-    .config_base = &__metal_dt_prci_10008000,
-    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLCFG,
-    .init_rate = 16000000UL,
-};
 
-/* From prci@10008000 */
-struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
-    .vtable = &__metal_driver_vtable_sifive_fe310_g000_prci,
-    .base = METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS,
-    .size = METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE,
-};
+/* --------------------- sifive_fu540_c000_l2 ------------ */
 
 
 #define __METAL_DT_MAX_MEMORIES 2
@@ -472,7 +842,8 @@ struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 
 #define __METAL_DT_CLOCK_4_HANDLE (&__metal_dt_clock_4)
 
+#endif /* MACROS_ELSE_SIFIVE_HIFIVE1__METAL_H*/
 
 #endif /* ! __METAL_MACHINE_MACROS */
-#endif /* SIFIVE_HIFIVE1__METAL_H*/
+
 #endif /* ! ASSEMBLY */
diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds
index 2f58f9b..00bc224 100644
--- a/bsp/sifive-hifive1/metal.ramrodata.lds
+++ b/bsp/sifive-hifive1/metal.ramrodata.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -161,18 +167,18 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-		PROVIDE( __global_pointer$ = . + 0x800 );
-		*(.sdata .sdata.* .sdata2.*)
-		*(.gnu.linkonce.s.*)
 		. = ALIGN(8);
 		*(.srodata.cst16)
 		*(.srodata.cst8)
 		*(.srodata.cst4)
 		*(.srodata.cst2)
 		*(.srodata .srodata.*)
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+		PROVIDE( __global_pointer$ = . + 0x800 );
+		*(.sdata .sdata.* .sdata2.*)
+		*(.gnu.linkonce.s.*)
 	} >ram AT>flash :ram_init
 
 
diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds
index 80a39b5..7a716d7 100644
--- a/bsp/sifive-hifive1/metal.scratchpad.lds
+++ b/bsp/sifive-hifive1/metal.scratchpad.lds
@@ -1,3 +1,9 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 20-05-2019 14-26-11        */
+/* ----------------------------------- */
+
 OUTPUT_ARCH("riscv")
 
 ENTRY(_enter)
@@ -58,6 +64,12 @@ SECTIONS
 		*(.rdata)
 		*(.rodata .rodata.*)
 		*(.gnu.linkonce.r.*)
+		. = ALIGN(8);
+		*(.srodata.cst16)
+		*(.srodata.cst8)
+		*(.srodata.cst4)
+		*(.srodata.cst2)
+		*(.srodata .srodata.*)
 	} >ram AT>ram :ram
 
 
@@ -170,12 +182,6 @@ SECTIONS
 		PROVIDE( __global_pointer$ = . + 0x800 );
 		*(.sdata .sdata.* .sdata2.*)
 		*(.gnu.linkonce.s.*)
-		. = ALIGN(8);
-		*(.srodata.cst16)
-		*(.srodata.cst8)
-		*(.srodata.cst4)
-		*(.srodata.cst2)
-		*(.srodata .srodata.*)
 	} >ram AT>ram :ram_init
 
 
diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk
index d863a6d..ed70259 100644
--- a/bsp/sifive-hifive1/settings.mk
+++ b/bsp/sifive-hifive1/settings.mk
@@ -1,3 +1,9 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 20-05-2019 14-26-11        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow