diff options
| author | Hsiang-Chia.Huang <hsiangchiah@sifive.com> | 2019-05-22 00:37:14 -0700 |
|---|---|---|
| committer | Hsiang-Chia.Huang <hsiangchiah@sifive.com> | 2019-05-22 19:58:17 -0700 |
| commit | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (patch) | |
| tree | dc9652a6765fefad29d18da1a19645de104d8639 /bsp | |
| parent | 9946f2062837098088e4c9701614a2eeffaa921b (diff) | |
Setup default options for dhrystone release.
Diffstat (limited to 'bsp')
24 files changed, 53 insertions, 23 deletions
diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index 5a405fe..bc4125f 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-09 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imc @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index 6520e6d..26ee991 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-09 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imc @@ -11,3 +11,4 @@ RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index b9be584..3e8ebf8 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index bb8d89a..fd09a82 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -11,3 +11,4 @@ RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 115db75..8f23cea 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -9,3 +9,4 @@ RISCV_ABI=ilp32f RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index 4d6b13e..715b312 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -11,3 +11,4 @@ RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index b9be584..3e8ebf8 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index bb8d89a..fd09a82 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -11,3 +11,4 @@ RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk index 115db75..8f23cea 100644 --- a/bsp/coreip-e34-arty/settings.mk +++ b/bsp/coreip-e34-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -9,3 +9,4 @@ RISCV_ABI=ilp32f RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index 4d6b13e..715b312 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -11,3 +11,4 @@ RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 115db75..8f23cea 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -9,3 +9,4 @@ RISCV_ABI=ilp32f RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index 18bea9e..0ef35b7 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -11,3 +11,4 @@ RISCV_CMODEL=medlow COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 19205af..a18cf05 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv64imac @@ -9,3 +9,4 @@ RISCV_ABI=lp64 RISCV_CMODEL=medany TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index 6af5958..b69debb 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv64imac @@ -11,3 +11,4 @@ RISCV_CMODEL=medany COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index 4ce0f71..1679ade 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv64imafdc @@ -9,3 +9,4 @@ RISCV_ABI=lp64d RISCV_CMODEL=medany TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index c7a4614..7602565 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv64imafdc @@ -11,3 +11,4 @@ RISCV_CMODEL=medany COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index 4ce0f71..a3f9bc1 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv64imafdc @@ -9,3 +9,4 @@ RISCV_ABI=lp64d RISCV_CMODEL=medany TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index c7a4614..7602565 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv64imafdc @@ -11,3 +11,4 @@ RISCV_CMODEL=medany COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk index 6c25a1f..9ae1de9 100644 --- a/bsp/coreip-u54-rtl/settings.mk +++ b/bsp/coreip-u54-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv64imafdc @@ -11,3 +11,4 @@ RISCV_CMODEL=medany COREIP_MEM_WIDTH=128 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk index e59f66a..7da27c4 100644 --- a/bsp/coreip-u54mc-rtl/settings.mk +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv64imac @@ -11,3 +11,4 @@ RISCV_CMODEL=medany COREIP_MEM_WIDTH=128 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index 6307e3a..da84dbc 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/sifive-hifive-unleashed/settings.mk b/bsp/sifive-hifive-unleashed/settings.mk index 38a72d6..07f05fd 100644 --- a/bsp/sifive-hifive-unleashed/settings.mk +++ b/bsp/sifive-hifive-unleashed/settings.mk @@ -1,5 +1,12 @@ +# Copyright 2019 SiFive, Inc # +# SPDX-License-Identifier: Apache-2.0 # +# ----------------------------------- # +# [XXXXX] 22-05-2019 00-09-03 # +# ----------------------------------- # + RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany TARGET_TAGS=board openocd +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index 442f2d3..fbfcb79 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=board jlink +TARGET_DHRY_ITERS=20000000 diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index ed70259..b4b69dc 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 22-05-2019 00-09-03 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=board openocd +TARGET_DHRY_ITERS=20000000 |