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| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-06-05 09:30:32 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-05 09:30:32 +0800 |
| commit | 78b48aac4add3ba3a8a46eafa2b8c8cde065d1f2 (patch) | |
| tree | 529b31e1159e56592621439d1bca1db64da03817 /bsp | |
| parent | f2c7f75ceef24aec9891d75c2b4fb5db5b847868 (diff) | |
| parent | 9ed1c05e3b202ef2ef17cae4bfc0ca6425541d13 (diff) | |
Merge pull request #259 from sifive/coremark_development-19.05
Coremark development 19.05
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/coreip-e20-arty/metal.ramrodata.lds | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds index 513e567..0c6fffa 100644 --- a/bsp/coreip-e20-arty/metal.ramrodata.lds +++ b/bsp/coreip-e20-arty/metal.ramrodata.lds @@ -9,8 +9,9 @@ ENTRY(_enter) MEMORY { - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x8000 flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x1fc00000 + itim (wx!rai) : ORIGIN = 0x80008000, LENGTH = 0x8000 } PHDRS @@ -127,13 +128,17 @@ SECTIONS { . = ALIGN(4); PROVIDE( metal_segment_itim_target_start = . ); - } >ram AT>flash :ram_init + } >itim AT>flash :itim_init .itim : { *(.itim .itim.*) - } >flash AT>flash :flash + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >itim AT>flash :itim_init . = ALIGN(8); @@ -144,8 +149,7 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - *(.itim .itim.*) - } >flash AT>flash :flash + } >itim AT>flash :flash .lalign : |