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authorcgsfv <cgsfv@users.noreply.github.com>2019-06-13 20:36:29 +0200
committercgsfv <cgsfv@users.noreply.github.com>2019-06-13 20:36:29 +0200
commit7ad24f2558984dcf03cf58b6fc90431067e78901 (patch)
treea75fd3086570e51a3c53b429e1ef2a2644a99209 /bsp
parent43c3d481f420f929de1e05dfe7169edd1dbe110b (diff)
Adding ref to matching QEMU repo
Diffstat (limited to 'bsp')
-rw-r--r--bsp/qemu-sifive-e31/README.md2
-rw-r--r--bsp/qemu-sifive-s51/README.md2
2 files changed, 4 insertions, 0 deletions
diff --git a/bsp/qemu-sifive-e31/README.md b/bsp/qemu-sifive-e31/README.md
index 9474b9f..72889b9 100644
--- a/bsp/qemu-sifive-e31/README.md
+++ b/bsp/qemu-sifive-e31/README.md
@@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an
- SPI memory with 1 interrupt line
- Serial port with 1 interrupt line
- 1 RGB LEDS
+
+This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1
diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md
index 64593f3..7825a98 100644
--- a/bsp/qemu-sifive-s51/README.md
+++ b/bsp/qemu-sifive-s51/README.md
@@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an
- SPI memory with 1 interrupt line
- Serial port with 1 interrupt line
- 1 RGB LEDS
+
+This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1