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authormwachs5 <megan@sifive.com>2017-05-05 17:27:24 -0700
committermwachs5 <megan@sifive.com>2017-05-05 17:29:47 -0700
commit7f861d2678aebbccc0a980c497febee0cdd7c025 (patch)
treeefffc8d3564c8d62b4703c81608976d01d76cb86 /bsp
parente5df5013430758db188055eff48f15d1fbd2083d (diff)
coreplex-e51: Correct width of MCAUSE
Diffstat (limited to 'bsp')
-rw-r--r--bsp/env/coreplexip-arty.h2
-rw-r--r--bsp/env/coreplexip-e31-arty/platform.h4
2 files changed, 3 insertions, 3 deletions
diff --git a/bsp/env/coreplexip-arty.h b/bsp/env/coreplexip-arty.h
index 12ff9a6..161da7c 100644
--- a/bsp/env/coreplexip-arty.h
+++ b/bsp/env/coreplexip-arty.h
@@ -97,6 +97,6 @@
#define RTC_FREQ 32768
-void write_hex(int fd, uint32_t hex);
+void write_hex(int fd, long int hex);
#endif /* _SIFIVE_COREPLEXIP_ARTY_H */
diff --git a/bsp/env/coreplexip-e31-arty/platform.h b/bsp/env/coreplexip-e31-arty/platform.h
index 2c9794c..42c8887 100644
--- a/bsp/env/coreplexip-e31-arty/platform.h
+++ b/bsp/env/coreplexip-e31-arty/platform.h
@@ -9,8 +9,8 @@
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x7FFFFFFFUL
#else
-#define MCAUSE_INT 0x80000000000000000UL
-#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFFUL
+#define MCAUSE_INT 0x8000000000000000UL
+#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL
#endif
#define IRQ_M_LOCAL 16