diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-06 21:41:15 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-06 21:41:15 +0000 |
| commit | 87f176dfbbbf1a64bd3e034713434393a0f3518b (patch) | |
| tree | 83596e3e6ed4d1fa832f6771cdee2ee35c070b95 /bsp | |
| parent | c71689996d85011f3d493b8cbe75e1379bdbc932 (diff) | |
| parent | 6aab6996dbd890c5788bf4e330454a3490268174 (diff) | |
Merge pull request #193 from sifive/hifive1-revb
Add support for Segger J-Link OB to HiFive1 Rev B
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/sifive-hifive1-revb/design.dts | 4 | ||||
| -rw-r--r-- | bsp/sifive-hifive1-revb/metal.lds | 2 | ||||
| -rw-r--r-- | bsp/sifive-hifive1-revb/settings.mk | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/bsp/sifive-hifive1-revb/design.dts b/bsp/sifive-hifive1-revb/design.dts index 5f1797d..6c7da04 100644 --- a/bsp/sifive-hifive1-revb/design.dts +++ b/bsp/sifive-hifive1-revb/design.dts @@ -8,7 +8,7 @@ chosen { stdout-path = "/soc/serial@10013000:115200"; - metal,entry = <&spi0 0x100000>; + metal,entry = <&spi0 0x10000>; }; cpus { @@ -180,7 +180,7 @@ compatible = "sifive,spi0"; interrupt-parent = <&plic>; interrupts = <6>; - reg = <0x10014000 0x1000 0x20000000 0x20000000>; + reg = <0x10014000 0x1000 0x20000000 0x7A120>; reg-names = "control", "mem"; clocks = <&hfclk>; pinmux = <&gpio0 0x0003C 0x0003C>; diff --git a/bsp/sifive-hifive1-revb/metal.lds b/bsp/sifive-hifive1-revb/metal.lds index fdd23c7..f7050c4 100644 --- a/bsp/sifive-hifive1-revb/metal.lds +++ b/bsp/sifive-hifive1-revb/metal.lds @@ -5,7 +5,7 @@ ENTRY(_enter) MEMORY { ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000 - flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x20000000 + flash (rxai!w) : ORIGIN = 0x20010000, LENGTH = 0x6a120 } PHDRS diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index d84238b..61e2b02 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,4 +1,4 @@ RISCV_ARCH = rv32imac RISCV_ABI = ilp32 RISCV_CMODEL = medlow -COREIP_MEM_WIDTH = 32 +SEGGER_JLINK_OB = 1 |