summaryrefslogtreecommitdiff
path: root/bsp
diff options
context:
space:
mode:
authorBunnaroath Sou <bsou@sifive.com>2019-03-26 12:07:46 -0700
committerBunnaroath Sou <bsou@sifive.com>2019-03-26 15:13:59 -0700
commit96f7c530cc7ec894ed8c326a47dc496fb7b9c35f (patch)
tree34721983e5e3b6b579f5bee8b0c0ab790f9a5538 /bsp
parentedd89ecddd9abea9fa47b91487bf6bb8360b1c66 (diff)
Making dhrystone public
Diffstat (limited to 'bsp')
-rw-r--r--bsp/coreip-e31-arty/settings.mk2
-rw-r--r--bsp/coreip-e31-rtl/settings.mk2
2 files changed, 2 insertions, 2 deletions
diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk
index 0b9c2cb..c2a2547 100644
--- a/bsp/coreip-e31-arty/settings.mk
+++ b/bsp/coreip-e31-arty/settings.mk
@@ -1,5 +1,5 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
-RISCV_CMODEL=medlow
+RISCV_CMODEL=medany
TARGET_TAGS=fpga openocd
diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk
index f60f250..50ec3c7 100644
--- a/bsp/coreip-e31-rtl/settings.mk
+++ b/bsp/coreip-e31-rtl/settings.mk
@@ -1,6 +1,6 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
-RISCV_CMODEL=medlow
+RISCV_CMODEL=medany
COREIP_MEM_WIDTH=32