Update BSPs for platform header

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

48 files changed, 2061 insertions, 277 deletions

diff --git a/bsp/coreip-e20-arty/metal-platform.h b/bsp/coreip-e20-arty/metal-platform.h
new file mode 100644
index 0000000..e952dd4
--- /dev/null
+++ b/bsp/coreip-e20-arty/metal-platform.h
@@ -0,0 +1,94 @@
+#ifndef COREIP_E20_ARTY__METAL_PLATFORM_H
+#define COREIP_E20_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 58UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_E20_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h
index 8528cc9..0517c64 100644
--- a/bsp/coreip-e20-arty/metal.h
+++ b/bsp/coreip-e20-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E20_ARTY__METAL_H
 #define COREIP_E20_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -163,7 +165,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
@@ -208,17 +210,17 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .vtable = &__metal_driver_vtable_sifive_clic0,
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = 33554432UL,
-    .control_size = 16777216UL,
+    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
     .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
-    .num_subinterrupts = 58UL,
-    .num_intbits = 2UL,
-    .max_levels = 16UL,
+    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
     .interrupt_controller = 1,
 };
 
@@ -282,8 +284,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@2000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -439,8 +441,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -457,8 +459,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h
new file mode 100644
index 0000000..109562d
--- /dev/null
+++ b/bsp/coreip-e20-rtl/metal-platform.h
@@ -0,0 +1,31 @@
+#ifndef COREIP_E20_RTL__METAL_PLATFORM_H
+#define COREIP_E20_RTL__METAL_PLATFORM_H
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 48UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E20_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h
index 094cb45..f031a28 100644
--- a/bsp/coreip-e20-rtl/metal.h
+++ b/bsp/coreip-e20-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E20_RTL__METAL_H
 #define COREIP_E20_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -110,17 +112,17 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .vtable = &__metal_driver_vtable_sifive_clic0,
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = 33554432UL,
-    .control_size = 16777216UL,
+    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
     .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
-    .num_subinterrupts = 48UL,
-    .num_intbits = 2UL,
-    .max_levels = 16UL,
+    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
     .interrupt_controller = 1,
 };
 
diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h
new file mode 100644
index 0000000..3daf97d
--- /dev/null
+++ b/bsp/coreip-e21-arty/metal-platform.h
@@ -0,0 +1,99 @@
+#ifndef COREIP_E21_ARTY__METAL_PLATFORM_H
+#define COREIP_E21_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL
+
+#define METAL_RISCV_PMP
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 153UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_E21_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h
index 56e972a..30fd7ef 100644
--- a/bsp/coreip-e21-arty/metal.h
+++ b/bsp/coreip-e21-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E21_ARTY__METAL_H
 #define COREIP_E21_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -169,7 +171,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
@@ -223,24 +225,24 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 4UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From interrupt_controller@2000000 */
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .vtable = &__metal_driver_vtable_sifive_clic0,
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = 33554432UL,
-    .control_size = 16777216UL,
+    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
     .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
-    .num_subinterrupts = 153UL,
-    .num_intbits = 2UL,
-    .max_levels = 16UL,
+    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
     .interrupt_controller = 1,
 };
 
@@ -399,8 +401,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@2000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -556,8 +558,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -574,8 +576,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-e21-rtl/metal-platform.h b/bsp/coreip-e21-rtl/metal-platform.h
new file mode 100644
index 0000000..9785d80
--- /dev/null
+++ b/bsp/coreip-e21-rtl/metal-platform.h
@@ -0,0 +1,36 @@
+#ifndef COREIP_E21_RTL__METAL_PLATFORM_H
+#define COREIP_E21_RTL__METAL_PLATFORM_H
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 143UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E21_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h
index 7f017fd..d90b0a7 100644
--- a/bsp/coreip-e21-rtl/metal.h
+++ b/bsp/coreip-e21-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E21_RTL__METAL_H
 #define COREIP_E21_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -139,24 +141,24 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From interrupt_controller@2000000 */
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .vtable = &__metal_driver_vtable_sifive_clic0,
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = 33554432UL,
-    .control_size = 16777216UL,
+    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
     .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
-    .num_subinterrupts = 143UL,
-    .num_intbits = 2UL,
-    .max_levels = 16UL,
+    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
     .interrupt_controller = 1,
 };
 
diff --git a/bsp/coreip-e24-arty/metal-platform.h b/bsp/coreip-e24-arty/metal-platform.h
new file mode 100644
index 0000000..c87c0f5
--- /dev/null
+++ b/bsp/coreip-e24-arty/metal-platform.h
@@ -0,0 +1,99 @@
+#ifndef COREIP_E24_ARTY__METAL_PLATFORM_H
+#define COREIP_E24_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL
+
+#define METAL_RISCV_PMP
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 153UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 4UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_E24_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h
index 13a5392..44bb118 100644
--- a/bsp/coreip-e24-arty/metal.h
+++ b/bsp/coreip-e24-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E24_ARTY__METAL_H
 #define COREIP_E24_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -169,7 +171,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
@@ -223,24 +225,24 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 4UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From interrupt_controller@2000000 */
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .vtable = &__metal_driver_vtable_sifive_clic0,
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = 33554432UL,
-    .control_size = 16777216UL,
+    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
     .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
-    .num_subinterrupts = 153UL,
-    .num_intbits = 4UL,
-    .max_levels = 16UL,
+    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
     .interrupt_controller = 1,
 };
 
@@ -399,8 +401,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@2000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -556,8 +558,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -574,8 +576,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-e24-rtl/metal-platform.h b/bsp/coreip-e24-rtl/metal-platform.h
new file mode 100644
index 0000000..c83d491
--- /dev/null
+++ b/bsp/coreip-e24-rtl/metal-platform.h
@@ -0,0 +1,36 @@
+#ifndef COREIP_E24_RTL__METAL_PLATFORM_H
+#define COREIP_E24_RTL__METAL_PLATFORM_H
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 143UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 4UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E24_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h
index bada746..5c8776b 100644
--- a/bsp/coreip-e24-rtl/metal.h
+++ b/bsp/coreip-e24-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E24_RTL__METAL_H
 #define COREIP_E24_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #ifndef __METAL_CLINT_NUM_PARENTS
@@ -139,24 +141,24 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From interrupt_controller@2000000 */
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .vtable = &__metal_driver_vtable_sifive_clic0,
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
-    .control_base = 33554432UL,
-    .control_size = 16777216UL,
+    .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
     .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
-    .num_subinterrupts = 143UL,
-    .num_intbits = 4UL,
-    .max_levels = 16UL,
+    .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+    .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+    .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
     .interrupt_controller = 1,
 };
 
diff --git a/bsp/coreip-e31-arty/metal-platform.h b/bsp/coreip-e31-arty/metal-platform.h
new file mode 100644
index 0000000..21689a3
--- /dev/null
+++ b/bsp/coreip-e31-arty/metal-platform.h
@@ -0,0 +1,101 @@
+#ifndef COREIP_E31_ARTY__METAL_PLATFORM_H
+#define COREIP_E31_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_E31_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h
index f029f9e..10df223 100644
--- a/bsp/coreip-e31-arty/metal.h
+++ b/bsp/coreip-e31-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E31_ARTY__METAL_H
 #define COREIP_E31_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -180,7 +182,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -220,8 +222,8 @@ struct metal_memory __metal_dt_mem_spi_20004000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -253,16 +255,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
@@ -308,8 +310,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -465,8 +467,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -483,8 +485,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-e31-rtl/metal-platform.h b/bsp/coreip-e31-rtl/metal-platform.h
new file mode 100644
index 0000000..d5bf04d
--- /dev/null
+++ b/bsp/coreip-e31-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_E31_RTL__METAL_PLATFORM_H
+#define COREIP_E31_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E31_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h
index b842fff..fe465a9 100644
--- a/bsp/coreip-e31-rtl/metal.h
+++ b/bsp/coreip-e31-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E31_RTL__METAL_H
 #define COREIP_E31_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -143,8 +145,8 @@ struct metal_memory __metal_dt_mem_itim_8000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -176,16 +178,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 128UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
diff --git a/bsp/coreip-e34-arty/metal-platform.h b/bsp/coreip-e34-arty/metal-platform.h
new file mode 100644
index 0000000..76f2494
--- /dev/null
+++ b/bsp/coreip-e34-arty/metal-platform.h
@@ -0,0 +1,101 @@
+#ifndef COREIP_E34_ARTY__METAL_PLATFORM_H
+#define COREIP_E34_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_E34_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h
index 3c79ea5..c5da8fa 100644
--- a/bsp/coreip-e34-arty/metal.h
+++ b/bsp/coreip-e34-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E34_ARTY__METAL_H
 #define COREIP_E34_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -180,7 +182,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -220,8 +222,8 @@ struct metal_memory __metal_dt_mem_spi_20004000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -253,16 +255,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
@@ -308,8 +310,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -465,8 +467,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -483,8 +485,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-e34-rtl/metal-platform.h b/bsp/coreip-e34-rtl/metal-platform.h
new file mode 100644
index 0000000..9b9e13c
--- /dev/null
+++ b/bsp/coreip-e34-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_E34_RTL__METAL_PLATFORM_H
+#define COREIP_E34_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E34_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h
index 89e7f85..4039765 100644
--- a/bsp/coreip-e34-rtl/metal.h
+++ b/bsp/coreip-e34-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E34_RTL__METAL_H
 #define COREIP_E34_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -143,8 +145,8 @@ struct metal_memory __metal_dt_mem_itim_8000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -176,16 +178,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 128UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h
new file mode 100644
index 0000000..f99ea6f
--- /dev/null
+++ b/bsp/coreip-e76-arty/metal-platform.h
@@ -0,0 +1,105 @@
+#ifndef COREIP_E76_ARTY__METAL_PLATFORM_H
+#define COREIP_E76_ARTY__METAL_PLATFORM_H
+
+/* From tlclk */
+#define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 31UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@10060000 */
+#define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_E76_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h
index b384007..7115c2a 100644
--- a/bsp/coreip-e76-arty/metal.h
+++ b/bsp/coreip-e76-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E76_ARTY__METAL_H
 #define COREIP_E76_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -176,7 +178,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_tlclk = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_memory_80000000 = {
@@ -205,8 +207,8 @@ struct metal_memory __metal_dt_mem_spi_20004000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -238,16 +240,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 31UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From global_external_interrupts */
@@ -268,8 +270,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268828672UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -283,8 +285,8 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -440,8 +442,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
@@ -459,8 +461,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h
new file mode 100644
index 0000000..0e9e786
--- /dev/null
+++ b/bsp/coreip-e76-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_E76_RTL__METAL_PLATFORM_H
+#define COREIP_E76_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E76_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h
index abd7a4d..5865710 100644
--- a/bsp/coreip-e76-rtl/metal.h
+++ b/bsp/coreip-e76-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_E76_RTL__METAL_H
 #define COREIP_E76_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -108,8 +110,8 @@ struct metal_memory __metal_dt_mem_memory_80000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -141,16 +143,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 128UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From global_external_interrupts */
diff --git a/bsp/coreip-s51-arty/metal-platform.h b/bsp/coreip-s51-arty/metal-platform.h
new file mode 100644
index 0000000..b6301ea
--- /dev/null
+++ b/bsp/coreip-s51-arty/metal-platform.h
@@ -0,0 +1,101 @@
+#ifndef COREIP_S51_ARTY__METAL_PLATFORM_H
+#define COREIP_S51_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_S51_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h
index 947c49d..1e17084 100644
--- a/bsp/coreip-s51-arty/metal.h
+++ b/bsp/coreip-s51-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_S51_ARTY__METAL_H
 #define COREIP_S51_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -180,7 +182,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -220,8 +222,8 @@ struct metal_memory __metal_dt_mem_spi_20004000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -253,16 +255,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
@@ -308,8 +310,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -465,8 +467,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -483,8 +485,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-s51-rtl/metal-platform.h b/bsp/coreip-s51-rtl/metal-platform.h
new file mode 100644
index 0000000..b1cf1a6
--- /dev/null
+++ b/bsp/coreip-s51-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_S51_RTL__METAL_PLATFORM_H
+#define COREIP_S51_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_S51_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h
index 849add9..d9b198f 100644
--- a/bsp/coreip-s51-rtl/metal.h
+++ b/bsp/coreip-s51-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_S51_RTL__METAL_H
 #define COREIP_S51_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -143,8 +145,8 @@ struct metal_memory __metal_dt_mem_itim_8000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -176,16 +178,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 128UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
diff --git a/bsp/coreip-s54-arty/metal-platform.h b/bsp/coreip-s54-arty/metal-platform.h
new file mode 100644
index 0000000..e715d34
--- /dev/null
+++ b/bsp/coreip-s54-arty/metal-platform.h
@@ -0,0 +1,101 @@
+#ifndef COREIP_S54_ARTY__METAL_PLATFORM_H
+#define COREIP_S54_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_S54_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h
index 546c3c6..6a6dbb7 100644
--- a/bsp/coreip-s54-arty/metal.h
+++ b/bsp/coreip-s54-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_S54_ARTY__METAL_H
 #define COREIP_S54_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -180,7 +182,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -220,8 +222,8 @@ struct metal_memory __metal_dt_mem_spi_20004000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -253,16 +255,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
@@ -308,8 +310,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -465,8 +467,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -483,8 +485,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-s54-rtl/metal-platform.h b/bsp/coreip-s54-rtl/metal-platform.h
new file mode 100644
index 0000000..78b3b50
--- /dev/null
+++ b/bsp/coreip-s54-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_S54_RTL__METAL_PLATFORM_H
+#define COREIP_S54_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_S54_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-s54-rtl/metal.h b/bsp/coreip-s54-rtl/metal.h
index 0003693..fcb10c4 100644
--- a/bsp/coreip-s54-rtl/metal.h
+++ b/bsp/coreip-s54-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_S54_RTL__METAL_H
 #define COREIP_S54_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -143,8 +145,8 @@ struct metal_memory __metal_dt_mem_itim_8000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -176,16 +178,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 128UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h
new file mode 100644
index 0000000..3be1bb1
--- /dev/null
+++ b/bsp/coreip-s76-arty/metal-platform.h
@@ -0,0 +1,105 @@
+#ifndef COREIP_S76_ARTY__METAL_PLATFORM_H
+#define COREIP_S76_ARTY__METAL_PLATFORM_H
+
+/* From tlclk */
+#define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 32500000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 31UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@10060000 */
+#define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+
+/* From gpio@20002000 */
+#define METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS 536879104UL
+#define METAL_SIFIVE_GPIO0_20002000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@20004000 */
+#define METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS 536887296UL
+#define METAL_SIFIVE_SPI0_20004000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@20000000 */
+#define METAL_SIFIVE_UART0_20000000_BASE_ADDRESS 536870912UL
+#define METAL_SIFIVE_UART0_20000000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* COREIP_S76_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h
index 0a385de..f42456d 100644
--- a/bsp/coreip-s76-arty/metal.h
+++ b/bsp/coreip-s76-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_S76_ARTY__METAL_H
 #define COREIP_S76_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -176,7 +178,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000;
 struct __metal_driver_fixed_clock __metal_dt_tlclk = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32500000UL,
+    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_memory_80000000 = {
@@ -205,8 +207,8 @@ struct metal_memory __metal_dt_mem_spi_20004000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -238,16 +240,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 31UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 1UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From global_external_interrupts */
@@ -268,8 +270,8 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268828672UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -283,8 +285,8 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 536879104UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_20002000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_20002000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -440,8 +442,8 @@ struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 536887296UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_20004000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_20004000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
@@ -459,8 +461,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 536870912UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_20000000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_20000000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
diff --git a/bsp/coreip-s76-rtl/metal-platform.h b/bsp/coreip-s76-rtl/metal-platform.h
new file mode 100644
index 0000000..d3ecc4c
--- /dev/null
+++ b/bsp/coreip-s76-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_S76_RTL__METAL_PLATFORM_H
+#define COREIP_S76_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 128UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_S76_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h
index c10f9d6..1187b69 100644
--- a/bsp/coreip-s76-rtl/metal.h
+++ b/bsp/coreip-s76-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_S76_RTL__METAL_H
 #define COREIP_S76_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -108,8 +110,8 @@ struct metal_memory __metal_dt_mem_memory_80000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -141,16 +143,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 128UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From global_external_interrupts */
diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h
new file mode 100644
index 0000000..79432cd
--- /dev/null
+++ b/bsp/coreip-u54-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_U54_RTL__METAL_PLATFORM_H
+#define COREIP_U54_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 133UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_U54_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h
index 3955675..38e231f 100644
--- a/bsp/coreip-u54-rtl/metal.h
+++ b/bsp/coreip-u54-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_U54_RTL__METAL_H
 #define COREIP_U54_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -127,8 +129,8 @@ struct metal_memory __metal_dt_mem_memory_80000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -162,16 +164,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .interrupt_lines[0] = 11,
     .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[1] = 9,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 133UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From global_external_interrupts */
diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h
new file mode 100644
index 0000000..a2ef2dc
--- /dev/null
+++ b/bsp/coreip-u54mc-rtl/metal-platform.h
@@ -0,0 +1,38 @@
+#ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H
+#define COREIP_U54MC_RTL__METAL_PLATFORM_H
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 137UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_U54MC_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h
index 380de59..935e165 100644
--- a/bsp/coreip-u54mc-rtl/metal.h
+++ b/bsp/coreip-u54mc-rtl/metal.h
@@ -3,6 +3,8 @@
 #ifndef COREIP_U54MC_RTL__METAL_H
 #define COREIP_U54MC_RTL__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 10
@@ -225,8 +227,8 @@ struct metal_memory __metal_dt_mem_memory_80000000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -354,16 +356,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .interrupt_lines[7] = 11,
     .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
     .interrupt_lines[8] = 9,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 137UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From global_external_interrupts */
diff --git a/bsp/freedom-e310-arty/metal-platform.h b/bsp/freedom-e310-arty/metal-platform.h
new file mode 100644
index 0000000..7fb01e7
--- /dev/null
+++ b/bsp/freedom-e310-arty/metal-platform.h
@@ -0,0 +1,89 @@
+#ifndef FREEDOM_E310_ARTY__METAL_PLATFORM_H
+#define FREEDOM_E310_ARTY__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 65000000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From gpio@10012000 */
+#define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@10014000 */
+#define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From serial@10013000 */
+#define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* FREEDOM_E310_ARTY__METAL_PLATFORM_H*/
diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h
index 16f2d53..5a726e0 100644
--- a/bsp/freedom-e310-arty/metal.h
+++ b/bsp/freedom-e310-arty/metal.h
@@ -3,6 +3,8 @@
 #ifndef FREEDOM_E310_ARTY__METAL_H
 #define FREEDOM_E310_ARTY__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -118,7 +120,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 65000000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -158,8 +160,8 @@ struct metal_memory __metal_dt_mem_spi_10014000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -191,10 +193,10 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
@@ -227,8 +229,8 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268509184UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -254,8 +256,8 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268517376UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
     .clock = NULL,
     .pinmux = NULL,
 };
@@ -264,8 +266,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 268513280UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
 /* From clock@0 */
     .clock = &__metal_dt_clock_0.clock,
 /* From gpio@10012000 */
diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h
new file mode 100644
index 0000000..db4360e
--- /dev/null
+++ b/bsp/sifive-hifive-unleashed/metal-platform.h
@@ -0,0 +1,119 @@
+#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H
+#define SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H
+
+/* From refclk */
+#define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL
+
+#define METAL_FIXED_CLOCK
+
+/* From tlclk */
+#define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL
+#define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL
+
+#define METAL_FIXED_FACTOR_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 54UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
+
+#define METAL_RISCV_PMP
+
+/* From gpio@10060000 */
+#define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL
+#define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@10040000 */
+#define METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS 268697600UL
+#define METAL_SIFIVE_SPI0_10040000_SIZE 4096UL
+
+/* From spi@10041000 */
+#define METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS 268701696UL
+#define METAL_SIFIVE_SPI0_10041000_SIZE 4096UL
+
+/* From spi@10050000 */
+#define METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS 268763136UL
+#define METAL_SIFIVE_SPI0_10050000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+/* From serial@10010000 */
+#define METAL_SIFIVE_UART0_10010000_BASE_ADDRESS 268500992UL
+#define METAL_SIFIVE_UART0_10010000_SIZE 4096UL
+
+/* From serial@10011000 */
+#define METAL_SIFIVE_UART0_10011000_BASE_ADDRESS 268505088UL
+#define METAL_SIFIVE_UART0_10011000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H*/
diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h
index b7a329b..118bdd3 100644
--- a/bsp/sifive-hifive-unleashed/metal.h
+++ b/bsp/sifive-hifive-unleashed/metal.h
@@ -3,6 +3,8 @@
 #ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H
 #define SIFIVE_HIFIVE_UNLEASHED__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 10
@@ -192,7 +194,7 @@ struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
 struct __metal_driver_fixed_clock __metal_dt_refclk = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 33333333UL,
+    .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY,
 };
 
 /* From tlclk */
@@ -201,8 +203,8 @@ struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = {
     .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock,
 /* From refclk */
     .parent = &__metal_dt_refclk.clock,
-    .mult = 1,
-    .div = 2,
+    .mult = METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT,
+    .div = METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV,
 };
 
 struct metal_memory __metal_dt_mem_dtim_1000000 = {
@@ -317,8 +319,8 @@ struct metal_memory __metal_dt_mem_spi_10050000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -446,24 +448,24 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .interrupt_lines[7] = 11,
     .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller,
     .interrupt_lines[8] = 9,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 54UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 1UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From gpio@10060000 */
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268828672UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10060000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -489,8 +491,8 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268697600UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10040000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
@@ -500,8 +502,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268701696UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10041000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
@@ -511,8 +513,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268763136UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10050000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
@@ -530,8 +532,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 268500992UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_10010000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_10010000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
@@ -545,8 +547,8 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 268505088UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_10011000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_10011000_SIZE,
 /* From tlclk */
     .clock = &__metal_dt_tlclk.clock,
     .pinmux = NULL,
diff --git a/bsp/sifive-hifive1-revb/metal-platform.h b/bsp/sifive-hifive1-revb/metal-platform.h
new file mode 100644
index 0000000..ae992ff
--- /dev/null
+++ b/bsp/sifive-hifive1-revb/metal-platform.h
@@ -0,0 +1,110 @@
+#ifndef SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H
+#define SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 16000000UL
+
+/* From clock@2 */
+#define METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY 72000000UL
+
+/* From clock@5 */
+#define METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY 32000000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From pmp@0 */
+#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
+
+#define METAL_RISCV_PMP
+
+/* From prci@10008000 */
+#define METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS 268468224UL
+#define METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE 32768UL
+
+#define METAL_SIFIVE_FE310_G000_PRCI
+#define METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG 0UL
+#define METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG 4UL
+#define METAL_SIFIVE_FE310_G000_PRCI_PLLCFG 8UL
+#define METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV 12UL
+
+/* From gpio@10012000 */
+#define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@10014000 */
+#define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From serial@10013000 */
+#define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H*/
diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h
index 82bfd01..330f08e 100644
--- a/bsp/sifive-hifive1-revb/metal.h
+++ b/bsp/sifive-hifive1-revb/metal.h
@@ -3,6 +3,8 @@
 #ifndef SIFIVE_HIFIVE1_REVB__METAL_H
 #define SIFIVE_HIFIVE1_REVB__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -159,21 +161,21 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 16000000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 /* From clock@2 */
 struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 72000000UL,
+    .rate = METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY,
 };
 
 /* From clock@5 */
 struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32000000UL,
+    .rate = METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -202,8 +204,8 @@ struct metal_memory __metal_dt_mem_spi_10014000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -235,16 +237,16 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
 /* From pmp@0 */
 struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = 8UL,
+    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
 };
 
 /* From local_external_interrupts_0 */
@@ -276,8 +278,8 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268509184UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -333,8 +335,8 @@ struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268517376UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
 /* From clock@4 */
     .clock = &__metal_dt_clock_4.clock,
 /* From gpio@10012000 */
@@ -347,8 +349,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 268513280UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
 /* From clock@4 */
     .clock = &__metal_dt_clock_4.clock,
 /* From gpio@10012000 */
@@ -369,7 +371,7 @@ struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
     .ref = &__metal_dt_clock_2.clock,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 0UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG,
 };
 
 /* From clock@1 */
@@ -380,7 +382,7 @@ struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
     .ref = &__metal_dt_clock_0.clock,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 4UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG,
 };
 
 /* From clock@4 */
@@ -393,18 +395,18 @@ struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
     .pllref = &__metal_dt_clock_1.clock,
 /* From prci@10008000 */
     .divider_base = &__metal_dt_prci_10008000,
-    .divider_offset = 12UL,
+    .divider_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 8UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLCFG,
     .init_rate = 16000000UL,
 };
 
 /* From prci@10008000 */
 struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
     .vtable = &__metal_driver_vtable_sifive_fe310_g000_prci,
-    .base = 268468224UL,
-    .size = 32768UL,
+    .base = METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE,
 };
 
 
diff --git a/bsp/sifive-hifive1/metal-platform.h b/bsp/sifive-hifive1/metal-platform.h
new file mode 100644
index 0000000..c50e2f9
--- /dev/null
+++ b/bsp/sifive-hifive1/metal-platform.h
@@ -0,0 +1,105 @@
+#ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H
+#define SIFIVE_HIFIVE1__METAL_PLATFORM_H
+
+/* From clock@0 */
+#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 16000000UL
+
+/* From clock@2 */
+#define METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY 72000000UL
+
+/* From clock@5 */
+#define METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY 32000000UL
+
+#define METAL_FIXED_CLOCK
+
+/* From clint@2000000 */
+#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
+
+#define METAL_RISCV_CLINT0
+#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
+#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
+#define METAL_RISCV_CLINT0_MTIME 49144UL
+
+/* From interrupt_controller@c000000 */
+#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
+#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
+#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
+
+#define METAL_RISCV_PLIC0
+#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
+#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
+#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
+#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
+#define METAL_RISCV_PLIC0_CLAIM 2097156UL
+
+/* From prci@10008000 */
+#define METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS 268468224UL
+#define METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE 32768UL
+
+#define METAL_SIFIVE_FE310_G000_PRCI
+#define METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG 0UL
+#define METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG 4UL
+#define METAL_SIFIVE_FE310_G000_PRCI_PLLCFG 8UL
+#define METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV 12UL
+
+/* From gpio@10012000 */
+#define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
+#define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
+
+#define METAL_SIFIVE_GPIO0
+#define METAL_SIFIVE_GPIO0_VALUE 0UL
+#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
+#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
+#define METAL_SIFIVE_GPIO0_PORT 12UL
+#define METAL_SIFIVE_GPIO0_PUE 16UL
+#define METAL_SIFIVE_GPIO0_DS 20UL
+#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
+#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
+#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
+#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
+#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
+#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
+#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
+#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
+#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
+#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
+#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
+
+/* From spi@10014000 */
+#define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
+#define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
+
+#define METAL_SIFIVE_SPI0
+#define METAL_SIFIVE_SPI0_SCKDIV 0UL
+#define METAL_SIFIVE_SPI0_SCKMODE 4UL
+#define METAL_SIFIVE_SPI0_CSID 16UL
+#define METAL_SIFIVE_SPI0_CSDEF 20UL
+#define METAL_SIFIVE_SPI0_CSMODE 24UL
+#define METAL_SIFIVE_SPI0_DELAY0 40UL
+#define METAL_SIFIVE_SPI0_DELAY1 44UL
+#define METAL_SIFIVE_SPI0_FMT 64UL
+#define METAL_SIFIVE_SPI0_TXDATA 72UL
+#define METAL_SIFIVE_SPI0_RXDATA 76UL
+#define METAL_SIFIVE_SPI0_TXMARK 80UL
+#define METAL_SIFIVE_SPI0_RXMARK 84UL
+#define METAL_SIFIVE_SPI0_FCTRL 96UL
+#define METAL_SIFIVE_SPI0_FFMT 100UL
+#define METAL_SIFIVE_SPI0_IE 112UL
+#define METAL_SIFIVE_SPI0_IP 116UL
+
+/* From serial@10013000 */
+#define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
+#define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
+
+#define METAL_SIFIVE_UART0
+#define METAL_SIFIVE_UART0_TXDATA 0UL
+#define METAL_SIFIVE_UART0_RXDATA 4UL
+#define METAL_SIFIVE_UART0_TXCTRL 8UL
+#define METAL_SIFIVE_UART0_RXCTRL 12UL
+#define METAL_SIFIVE_UART0_IE 16UL
+#define METAL_SIFIVE_UART0_IP 20UL
+#define METAL_SIFIVE_UART0_DIV 24UL
+
+#endif /* SIFIVE_HIFIVE1__METAL_PLATFORM_H*/
diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h
index 28979c7..4e96c74 100644
--- a/bsp/sifive-hifive1/metal.h
+++ b/bsp/sifive-hifive1/metal.h
@@ -3,6 +3,8 @@
 #ifndef SIFIVE_HIFIVE1__METAL_H
 #define SIFIVE_HIFIVE1__METAL_H
 
+#include <metal/machine/platform.h>
+
 #ifdef __METAL_MACHINE_MACROS
 
 #define __METAL_CLINT_NUM_PARENTS 2
@@ -156,21 +158,21 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000;
 struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 16000000UL,
+    .rate = METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY,
 };
 
 /* From clock@2 */
 struct __metal_driver_fixed_clock __metal_dt_clock_2 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 72000000UL,
+    .rate = METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY,
 };
 
 /* From clock@5 */
 struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
     .vtable = &__metal_driver_vtable_fixed_clock,
     .clock.vtable = &__metal_driver_vtable_fixed_clock.clock,
-    .rate = 32000000UL,
+    .rate = METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY,
 };
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
@@ -199,8 +201,8 @@ struct metal_memory __metal_dt_mem_spi_10014000 = {
 struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
     .vtable = &__metal_driver_vtable_riscv_clint0,
     .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
-    .control_base = 33554432UL,
-    .control_size = 65536UL,
+    .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_CLINT0_2000000_SIZE,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLINT_INTERRUPTS,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
@@ -232,10 +234,10 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
     .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 11,
-    .control_base = 201326592UL,
-    .control_size = 67108864UL,
-    .max_priority = 7UL,
-    .num_interrupts = 27UL,
+    .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS,
+    .control_size = METAL_RISCV_PLIC0_C000000_SIZE,
+    .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY,
+    .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV,
     .interrupt_controller = 1,
 };
 
@@ -268,8 +270,8 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa
 struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = {
     .vtable = &__metal_driver_vtable_sifive_gpio0,
     .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
-    .base = 268509184UL,
-    .size = 4096UL,
+    .base = METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_GPIO0_10012000_SIZE,
 /* From interrupt_controller@c000000 */
     .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller,
     .num_interrupts = METAL_MAX_GPIO_INTERRUPTS,
@@ -325,8 +327,8 @@ struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = {
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
     .vtable = &__metal_driver_vtable_sifive_spi0,
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
-    .control_base = 268517376UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_SPI0_10014000_SIZE,
 /* From clock@4 */
     .clock = &__metal_dt_clock_4.clock,
 /* From gpio@10012000 */
@@ -339,8 +341,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
     .vtable = &__metal_driver_vtable_sifive_uart0,
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,
-    .control_base = 268513280UL,
-    .control_size = 4096UL,
+    .control_base = METAL_SIFIVE_UART0_10013000_BASE_ADDRESS,
+    .control_size = METAL_SIFIVE_UART0_10013000_SIZE,
 /* From clock@4 */
     .clock = &__metal_dt_clock_4.clock,
 /* From gpio@10012000 */
@@ -361,7 +363,7 @@ struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = {
     .ref = &__metal_dt_clock_2.clock,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 0UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG,
 };
 
 /* From clock@1 */
@@ -372,7 +374,7 @@ struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = {
     .ref = &__metal_dt_clock_0.clock,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 4UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG,
 };
 
 /* From clock@4 */
@@ -385,18 +387,18 @@ struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = {
     .pllref = &__metal_dt_clock_1.clock,
 /* From prci@10008000 */
     .divider_base = &__metal_dt_prci_10008000,
-    .divider_offset = 12UL,
+    .divider_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV,
 /* From prci@10008000 */
     .config_base = &__metal_dt_prci_10008000,
-    .config_offset = 8UL,
+    .config_offset = METAL_SIFIVE_FE310_G000_PRCI_PLLCFG,
     .init_rate = 16000000UL,
 };
 
 /* From prci@10008000 */
 struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = {
     .vtable = &__metal_driver_vtable_sifive_fe310_g000_prci,
-    .base = 268468224UL,
-    .size = 32768UL,
+    .base = METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS,
+    .size = METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE,
 };