diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-01-30 13:51:39 -0800 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-02-04 12:20:52 -0800 |
| commit | e13896aa54d9ccb93b637b476d555e032a5a668e (patch) | |
| tree | f3bc7355ed0dfab29fdf1a2921979b5634599216 /bsp | |
| parent | 508c169463eeddfd5eef8b0e6f928fa848dd46c0 (diff) | |
Replace all mee with metal
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/coreip-e31-arty/design.dts | 2 | ||||
| -rw-r--r-- | bsp/coreip-s51-arty/design.dts | 2 | ||||
| -rw-r--r-- | bsp/freedom-e310-arty/design.dts | 2 | ||||
| -rw-r--r-- | bsp/sifive-hifive1/design.dts | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts index 96698e9..c69740e 100644 --- a/bsp/coreip-e31-arty/design.dts +++ b/bsp/coreip-e31-arty/design.dts @@ -8,7 +8,7 @@ chosen { stdout-path = "/soc/serial@20000000:115200"; - mee,entry = <&L12 0x400000>; + metal,entry = <&L12 0x400000>; }; L17: cpus { diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index ea349bb..6c7379d 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -8,7 +8,7 @@ chosen { stdout-path = "/soc/serial@20000000:115200"; - mee,entry = <&L12 0x400000>; + metal,entry = <&L12 0x400000>; }; L17: cpus { diff --git a/bsp/freedom-e310-arty/design.dts b/bsp/freedom-e310-arty/design.dts index 73f8fbb..74da572 100644 --- a/bsp/freedom-e310-arty/design.dts +++ b/bsp/freedom-e310-arty/design.dts @@ -8,7 +8,7 @@ chosen { stdout-path = "/soc/serial@10013000:115200"; - mee,entry = <&sip0 0x400000>; + metal,entry = <&sip0 0x400000>; }; cpus { diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts index 26e4048..abccd6c 100644 --- a/bsp/sifive-hifive1/design.dts +++ b/bsp/sifive-hifive1/design.dts @@ -8,7 +8,7 @@ chosen { stdout-path = "/soc/serial@10013000:115200"; - mee,entry = <&sip0 0x400000>; + metal,entry = <&sip0 0x400000>; }; cpus { |