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| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-06-05 09:30:32 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-05 09:30:32 +0800 |
| commit | 78b48aac4add3ba3a8a46eafa2b8c8cde065d1f2 (patch) | |
| tree | 529b31e1159e56592621439d1bca1db64da03817 /scripts | |
| parent | f2c7f75ceef24aec9891d75c2b4fb5db5b847868 (diff) | |
| parent | 9ed1c05e3b202ef2ef17cae4bfc0ca6425541d13 (diff) | |
Merge pull request #259 from sifive/coremark_development-19.05
Coremark development 19.05
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/standalone.mk | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/scripts/standalone.mk b/scripts/standalone.mk index 6f87950..d0740cd 100644 --- a/scripts/standalone.mk +++ b/scripts/standalone.mk @@ -49,6 +49,14 @@ ifeq ($(LINK_TARGET),) endif endif +ifeq ($(PROGRAM),coremark) +ifeq ($(CONFIGURATION),release) +ifeq ($(LINK_TARGET),) +LINK_TARGET = ramrodata +endif +endif +endif + ifeq ($(LINK_TARGET),) LINK_TARGET = default endif @@ -127,6 +135,15 @@ endif RISCV_XCFLAGS += -DDHRY_ITERS=$(TARGET_DHRY_ITERS) endif +ifeq ($(PROGRAM),coremark) +ifeq ($(RISCV_SERIES),sifive-7-series) +RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -funroll-all-loops --param max-inline-insns-auto=20 -falign-functions=8 -falign-jumps=8 -falign-loops=8 --param inline-min-speedup=10 -mtune=sifive-7-series -ffast-math +else +RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4 --param inline-min-speedup=10 +endif +RISCV_XCFLAGS += -DITERATIONS=$(TARGET_CORE_ITERS) +endif + # Turn on garbage collection for unused sections RISCV_LDFLAGS += -Wl,--gc-sections # Turn on linker map file generation @@ -171,6 +188,7 @@ $(PROGRAM_ELF): \ $(BSP_DIR)/metal.$(LINK_TARGET).lds mkdir -p $(dir $@) $(MAKE) -C $(SRC_DIR) $(basename $(notdir $@)) \ + PORT_DIR=$(PORT_DIR) \ AR=$(RISCV_AR) \ CC=$(RISCV_GCC) \ CXX=$(RISCV_GXX) \ |