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-rw-r--r--bsp/coreip-e20/settings.mk1
-rw-r--r--bsp/coreip-e21/settings.mk1
-rw-r--r--bsp/coreip-e24/settings.mk1
-rw-r--r--bsp/coreip-e34/settings.mk1
-rw-r--r--bsp/coreip-e76/settings.mk1
-rw-r--r--bsp/coreip-s54/settings.mk1
-rw-r--r--bsp/coreip-s76/settings.mk1
7 files changed, 7 insertions, 0 deletions
diff --git a/bsp/coreip-e20/settings.mk b/bsp/coreip-e20/settings.mk
index 50c6504..1ac4d9f 100644
--- a/bsp/coreip-e20/settings.mk
+++ b/bsp/coreip-e20/settings.mk
@@ -2,4 +2,5 @@
RISCV_ARCH=rv32imc
RISCV_ABI=ilp32
+RISCV_CMODEL=medlow
COREIP_MEM_WIDTH=32
diff --git a/bsp/coreip-e21/settings.mk b/bsp/coreip-e21/settings.mk
index 0c818ec..32bb84d 100644
--- a/bsp/coreip-e21/settings.mk
+++ b/bsp/coreip-e21/settings.mk
@@ -2,4 +2,5 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
+RISCV_CMODEL=medlow
COREIP_MEM_WIDTH=32
diff --git a/bsp/coreip-e24/settings.mk b/bsp/coreip-e24/settings.mk
index 0c818ec..32bb84d 100644
--- a/bsp/coreip-e24/settings.mk
+++ b/bsp/coreip-e24/settings.mk
@@ -2,4 +2,5 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
+RISCV_CMODEL=medlow
COREIP_MEM_WIDTH=32
diff --git a/bsp/coreip-e34/settings.mk b/bsp/coreip-e34/settings.mk
index 0c818ec..32bb84d 100644
--- a/bsp/coreip-e34/settings.mk
+++ b/bsp/coreip-e34/settings.mk
@@ -2,4 +2,5 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
+RISCV_CMODEL=medlow
COREIP_MEM_WIDTH=32
diff --git a/bsp/coreip-e76/settings.mk b/bsp/coreip-e76/settings.mk
index 3dcc8c7..fd049f4 100644
--- a/bsp/coreip-e76/settings.mk
+++ b/bsp/coreip-e76/settings.mk
@@ -2,4 +2,5 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
+RISCV_CMODEL=medlow
COREIP_MEM_WIDTH=64
diff --git a/bsp/coreip-s54/settings.mk b/bsp/coreip-s54/settings.mk
index 553417e..fabb838 100644
--- a/bsp/coreip-s54/settings.mk
+++ b/bsp/coreip-s54/settings.mk
@@ -1,3 +1,4 @@
RISCV_ARCH=rv64imac
RISCV_ABI=lp64
+RISCV_CMODE=medany
COREIP_MEM_WIDTH=64
diff --git a/bsp/coreip-s76/settings.mk b/bsp/coreip-s76/settings.mk
index 553417e..a7d8dfa 100644
--- a/bsp/coreip-s76/settings.mk
+++ b/bsp/coreip-s76/settings.mk
@@ -1,3 +1,4 @@
RISCV_ARCH=rv64imac
RISCV_ABI=lp64
+RISCV_CMODEL=medany
COREIP_MEM_WIDTH=64