diff options
| -rw-r--r-- | bsp/coreip-e24-arty/design.dts | 113 | ||||
| -rw-r--r-- | bsp/coreip-e24-arty/mee.h | 138 | ||||
| -rw-r--r-- | bsp/coreip-e24-arty/mee.lds | 215 | ||||
| -rw-r--r-- | bsp/coreip-e24-arty/openocd.cfg | 30 | ||||
| -rw-r--r-- | bsp/coreip-e24-arty/settings.mk | 2 |
5 files changed, 498 insertions, 0 deletions
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts new file mode 100644 index 0000000..7cf8609 --- /dev/null +++ b/bsp/coreip-e24-arty/design.dts @@ -0,0 +1,113 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE240G-dev", "fe240-dev", "sifive-dev"; + model = "SiFive,FE240G"; + L17: aliases { + serial0 = &L10; + }; + L16: cpus { + #address-cells = <1>; + #size-cells = <0>; + L3: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,caboose0", "riscv"; + device_type = "cpu"; + reg = <0x0>; + riscv,isa = "rv32imafc"; + status = "okay"; + timebase-frequency = <1000000>; + L2: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L15: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; + ranges; + L0: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L2 65535>; + reg = <0x0 0x1000>; + reg-names = "control"; + }; + L9: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + reg-names = "mem"; + }; + L7: global-external-interrupts { + interrupt-parent = <&L1>; + interrupts = <0 1 2 3>; + }; + L12: gpio@20002000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sifive,gpio0"; + gpio-controller; + interrupt-controller; + interrupt-parent = <&L1>; + interrupts = <6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21>; + reg = <0x20002000 0x1000>; + reg-names = "control"; + }; + L1: interrupt-controller@2000000 { + #interrupt-cells = <1>; + compatible = "sifive,clic0"; + interrupt-controller; + interrupts-extended = <&L2 3 &L2 7 &L2 11>; + reg = <0x2000000 0x1000000>; + reg-names = "control"; + sifive,numints = <143>; + sifive,numlevels = <16>; + }; + L8: local-external-interrupts-0 { + interrupt-parent = <&L1>; + interrupts = <26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152>; + }; + L13: pwm@20005000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L1>; + interrupts = <22 23 24 25>; + reg = <0x20005000 0x1000>; + reg-names = "control"; + }; + L10: serial@20000000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L1>; + interrupts = <4>; + reg = <0x20000000 0x1000>; + reg-names = "control"; + }; + L11: spi@20004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sifive,spi0"; + interrupt-parent = <&L1>; + interrupts = <5>; + reg = <0x20004000 0x1000 0x40000000 0x20000000>; + reg-names = "control", "mem"; + }; + L5: sys-sram@80000000 { + compatible = "sifive,sram0"; + reg = <0x80000000 0x8000>; + reg-names = "mem"; + }; + L6: sys-sram@80008000 { + compatible = "sifive,sram0"; + reg = <0x80008000 0x8000>; + reg-names = "mem"; + }; + L4: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x4000 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/coreip-e24-arty/mee.h b/bsp/coreip-e24-arty/mee.h new file mode 100644 index 0000000..fb052dc --- /dev/null +++ b/bsp/coreip-e24-arty/mee.h @@ -0,0 +1,138 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_E24_ARTY__MEE_H +#define COREIP_E24_ARTY__MEE_H + +#define __MEE_GPIO_20002000_INTERRUPTS 16 +#define MEE_MAX_GPIO_INTERRUPTS __MEE_GPIO_20002000_INTERRUPTS + +#define __MEE_SERIAL_20000000_INTERRUPTS 1 +#define MEE_MAX_UART_INTERRUPTS __MEE_SERIAL_20000000_INTERRUPTS + +#include <mee/drivers/riscv,cpu.h> +#include <mee/drivers/sifive,gpio0.h> +#include <mee/drivers/sifive,uart0.h> +#include <mee/drivers/sifive,test0.h> +/* From cpu@0 */ +asm (".weak __mee_dt_cpu_0"); +struct __mee_driver_cpu __mee_dt_cpu_0; + +/* From interrupt_controller */ +asm (".weak __mee_dt_interrupt_controller"); +struct __mee_driver_riscv_cpu_intc __mee_dt_interrupt_controller; + +/* From gpio@20002000 */ +asm (".weak __mee_dt_gpio_20002000"); +struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000; + +/* From serial@20000000 */ +asm (".weak __mee_dt_serial_20000000"); +struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000; + +/* From teststatus@4000 */ +asm (".weak __mee_dt_teststatus_4000"); +struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000; + +/* From cpu@0 */ +struct __mee_driver_cpu __mee_dt_cpu_0 = { + .vtable = &__mee_driver_vtable_cpu, + .cpu.vtable = &__mee_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__mee_dt_interrupt_controller.controller, +}; + +/* From cpu@0 */ +#define __MEE_DT_RISCV_CPU_HANDLE (&__mee_dt_cpu_0.cpu) + +#define __MEE_DT_CPU_0_HANDLE (&__mee_dt_cpu_0.cpu) + +/* From interrupt_controller */ +struct __mee_driver_riscv_cpu_intc __mee_dt_interrupt_controller = { + .vtable = &__mee_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__mee_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +#define __MEE_DT_RISCV_CPU_INTC_HANDLE (&__mee_dt_interrupt_controller.controller) + +#define __MEE_DT_INTERRUPT_CONTROLLER_HANDLE (&__mee_dt_interrupt_controller.controller) + +/* From gpio@20002000 */ +struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000 = { + .vtable = &__mee_driver_vtable_sifive_gpio0, + .base = 536879104UL, + .size = 4096UL, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__mee_dt_interrupt_controller_2000000.plic0, + .num_interrupts = MEE_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 6, + .interrupt_lines[1] = 7, + .interrupt_lines[2] = 8, + .interrupt_lines[3] = 9, + .interrupt_lines[4] = 10, + .interrupt_lines[5] = 11, + .interrupt_lines[6] = 12, + .interrupt_lines[7] = 13, + .interrupt_lines[8] = 14, + .interrupt_lines[9] = 15, + .interrupt_lines[10] = 16, + .interrupt_lines[11] = 17, + .interrupt_lines[12] = 18, + .interrupt_lines[13] = 19, + .interrupt_lines[14] = 20, + .interrupt_lines[15] = 21, +}; + +/* From serial@20000000 */ +struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000 = { + .vtable = &__mee_driver_vtable_sifive_uart0, + .uart.vtable = &__mee_driver_vtable_sifive_uart0.uart, + .control_base = 536870912UL, + .control_size = 4096UL, + .clock = NULL, + .pinmux = NULL, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__mee_dt_interrupt_controller_2000000.plic0, + .num_interrupts = MEE_MAX_UART_INTERRUPTS, + .interrupt_line = 4UL, +}; + +/* From teststatus@4000 */ +struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000 = { + .vtable = &__mee_driver_vtable_sifive_test0, + .shutdown.vtable = &__mee_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From teststatus@4000 */ +#define __MEE_DT_SHUTDOWN_HANDLE (&__mee_dt_teststatus_4000.shutdown) + +#define __MEE_DT_TESTSTATUS_4000_HANDLE (&__mee_dt_teststatus_4000.shutdown) + +#define __MEE_DT_MAX_HARTS 1 + +asm (".weak __mee_cpu_table"); +struct __mee_driver_cpu *__mee_cpu_table[] = { + &__mee_dt_cpu_0}; + +#define __MEE_DT_MAX_LEDS 0 + +asm (".weak __mee_led_table"); +struct __mee_driver_sifive_gpio_led *__mee_led_table[] = { + NULL }; +#define __MEE_DT_MAX_BUTTONS 0 + +asm (".weak __mee_button_table"); +struct __mee_driver_sifive_gpio_button *__mee_button_table[] = { + NULL }; +#define __MEE_DT_MAX_SWITCHES 0 + +asm (".weak __mee_switch_table"); +struct __mee_driver_sifive_gpio_switch *__mee_switch_table[] = { + NULL }; +#endif /*MEE__MACHINE__COREIP_E24_ARTY__MEE_H*/ + +#endif/*ASSEMBLY*/ diff --git a/bsp/coreip-e24-arty/mee.lds b/bsp/coreip-e24-arty/mee.lds new file mode 100644 index 0000000..1981dec --- /dev/null +++ b/bsp/coreip-e24-arty/mee.lds @@ -0,0 +1,215 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x800; + + + .init : + { + KEEP (*(.text.mee.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.itim .itim.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >ram AT>flash :ram_init + + + .itim : + { + } >flash AT>flash :flash + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( mee_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( mee_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( mee_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( mee_segment_bss_target_end = . ); + PROVIDE( mee_segment_heap_target_start = . ); + + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( mee_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(mee_segment_stack_end = .); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-e24-arty/openocd.cfg b/bsp/coreip-e24-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-e24-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk new file mode 100644 index 0000000..31143b5 --- /dev/null +++ b/bsp/coreip-e24-arty/settings.mk @@ -0,0 +1,2 @@ +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 |