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| -rw-r--r-- | bsp/sifive-hifive1/README.md | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index 6311207..d0d0c7a 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -4,7 +4,6 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines |