diff options
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | README.md | 70 | ||||
| -rw-r--r-- | bsp/coreip-e31-arty/openocd.cfg | 30 | ||||
| -rw-r--r-- | bsp/coreip-s51-arty/openocd.cfg | 30 | ||||
| -rw-r--r-- | bsp/freedom-e310-arty/openocd.cfg | 30 | ||||
| -rwxr-xr-x | bsp/update-targets.sh | 2 |
6 files changed, 158 insertions, 12 deletions
@@ -131,17 +131,21 @@ RISCV_GXX := $(CROSS_COMPILE)-g++ RISCV_OBJDUMP := $(CROSS_COMPILE)-objdump RISCV_GDB := $(CROSS_COMPILE)-gdb RISCV_AR := $(CROSS_COMPILE)-ar -RISCV_OPENOCD := openocd else RISCV_GCC := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-gcc) RISCV_GXX := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-g++) RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-objdump) RISCV_GDB := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-gdb) RISCV_AR := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-ar) -RISCV_OPENOCD := $(abspath $(RISCV_PATH)/bin/openocd) PATH := $(abspath $(RISCV_PATH)/bin):$(PATH) endif +ifeq ($(RISCV_OPENOCD_PATH),) +RISCV_OPENOCD := openocd +else +RISCV_OPENOCD := $(abspath $(RISCV_OPENOCD_PATH)/bin/openocd) +endif + ############################################################# # Compiles an instance of the MEE targeted at $(BOARD) ############################################################# @@ -1,11 +1,40 @@ -# README # +# SiFive Freedom E SDK README # -This repository, maintained by SiFive, Inc, makes it easy to get started developing software for the Freedom E RISC-V platform. +This repository, maintained by SiFive Inc, makes it easy to get started developing +software for the Freedom E and Freedom S Embedded RISC-V Platforms. ### Contents ### -* Board Support Packages for FE310 and Development Kits +#### Freedom Metal Compatibility Library #### + +* Board Support Packages for + - SiFive HiFive 1 (sifive-hifive1) + - SiFive Freedom E310 Arty (freedom-e310-arty) + - SiFive CoreIP (e.g. coreip-e31) + - SiFive CoreIP Arty FPGA Evaluation targets (e.g. coreip-e31-arty) * A Few Example Programs + - Example programs targeting the Freedom Metal compatibility library can be identified + as submodules within the software/ directory, rather than being maintained in-tree + like the legacy examples are. + +#### (Deprecated) Legacy Freedom E SDK Library #### + +As we transition to supporting SiFive targets and examples with the new Freedom Metal +compatibility library, the legacy Freedom E SDK libraries and examples are still available +within this repository. + +* Board Support Packages for + - SiFive HiFive 1 (freedom-e300-hifive1) + - SiFive Freedom E310 Arty (freedom-e300-arty) + - SiFive CoreIP Arty FPGA Evaluation Targets (e.g. coreplexip-e31-arty) + - Additional legacy targets are contained within the bsp/env/ directory. +* A Few Example Programs + - Example programs targeting the legacy Freedom E SDK can be identified as being tracked + within this repository in the software/ directory, rathre than being maintained + out-of-tree like the Freedom Metal examples are. + +Legacy examples can be built using the same commands as the Freedom Metal examples and simply +omitting the `BSP=mee` argument or substituting it with `BSP=legacy`. ### Setting up the SDK ### @@ -15,6 +44,12 @@ First, clone this repository: git clone --recursive https://github.com/sifive/freedom-e-sdk.git ``` +If at first you omit the `--recursive` option, you can update submodules using the command: + +``` +git submodule update --init --recursive +``` + To see Makefile options: ``` @@ -52,19 +87,36 @@ git pull origin master git submodule update --init --recursive ``` -If you would like to recompile the entire toolchain after performing the above: +### Using the Tools ### + +#### Building an Example #### + +To compile a bare-metal RISC-V program: + +``` +cd freedom-e-sdk +make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] software +``` + +#### Uploading to the Target Board #### + +``` +cd freedom-e-sdk +make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] upload +``` + +#### Debugging a Target Program #### ``` -make uninstall -make tools +cd freedom-e-sdk +make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] debug ``` -### Using the Tools ### -To compile a bare-metal RISC-V program: +#### Cleaning a Target Program Build Directory #### ``` cd freedom-e-sdk -make software [PROGRAM=demo_gpio] [BOARD=freedom-e300-hifive1] +make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] clean ``` Run `make help` for more commands. diff --git a/bsp/coreip-e31-arty/openocd.cfg b/bsp/coreip-e31-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-e31-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/coreip-s51-arty/openocd.cfg b/bsp/coreip-s51-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-s51-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/freedom-e310-arty/openocd.cfg b/bsp/freedom-e310-arty/openocd.cfg new file mode 100644 index 0000000..ba13207 --- /dev/null +++ b/bsp/freedom-e310-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10014000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/update-targets.sh b/bsp/update-targets.sh index 337d493..780d662 100755 --- a/bsp/update-targets.sh +++ b/bsp/update-targets.sh @@ -9,7 +9,7 @@ DTB_FILENAME=temp.dtb HEADER_FILENAME=mee.h LDSCRIPT_FILENAME=mee.lds -TARGET_LIST="$(ls coreip* -d) " +TARGET_LIST="$(ls -d coreip*) " TARGET_LIST+="sifive-hifive1 freedom-e310-arty " update_target() { |