diff options
| -rw-r--r-- | bsp/qemu-sifive-e31/README.md | 2 | ||||
| -rw-r--r-- | bsp/qemu-sifive-s51/README.md | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/bsp/qemu-sifive-e31/README.md b/bsp/qemu-sifive-e31/README.md index 9474b9f..72889b9 100644 --- a/bsp/qemu-sifive-e31/README.md +++ b/bsp/qemu-sifive-e31/README.md @@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS + +This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1 diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md index 64593f3..7825a98 100644 --- a/bsp/qemu-sifive-s51/README.md +++ b/bsp/qemu-sifive-s51/README.md @@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS + +This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1 |