diff options
122 files changed, 218 insertions, 37427 deletions
diff --git a/FreedomStudio/E2FPGA/clic_vectored/.cproject b/FreedomStudio/E2FPGA/clic_vectored/.cproject deleted file mode 100644 index 85a0e97..0000000 --- a/FreedomStudio/E2FPGA/clic_vectored/.cproject +++ /dev/null @@ -1,208 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings/> - <extensions> - <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> - <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> - 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b/FreedomStudio/E2FPGA/coreplexip_welcome/.project deleted file mode 100644 index 29e06f6..0000000 --- a/FreedomStudio/E2FPGA/coreplexip_welcome/.project +++ /dev/null @@ -1,358 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<projectDescription> - <name>coreplexip_welcome</name> - <comment></comment> - <projects> - </projects> - <buildSpec> - <buildCommand> - <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> - <triggers>clean,full,incremental,</triggers> - <arguments> - </arguments> - </buildCommand> - <buildCommand> - <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> - <triggers>full,incremental,</triggers> - <arguments> - </arguments> - </buildCommand> - </buildSpec> - <natures> - <nature>org.eclipse.cdt.core.cnature</nature> - <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> - <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> - </natures> - <linkedResources> - <link> - <name>bsp</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>coreplexip_welcome.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/software/coreplexip_welcome/coreplexip_welcome.c</locationURI> - </link> - <link> - <name>bsp/drivers</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/env</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/include</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/libwrap</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/drivers/clic</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/drivers/fe300prci</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/env/coreplexip-arty.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI> - </link> - <link> - <name>bsp/env/encoding.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI> - </link> - <link> - <name>bsp/env/entry.S</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI> - </link> - <link> - <name>bsp/env/hifive1.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI> - </link> - <link> - <name>bsp/env/start.S</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI> - </link> - <link> - <name>bsp/include/sifive</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/libwrap/misc</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/libwrap/stdlib</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/libwrap/sys</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/drivers/clic/clic_driver.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.c</locationURI> - </link> - <link> - <name>bsp/drivers/clic/clic_driver.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.h</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/flash.lds</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/init.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/openocd.cfg</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/platform.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/settings.mk</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/tim-split.lds</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds</locationURI> - </link> - <link> - <name>bsp/env/coreip-e2-arty/tim.lds</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds</locationURI> - </link> - <link> - <name>bsp/include/sifive/bits.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/const.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices</name> - <type>2</type> - <locationURI>virtual:/virtual</locationURI> - </link> - <link> - <name>bsp/include/sifive/sections.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/smp.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI> - </link> - <link> - <name>bsp/libwrap/misc/write_hex.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI> - </link> - <link> - <name>bsp/libwrap/stdlib/malloc.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/_exit.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/close.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/execve.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/fork.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/fstat.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/getpid.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/isatty.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/kill.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/link.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/lseek.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/open.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/openat.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/puts.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/read.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/sbrk.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/stat.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/stub.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/times.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/unlink.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/wait.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/weak_under_alias.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/write.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/aon.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/clic.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clic.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/clint.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/gpio.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/otp.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/plic.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/prci.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/pwm.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/spi.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/uart.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> - </link> - </linkedResources> -</projectDescription> diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch deleted file mode 100644 index 356c25a..0000000 --- a/FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch +++ /dev/null @@ -1,61 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/> -<booleanAttribute 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value="Debug/coreplexip_welcome.elf"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/> -<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/coreplexip_welcome"/> -</listAttribute> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> -<listEntry value="4"/> -</listAttribute> -<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> -<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> -</launchConfiguration> diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E2FPGA/dhrystone/.cproject b/FreedomStudio/E2FPGA/dhrystone/.cproject deleted file mode 100644 index 863a5a9..0000000 --- a/FreedomStudio/E2FPGA/dhrystone/.cproject +++ /dev/null @@ -1,216 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings/> - <extensions> - <extension id="org.eclipse.cdt.core.ELF" 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- "e31arty": { - "displayName": "Core Complex E31 Arty", - "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.", - "supplier": { - "name": "sifive", - "id": "1", - "displayName": "SiFive", - "fullName": "SiFive, Inc.", - "contact": "info@sifive.com" - }, - "busWidth": "32", - "resetMask": "all", - "resetValue": "0x00000000", - "access": "rw", - "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_", - "headerTypePrefix": "sifive_e31arty_", - "headerInterruptPrefix": "sifive_e31arty_interrupt_global_", - "headerInterruptEnumPrefix": "riscv_interrupts_global_", - "revision": "r0p0", - "numInterrupts": "26", - "priorityBits": "3", - "regWidth": "32", - "cores": { - "e31": { - "harts": "1", - "isa": "RV32IMAC", - "isaVersion": "2.2", - "mpu": "pmp", - "mmu": "none", - "localInterrupts": { - "machine_software": { - "description": "Machine Software Interrupt", - "value": "3" - }, - "machine_timer": { - "description": "Machine Timer Interrupt", - "value": "7" - }, - "machine_ext": { - "description": "Machine External Interrupt", - "value": "11" - }, - "0": { - "description": "Local Interrupt 0", - "value": "16" - }, - "1": { - "description": "Local Interrupt 1", - "value": "17" - }, - "2": { - "description": "Local Interrupt 2", - "value": "18" - }, - "3": { - "description": "Local Interrupt 3", - "value": "19" - }, - "4": { - "description": "Local Interrupt 4", - "value": "20" - }, - "5": { - "description": "Local Interrupt 5", - "value": "21" - }, - "6": { - "description": "Local Interrupt 6", - "value": "22" - }, - "7": { - "description": "Local Interrupt 7", - "value": "23" - }, - "8": { - "description": "Local Interrupt 8", - "value": "24" - }, - "9": { - "description": "Local Interrupt 9", - "value": "25" - }, - "10": { - "description": "Local Interrupt 10", - "value": "26" - }, - "11": { - "description": "Local Interrupt 11", - "value": "27" - }, - "12": { - "description": "Local Interrupt 12", - "value": "28" - }, - "13": { - "description": "Local Interrupt 13", - "value": "29" - }, - "14": { - "description": "Local Interrupt 14", - "value": "30" - }, - "15": { - "description": "Local Interrupt 15", - "value": "31" - } - }, - "numLocalInterrupts": "16" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - } - }, - "clusters": { - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "registers": { - "low": { - "description": "Machine Compare Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Compare Register High", - "addressOffset": "0x0004" - } - } - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "registers": { - "low": { - "description": "Machine Time Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Time Register High", - "addressOffset": "0x0004" - } - } - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "27", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "8", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "8", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - }, - "interrupts": { - "switch0": { - "description": "SWITCH 0 Interrupt", - "value": "2" - }, - "switch1": { - "description": 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"addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low 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"gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E31FPGA/dhrystone/.cproject b/FreedomStudio/E31FPGA/dhrystone/.cproject deleted file mode 100644 index dba647c..0000000 --- a/FreedomStudio/E31FPGA/dhrystone/.cproject +++ /dev/null @@ -1,216 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" 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"schemaVersion": "0.2.4", - "contentVersion": "0.2.0", - "headerVersion": "0.2.0", - "device": { - "e31arty": { - "displayName": "Core Complex E31 Arty", - "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.", - "supplier": { - "name": "sifive", - "id": "1", - "displayName": "SiFive", - "fullName": "SiFive, Inc.", - "contact": "info@sifive.com" - }, - "busWidth": "32", - "resetMask": "all", - "resetValue": "0x00000000", - "access": "rw", - "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_", - "headerTypePrefix": "sifive_e31arty_", - "headerInterruptPrefix": "sifive_e31arty_interrupt_global_", - "headerInterruptEnumPrefix": "riscv_interrupts_global_", - "revision": "r0p0", - "numInterrupts": "26", - "priorityBits": "3", - "regWidth": "32", - "cores": { - "e31": { - "harts": "1", - "isa": "RV32IMAC", - "isaVersion": "2.2", - "mpu": "pmp", - "mmu": "none", - "localInterrupts": { - "machine_software": { - "description": "Machine Software Interrupt", - "value": "3" - }, - "machine_timer": { - "description": "Machine Timer Interrupt", - "value": "7" - }, - "machine_ext": { - "description": "Machine External Interrupt", - "value": "11" - }, - "0": { - "description": "Local Interrupt 0", - "value": "16" - }, - "1": { - "description": "Local Interrupt 1", - "value": "17" - }, - "2": { - "description": "Local Interrupt 2", - "value": "18" - }, - "3": { - "description": "Local Interrupt 3", - "value": "19" - }, - "4": { - "description": "Local Interrupt 4", - "value": "20" - }, - "5": { - "description": "Local Interrupt 5", - "value": "21" - }, - "6": { - "description": "Local Interrupt 6", - "value": "22" - }, - "7": { - "description": "Local Interrupt 7", - "value": "23" - }, - "8": { - "description": "Local Interrupt 8", - "value": "24" - }, - "9": { - "description": "Local Interrupt 9", - "value": "25" - }, - "10": { - "description": "Local Interrupt 10", - "value": "26" - }, - "11": { - "description": "Local Interrupt 11", - "value": "27" - }, - "12": { - "description": "Local Interrupt 12", - "value": "28" - }, - "13": { - "description": "Local Interrupt 13", - "value": "29" - }, - "14": { - "description": "Local Interrupt 14", - "value": "30" - }, - "15": { - "description": "Local Interrupt 15", - "value": "31" - } - }, - "numLocalInterrupts": "16" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - } - }, - "clusters": { - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "registers": { - "low": { - "description": "Machine Compare Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Compare Register High", - "addressOffset": "0x0004" - } - } - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "registers": { - "low": { - "description": "Machine Time Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Time Register High", - "addressOffset": "0x0004" - } - } - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "27", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "8", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "8", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - }, - "interrupts": { - "switch0": { - "description": "SWITCH 0 Interrupt", - "value": "2" - }, - "switch1": { - "description": "SWITCH 1 Interrupt", - "value": "3" - }, - "switch2": { - "description": "SWITCH 2 Interrupt", - "value": "4" - }, - "switch3": { - "description": "SWITCH 3 Interrupt", - "value": "5" - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x20002000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E31FPGA/global_interrupts/.cproject b/FreedomStudio/E31FPGA/global_interrupts/.cproject deleted file mode 100644 index 3d95eb4..0000000 --- a/FreedomStudio/E31FPGA/global_interrupts/.cproject +++ /dev/null @@ -1,215 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings/> - <extensions> - <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> - 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"bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - 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} -}
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a/FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 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"bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 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"description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
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a/FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 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"gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
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a/FreedomStudio/E31FPGA/performance_counters/sifive-coreplexip-e31-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote 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"bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch deleted file mode 100644 index 0723d26..0000000 --- a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch +++ /dev/null @@ -1,80 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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"description": "Local Interrupt 14", - "value": "30" - }, - "15": { - "description": "Local Interrupt 15", - "value": "31" - } - }, - "numLocalInterrupts": "16" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - }, - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "regWidth": "64" - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "regWidth": "64" - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "27", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "16", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "16", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - }, - "interrupts": { - "switch0": { - "description": "SWITCH 0 Interrupt", - "value": "2" - }, - "switch1": { - "description": "SWITCH 1 Interrupt", - "value": "3" - }, - "switch2": { - "description": "SWITCH 2 Interrupt", - "value": "4" - }, - "switch3": { - "description": "SWITCH 3 Interrupt", - "value": "5" - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x20002000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to 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- "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E51FPGA/global_interrupts/.cproject b/FreedomStudio/E51FPGA/global_interrupts/.cproject deleted file mode 100644 index 672c12d..0000000 --- a/FreedomStudio/E51FPGA/global_interrupts/.cproject +++ /dev/null @@ -1,210 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings/> - <extensions> - <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> - 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<type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/otp.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/plic.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/prci.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/pwm.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/spi.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/uart.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> - </link> - </linkedResources> -</projectDescription> diff --git a/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json deleted file mode 100644 index aac7a77..0000000 --- a/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json +++ /dev/null @@ -1,1230 +0,0 @@ -{ - "schemaVersion": "0.2.4", - "contentVersion": "0.2.0", - "headerVersion": "0.2.0", - "device": { - "e51arty": { - "displayName": "Core Complex E51 Arty", - "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.", - "supplier": { - "name": "sifive", - "id": "1", - "displayName": "SiFive", - "fullName": "SiFive, Inc.", - "contact": "info@sifive.com" - }, - "busWidth": "64", - "resetMask": "all", - "resetValue": "0x0000000000000000", - "access": "rw", - "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_", - "headerTypePrefix": "sifive_e51arty_", - "headerInterruptPrefix": "sifive_e51arty_interrupt_global_", - "headerInterruptEnumPrefix": "riscv_interrupts_global_", - "revision": "r0p0", - "numInterrupts": "26", - "priorityBits": "3", - "regWidth": "32", - "cores": { - "e51": { - "harts": "1", - "isa": "RV64IMAC", - "isaVersion": "2.2", - "mpu": "pmp", - "mmu": "none", - "localInterrupts": { - "machine_software": { - "description": "Machine Software Interrupt", - "value": "3" - }, - "machine_timer": { - "description": "Machine Timer Interrupt", - "value": "7" - }, - "machine_ext": { - "description": "Machine External Interrupt", - "value": "11" - }, - "0": { - "description": "Local Interrupt 0", - "value": "16" - }, - "1": { - "description": "Local Interrupt 1", - "value": "17" - }, - "2": { - "description": "Local Interrupt 2", - "value": "18" - }, - "3": { - "description": "Local Interrupt 3", - "value": "19" - }, - "4": { - "description": "Local Interrupt 4", - "value": "20" - }, - "5": { - "description": "Local Interrupt 5", - "value": "21" - }, - "6": { - "description": "Local Interrupt 6", - "value": "22" - }, - "7": { - "description": "Local Interrupt 7", - "value": "23" - }, - "8": { - "description": "Local Interrupt 8", - "value": "24" - }, - "9": { - "description": "Local Interrupt 9", - "value": "25" - }, - "10": { - "description": "Local Interrupt 10", - "value": "26" - }, - "11": { - "description": "Local Interrupt 11", - "value": "27" - }, - "12": { - "description": "Local Interrupt 12", - "value": "28" - }, - "13": { - "description": "Local Interrupt 13", - "value": "29" - }, - "14": { - "description": "Local Interrupt 14", - "value": "30" - }, - "15": { - "description": "Local Interrupt 15", - "value": "31" - } - }, - "numLocalInterrupts": "16" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - }, - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "regWidth": "64" - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "regWidth": "64" - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "27", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "16", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "16", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - }, - "interrupts": { - "switch0": { - "description": "SWITCH 0 Interrupt", - "value": "2" - }, - "switch1": { - "description": "SWITCH 1 Interrupt", - "value": "3" - }, - "switch2": { - "description": "SWITCH 2 Interrupt", - "value": "4" - }, - "switch3": { - "description": "SWITCH 3 Interrupt", - "value": "5" - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x20002000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch deleted file mode 100644 index 6a7abd3..0000000 --- a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch +++ /dev/null @@ -1,60 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off set arch riscv:rv64 set remotetimeout 250"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/> -<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e51-arty.cfg"/> -<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> -<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> -<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/> -<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/> -<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> -<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> -<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> -<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/global_interrupts.elf"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="global_interrupts"/> -<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/global_interrupts"/> -</listAttribute> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> -<listEntry value="4"/> -</listAttribute> -<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> -<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> -</launchConfiguration> diff --git a/FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo 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"addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "16", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "16", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - }, - "interrupts": { - "switch0": { - "description": "SWITCH 0 Interrupt", - "value": "2" - }, - "switch1": { - "description": "SWITCH 1 Interrupt", - "value": "3" - }, - "switch2": { - "description": "SWITCH 2 Interrupt", - "value": "4" - }, - "switch3": { - "description": "SWITCH 3 Interrupt", - "value": "5" - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x20002000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
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8b382dc..0000000 --- a/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready 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Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch b/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch deleted file mode 100644 index 75f80ba..0000000 --- a/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch +++ /dev/null @@ -1,60 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" 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value="performance_counters"/> -<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/performance_counters"/> -</listAttribute> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> -<listEntry value="4"/> -</listAttribute> -<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="2147483648" label="0x80000000"/> </memoryBlockExpressionList> "/> -<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> -</launchConfiguration> diff --git a/FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject deleted file mode 100644 index 747f474..0000000 --- a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject +++ /dev/null @@ -1,211 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" 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<name>bsp/libwrap/sys/unlink.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/wait.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/weak_under_alias.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI> - </link> - <link> - <name>bsp/libwrap/sys/write.c</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/aon.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/clint.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/gpio.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/otp.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/plic.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/prci.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/pwm.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/spi.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> - </link> - <link> - <name>bsp/include/sifive/devices/uart.h</name> - <type>1</type> - <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> - </link> - </linkedResources> -</projectDescription> diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json deleted file mode 100644 index aac7a77..0000000 --- a/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json +++ /dev/null @@ -1,1230 +0,0 @@ -{ - "schemaVersion": "0.2.4", - "contentVersion": "0.2.0", - "headerVersion": "0.2.0", - "device": { - "e51arty": { - "displayName": "Core Complex E51 Arty", - "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.", - "supplier": { - "name": "sifive", - "id": "1", - "displayName": "SiFive", - "fullName": "SiFive, Inc.", - "contact": "info@sifive.com" - }, - "busWidth": "64", - "resetMask": "all", - "resetValue": "0x0000000000000000", - "access": "rw", - "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_", - "headerTypePrefix": "sifive_e51arty_", - "headerInterruptPrefix": "sifive_e51arty_interrupt_global_", - "headerInterruptEnumPrefix": "riscv_interrupts_global_", - "revision": "r0p0", - "numInterrupts": "26", - "priorityBits": "3", - "regWidth": "32", - "cores": { - "e51": { - "harts": "1", - "isa": "RV64IMAC", - "isaVersion": "2.2", - "mpu": "pmp", - "mmu": "none", - "localInterrupts": { - "machine_software": { - "description": "Machine Software Interrupt", - "value": "3" - }, - "machine_timer": { - "description": "Machine Timer Interrupt", - "value": "7" - }, - "machine_ext": { - "description": "Machine External Interrupt", - "value": "11" - }, - "0": { - "description": "Local Interrupt 0", - "value": "16" - }, - "1": { - "description": "Local Interrupt 1", - "value": "17" - }, - "2": { - "description": "Local Interrupt 2", - "value": "18" - }, - "3": { - "description": "Local Interrupt 3", - "value": "19" - }, - "4": { - "description": "Local Interrupt 4", - "value": "20" - }, - "5": { - "description": "Local Interrupt 5", - "value": "21" - }, - "6": { - "description": "Local Interrupt 6", - "value": "22" - }, - "7": { - "description": "Local Interrupt 7", - "value": "23" - }, - "8": { - "description": "Local Interrupt 8", - "value": "24" - }, - "9": { - "description": "Local Interrupt 9", - "value": "25" - }, - "10": { - "description": "Local Interrupt 10", - "value": "26" - }, - "11": { - "description": "Local Interrupt 11", - "value": "27" - }, - "12": { - "description": "Local Interrupt 12", - "value": "28" - }, - "13": { - "description": "Local Interrupt 13", - "value": "29" - }, - "14": { - "description": "Local Interrupt 14", - "value": "30" - }, - "15": { - "description": "Local Interrupt 15", - "value": "31" - } - }, - "numLocalInterrupts": "16" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - }, - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "regWidth": "64" - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "regWidth": "64" - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "27", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "16", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "16", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - }, - "interrupts": { - "switch0": { - "description": "SWITCH 0 Interrupt", - "value": "2" - }, - "switch1": { - "description": "SWITCH 1 Interrupt", - "value": "3" - }, - "switch2": { - "description": "SWITCH 2 Interrupt", - "value": "4" - }, - "switch3": { - "description": "SWITCH 3 Interrupt", - "value": "5" - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x20002000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "7" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "8" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "9" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "10" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "11" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "12" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "13" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "14" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "15" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "16" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "17" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "18" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "19" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "20" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "21" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "22" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x20000000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "1" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x20004000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "6" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x20005000", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "23" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "24" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "25" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "26" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg deleted file mode 100644 index 8b382dc..0000000 --- a/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg +++ /dev/null @@ -1,31 +0,0 @@ -# JTAG adapter setup -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a - -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -# Un-comment these two flash lines if you have a SPI flash and want to write -# it. -flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 -init -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z -} -halt -flash protect 0 64 last off -echo "Ready for Remote Connections" diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch deleted file mode 100644 index 6d29781..0000000 --- a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch +++ /dev/null @@ -1,60 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" 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value="Debug/demo_gpio.elf"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="demo_gpio"/> -<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"/> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/demo_gpio"/> -</listAttribute> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> -<listEntry value="4"/> -</listAttribute> -<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> -<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> -</launchConfiguration> diff --git a/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json b/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json deleted file mode 100644 index 1722e54..0000000 --- a/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json +++ /dev/null @@ -1,2325 +0,0 @@ -{ - "schemaVersion": "0.2.4", - "contentVersion": "0.2.0", - "headerVersion": "0.2.0", - "device": { - "fe310": { - "displayName": "Freedom E310-G000", - "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.", - "supplier": { - "name": "sifive", - "id": "1", - "displayName": "SiFive", - "fullName": "SiFive, Inc.", - "contact": "info@sifive.com" - }, - "busWidth": "32", - "resetMask": "all", - "resetValue": "0x00000000", - "access": "rw", - "headerGuardPrefix": "SIFIVE_DEVICES_FE310_", - "headerTypePrefix": "sifive_fe310_", - "headerInterruptPrefix": "sifive_fe310_interrupt_global_", - "headerInterruptEnumPrefix": "riscv_interrupts_global_", - "revision": "r0p0", - "numInterrupts": "51", - "priorityBits": "3", - "regWidth": "32", - "cores": { - "e31": { - "harts": "1", - "isa": "RV32IMAC", - "isaVersion": "2.2", - "mpu": "pmp", - "mmu": "none", - "localInterrupts": { - "machine_software": { - "description": "Machine Software Interrupt", - "value": "3" - }, - "machine_timer": { - "description": "Machine Timer Interrupt", - "value": "7" - }, - "machine_ext": { - "description": "Machine External Interrupt", - "value": "11" - } - }, - "numLocalInterrupts": "0" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - } - }, - "clusters": { - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "registers": { - "low": { - "description": "Machine Compare Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Compare Register High", - "addressOffset": "0x0004" - } - } - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "registers": { - "low": { - "description": "Machine Time Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Time Register High", - "addressOffset": "0x0004" - } - } - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "52", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "2", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "2", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - } - }, - "wdog": { - "description": "Watchdog Timer (WDT), part of Always-On Domain", - "baseAddress": "0x10000000", - "size": "0x0040", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Watchdog Configuration Register", - "addressOffset": "0x0000", - "fields": { - "scale": { - "description": "Watchdog counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "rsten": { - "description": "Watchdog full reset enable", - "bitOffset": "8", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "zerocmp": { - "description": "Watchdog zero on comparator", - "bitOffset": "9", - "bitWidth": "1" - }, - "enalways": { - "description": "Watchdog enable counter always", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "encoreawake": { - "description": "Watchdog counter only when awake", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmpip": { - "description": "Watchdog interrupt pending", - "bitOffset": "28", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Watchdog Count Register", - "addressOffset": "0x0008" - }, - "scale": { - "description": "Watchdog Scale Register", - "addressOffset": "0x0010", - "fields": { - "value": { - "description": "Watchdog scale value", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "feed": { - "description": "Watchdog Feed Address Register", - "addressOffset": "0x0018" - }, - "key": { - "description": "Watchdog Key Register", - "addressOffset": "0x001C" - }, - "cmp": { - "description": "Watchdog Compare Register", - "addressOffset": "0x0020", - "fields": { - "value": { - "description": "Watchdog compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - } - }, - "interrupts": { - "wdogcmp": { - "description": "Watchdog Compare Interrupt", - "value": "1" - } - } - }, - "rtc": { - "description": "Real-Time Clock (RTC), part of Always-On Domain", - "baseAddress": "0x10000040", - "size": "0x0030", - "resetMask": "none", - "registers": { - "cfg": { - "description": "RTC Configuration Register", - "addressOffset": "0x0000", - "fields": { - "scale": { - "description": "RTC clock rate scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "enalways": { - "description": "RTC counter enable", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmpip": { - "description": "RTC comparator interrupt pending", - "bitOffset": "28", - "bitWidth": "1", - "access": "r" - } - } - }, - "low": { - "description": "RTC Counter Register Low", - "addressOffset": "0x0008" - }, - "high": { - "description": "RTC Counter Register High", - "addressOffset": "0x000C", - "fields": { - "value": { - "description": "RTC counter register, high bits", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "scale": { - "description": "RTC Scale Register", - "addressOffset": "0x0010" - }, - "cmp": { - "description": "RTC Compare Register", - "addressOffset": "0x0020" - } - }, - "interrupts": { - "rtccmp": { - "description": "RTC Compare Interrupt", - "value": "2" - } - } - }, - "pmu": { - "description": "Power-Management Unit (PMU), part of Always-On Domain", - "baseAddress": "0x10000100", - "size": "0x0050", - "resetMask": "none", - "registers": { - "wakeupi": { - "description": "Wakeup program instruction Registers", - "addressOffset": "0x0000", - "arraySize": "8" - }, - "sleepi": { - "description": "Sleep Program Instruction Registers", - "addressOffset": "0x0020", - "arraySize": "8" - }, - "ie": { - "description": "PMU Interrupt Enables Register", - "addressOffset": "0x0040", - "fields": { - "rtc": { - "description": "RTC Comparator active", - "bitOffset": "1", - "bitWidth": "1" - }, - "dwakeup": { - "description": "dwakeup_n pin active", - "bitOffset": "2", - "bitWidth": "1" - } - } - }, - "cause": { - "description": "PMU Wakeup Cause Register", - "addressOffset": "0x0044", - "fields": { - "wakeupcause": { - "description": "Wakeup cause", - "bitOffset": "0", - "bitWidth": "2", - "access": "r", - "enumerations": { - "wakeupcause-enum": { - "description": "Wakeup Cause Values Enumeration", - "values": { - "0": { - "displayName": "reset", - "description": "Reset Wakeup" - }, - "1": { - "displayName": "rtc", - "description": "RTC Wakeup" - }, - "2": { - "displayName": "dwakeup", - "description": "Digital input Wakeup" - }, - "*": { - "displayName": "undefined" - } - } - } - } - }, - "resetcause": { - "description": "Reset cause", - "bitOffset": "8", - "bitWidth": "2", - "access": "r", - "enumerations": { - "resetcause-enum": { - "description": "Reset Cause Values Enumeration", - "values": { - "1": { - "displayName": "external", - "description": "External reset" - }, - "2": { - "displayName": "watchdog", - "description": "Watchdog timer reset" - }, - "*": { - "displayName": "undefined" - } - } - } - } - } - } - }, - "sleep": { - "description": "PMU Initiate Sleep Sequence Register", - "addressOffset": "0x0048" - }, - "key": { - "description": "PMU Key Register", - "addressOffset": "0x004C" - } - } - }, - "aon": { - "description": "Always-On (AON) Domain", - "baseAddress": "0x10000070", - "size": "0x0090", - "resetMask": "none", - "registers": { - "lfrosccfg": { - "description": "Internal Programmable Low-Frequency Ring Oscillator Register", - "addressOffset": "0x0000", - "fields": { - "div": { - "description": "LFROSC divider", - "bitOffset": "0", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x04" - }, - "trim": { - "description": "LFROSC trim value", - "bitOffset": "16", - "bitWidth": "5", - "resetMask": "all", - "resetValue": "0x10" - }, - "en": { - "description": "LFROSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "LFROSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "backup": { - "description": "Backup Registers", - "addressOffset": "0x0010", - "arraySize": "32" - } - } - }, - "prci": { - "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral", - "baseAddress": "0x10008000", - "size": "0x8000", - "registers": { - "hfrosccfg": { - "description": "Internal Trimmable Programmable 72 MHz Oscillator Register", - "addressOffset": "0x0000", - "fields": { - "div": { - "description": "HFROSC divider", - "bitOffset": "0", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x04" - }, - "trim": { - "description": "HFROSC trim value", - "bitOffset": "16", - "bitWidth": "5", - "resetMask": "all", - "resetValue": "0x10" - }, - "en": { - "description": "HFROSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "HFROSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "hfxosccfg": { - "description": "External 16 MHz Crystal Oscillator Register", - "addressOffset": "0x0004", - "fields": { - "en": { - "description": "HFXOSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "HFXOSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "pllcfg": { - "description": "Internal High-Frequency PLL (HFPLL) Register", - "addressOffset": "0x0008", - "fields": { - "r": { - "description": "PLL R input divider value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "pllr-enum": { - "description": "Reference Clock R Divide Ratio Enumeration", - "values": { - "0": { - "displayName": "/1", - "headerName": "div1", - "description": "Unchanged" - }, - "1": { - "displayName": "/2", - "headerName": "div2", - "description": "Divided by 2" - }, - "2": { - "displayName": "/3", - "headerName": "div3", - "description": "Divided by 3" - }, - "3": { - "displayName": "/4", - "headerName": "div4", - "description": "Divided by 4" - } - } - } - } - }, - "f": { - "description": "PLL F multiplier value", - "bitOffset": "4", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x1F", - "enumerations": { - "pllf-enum": { - "description": "Reference Clock F Multiplier Ratio Enumeration", - "values": { - "0": { - "displayName": "*2", - "headerName": "mul2", - "description": "Multiplied by 2" - }, - "1": { - "displayName": "*4", - "headerName": "mul4", - "description": "Multiplied by 4" - }, - "2": { - "displayName": "*6", - "headerName": "mul6", - "description": "Multiplied by 6" - }, - "3": { - "displayName": "*8", - "headerName": "mul8", - "description": "Multiplied by 8" - }, - "4": { - "displayName": "*10", - "headerName": "mul10", - "description": "Multiplied by 10" - }, - "5": { - "displayName": "*12", - "headerName": "mul12", - "description": "Multiplied by 12" - }, - "6": { - "displayName": "*14", - "headerName": "mul14", - "description": "Multiplied by 14" - }, - "7": { - "displayName": "*16", - "headerName": "mul16", - "description": "Multiplied by 16" - }, - "8": { - "displayName": "*18", - "headerName": "mul18", - "description": "Multiplied by 18" - }, - "9": { - "displayName": "*20", - "headerName": "mul20", - "description": "Multiplied by 20" - }, - "10": { - "displayName": "*22", - "headerName": "mul22", - "description": "Multiplied by 22" - }, - "11": { - "displayName": "*24", - "headerName": "mul24", - "description": "Multiplied by 24" - }, - "12": { - "displayName": "*26", - "headerName": "mul26", - "description": "Multiplied by 26" - }, - "13": { - "displayName": "*28", - "headerName": "mul28", - "description": "Multiplied by 28" - }, - "14": { - "displayName": "*30", - "headerName": "mul30", - "description": "Multiplied by 30" - }, - "15": { - "displayName": "*32", - "headerName": "mul32", - "description": "Multiplied by 32" - }, - "16": { - "displayName": "*34", - "headerName": "mul34", - "description": "Multiplied by 34" - }, - "17": { - "displayName": "*36", - "headerName": "mul36", - "description": "Multiplied by 36" - }, - "18": { - "displayName": "*38", - "headerName": "mul38", - "description": "Multiplied by 38" - }, - "19": { - "displayName": "*40", - "headerName": "mul40", - "description": "Multiplied by 40" - }, - "20": { - "displayName": "*42", - "headerName": "mul42", - "description": "Multiplied by 42" - }, - "21": { - "displayName": "*44", - "headerName": "mul44", - "description": "Multiplied by 44" - }, - "22": { - "displayName": "*46", - "headerName": "mul46", - "description": "Multiplied by 46" - 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}, - "53": { - "displayName": "*108", - "headerName": "mul108", - "description": "Multiplied by 108" - }, - "54": { - "displayName": "*110", - "headerName": "mul110", - "description": "Multiplied by 110" - }, - "55": { - "displayName": "*112", - "headerName": "mul112", - "description": "Multiplied by 112" - }, - "56": { - "displayName": "*114", - "headerName": "mul114", - "description": "Multiplied by 114" - }, - "57": { - "displayName": "*116", - "headerName": "mul116", - "description": "Multiplied by 116" - }, - "58": { - "displayName": "*118", - "headerName": "mul118", - "description": "Multiplied by 118" - }, - "59": { - "displayName": "*120", - "headerName": "mul120", - "description": "Multiplied by 120" - }, - "60": { - "displayName": "*122", - "headerName": "mul122", - "description": "Multiplied by 122" - }, - "61": { - "displayName": "*124", - "headerName": "mul124", - "description": "Multiplied by 124" - }, - "62": { - "displayName": "*126", - "headerName": "mul126", - "description": "Multiplied by 126" - }, - "63": { - "displayName": "*128", - "headerName": "mul128", - "description": "Multiplied by 128" - } - } - } - } - }, - "q": { - "description": "PLL Q output divider value", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x3", - "enumerations": { - "pllq-enum": { - "description": "Reference Clock Q Divide Ratio Enumeration", - "values": { - "*": { - "displayName": "n/a", - "description": "Not supported" - }, - "1": { - "displayName": "/2", - "headerName": "div2", - "description": "Divided by 2" - }, - "2": { - "displayName": "/4", - "headerName": "div4", - "description": "Divided by 4" - }, - "3": { - "displayName": "/8", - "headerName": "div8", - "description": "Divided by 8" - } - } - } - } - }, - "sel": { - "description": "PLL select", - "bitOffset": "16", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "refsel": { - "description": "PLL reference select", - "bitOffset": "17", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "bypass": { - "description": "PLL bypass", - "bitOffset": "18", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "lock": { - "description": "PLL lock indicator", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "plloutdiv": { - "description": "PLL Output Divider", - "addressOffset": "0x000C" - } - } - }, - "otp": { - "description": "One-Time Programmable Memory (OTP) Peripheral", - "baseAddress": "0x10010000", - "size": "0x1000", - "registers": { - "lock": { - "description": "Programmed-I/O Lock Register", - "addressOffset": "0x0000" - }, - "ck": { - "description": "Device Clock Signal Register", - "addressOffset": "0x0004" - }, - "oe": { - "description": "Device Output-Enable Signal Register", - "addressOffset": "0x0008" - }, - "sel": { - "description": "Device Chip-Select Signal Register", - "addressOffset": "0x000C" - }, - "we": { - "description": "Device Write-Enable Signal Register", - "addressOffset": "0x0010" - }, - "mr": { - "description": "Device Mode Register", - "addressOffset": "0x0014" - }, - "mrr": { - "description": "Read-Voltage Regulator Control Register", - "addressOffset": "0x0018" - }, - "mpp": { - "description": "Write-Voltage Charge Pump Control Register", - "addressOffset": "0x001C" - }, - "vrren": { - "description": "Read-Voltage Enable Register", - "addressOffset": "0x0020" - }, - "vppen": { - "description": "Write-Voltage Enable Register", - "addressOffset": "0x0024" - }, - "a": { - "description": "Device Address Register", - "addressOffset": "0x0028" - }, - "d": { - "description": "Device Data Input Register", - "addressOffset": "0x002C" - }, - "q": { - "description": "Device Data Output Register", - "addressOffset": "0x0030" - }, - "rsctrl": { - "description": "Read Sequencer Control Register", - "addressOffset": "0x0034", - "fields": { - "scale": { - "description": "OTP timescale", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x1" - }, - "tas": { - "description": "Address setup time", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "trp": { - "description": "Read pulse time", - "bitOffset": "4", - "bitWidth": "1" - }, - "tracc": { - "description": "Read access time", - "bitOffset": "5", - "bitWidth": "1" - } - } - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x10012000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "8" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "9" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "10" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "11" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "12" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "13" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "14" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "15" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "16" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "17" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "18" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "19" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "20" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "21" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "22" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "23" - }, - "gpio16": { - "description": "GPIO16 Interrupt", - "value": "24" - }, - "gpio17": { - "description": "GPIO17 Interrupt", - "value": "25" - }, - "gpio18": { - "description": "GPIO18 Interrupt", - "value": "26" - }, - "gpio19": { - "description": "GPIO19 Interrupt", - "value": "27" - }, - "gpio20": { - "description": "GPIO20 Interrupt", - "value": "28" - }, - "gpio21": { - "description": "GPIO21 Interrupt", - "value": "29" - }, - "gpio22": { - "description": "GPIO22 Interrupt", - "value": "30" - }, - "gpio23": { - "description": "GPIO23 Interrupt", - "value": "31" - }, - "gpio24": { - "description": "GPIO24 Interrupt", - "value": "32" - }, - "gpio25": { - "description": "GPIO25 Interrupt", - "value": "33" - }, - "gpio26": { - "description": "GPIO26 Interrupt", - "value": "34" - }, - "gpio27": { - "description": "GPIO27 Interrupt", - "value": "35" - }, - "gpio28": { - "description": "GPIO28 Interrupt", - "value": "36" - }, - "gpio29": { - "description": "GPIO29 Interrupt", - "value": "37" - }, - "gpio30": { - "description": "GPIO30 Interrupt", - "value": "38" - }, - "gpio31": { - "description": "GPIO31 Interrupt", - "value": "39" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x10013000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "3" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x10014000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "5" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10015000", - "size": "0x1000", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - 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}, - "pwm2cmp3": { - "description": "PWM2 Compare 3 Interrupt", - "value": "51" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg deleted file mode 100644 index b0a8e26..0000000 --- a/FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg +++ /dev/null @@ -1,34 +0,0 @@ -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 - -#Reset Stretcher logic on FE310 is ~1 second long -#This doesn't apply if you use -# ftdi_set_signal, but still good to document -#adapter_nsrst_delay 1500 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME -init -#reset -- This type of reset is not implemented yet -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z - #Wait for the reset stretcher - #It will work without this, but - #will incur lots of delays for later commands. - sleep 1500 -} -halt -flash protect 0 64 last off diff --git a/FreedomStudio/HiFive1/dhrystone/.cproject b/FreedomStudio/HiFive1/dhrystone/.cproject deleted file mode 100644 index ca95225..0000000 --- a/FreedomStudio/HiFive1/dhrystone/.cproject +++ /dev/null @@ -1,211 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" 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"value": "11" - } - }, - "numLocalInterrupts": "0" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - } - }, - "clusters": { - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "registers": { - "low": { - "description": "Machine Compare Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Compare Register High", - "addressOffset": "0x0004" - } - } - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "registers": { - "low": { - "description": "Machine Time Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Time Register High", - "addressOffset": "0x0004" - } - } - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "52", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "2", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "2", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - } - }, - "wdog": { - "description": "Watchdog Timer (WDT), part of Always-On Domain", - "baseAddress": "0x10000000", - "size": "0x0040", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Watchdog Configuration Register", - "addressOffset": "0x0000", - "fields": { - "scale": { - "description": "Watchdog counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "rsten": { - "description": "Watchdog full reset enable", - "bitOffset": "8", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "zerocmp": { - "description": "Watchdog zero on comparator", - "bitOffset": "9", - "bitWidth": "1" - }, - "enalways": { - "description": "Watchdog enable counter always", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "encoreawake": { - "description": "Watchdog counter only when awake", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmpip": { - "description": "Watchdog interrupt pending", - "bitOffset": "28", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Watchdog Count Register", - "addressOffset": "0x0008" - }, - "scale": { - "description": "Watchdog Scale Register", - "addressOffset": "0x0010", - "fields": { - "value": { - "description": "Watchdog scale value", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "feed": { - "description": "Watchdog Feed Address Register", - "addressOffset": "0x0018" - }, - "key": { - "description": "Watchdog Key Register", - "addressOffset": "0x001C" - }, - "cmp": { - "description": "Watchdog Compare Register", - "addressOffset": "0x0020", - "fields": { - "value": { - "description": "Watchdog compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - } - }, - "interrupts": { - "wdogcmp": { - "description": "Watchdog Compare Interrupt", - "value": "1" - } - } - }, - "rtc": { - "description": "Real-Time Clock (RTC), part of Always-On Domain", - "baseAddress": "0x10000040", - "size": "0x0030", - "resetMask": "none", - "registers": { - "cfg": { - "description": "RTC Configuration Register", - "addressOffset": "0x0000", - "fields": { - "scale": { - "description": "RTC clock rate scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "enalways": { - "description": "RTC counter enable", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmpip": { - "description": "RTC comparator interrupt pending", - "bitOffset": "28", - "bitWidth": "1", - "access": "r" - } - } - }, - "low": { - "description": "RTC Counter Register Low", - "addressOffset": "0x0008" - }, - "high": { - "description": "RTC Counter Register High", - "addressOffset": "0x000C", - "fields": { - "value": { - "description": "RTC counter register, high bits", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "scale": { - "description": "RTC Scale Register", - "addressOffset": "0x0010" - }, - "cmp": { - "description": "RTC Compare Register", - "addressOffset": "0x0020" - } - }, - "interrupts": { - "rtccmp": { - "description": "RTC Compare Interrupt", - "value": "2" - } - } - }, - "pmu": { - "description": "Power-Management Unit (PMU), part of Always-On Domain", - "baseAddress": "0x10000100", - "size": "0x0050", - "resetMask": "none", - "registers": { - "wakeupi": { - "description": "Wakeup program instruction Registers", - "addressOffset": "0x0000", - "arraySize": "8" - }, - "sleepi": { - "description": "Sleep Program Instruction Registers", - "addressOffset": "0x0020", - "arraySize": "8" - }, - "ie": { - "description": "PMU Interrupt Enables Register", - "addressOffset": "0x0040", - "fields": { - "rtc": { - "description": "RTC Comparator active", - "bitOffset": "1", - "bitWidth": "1" - }, - "dwakeup": { - "description": "dwakeup_n pin active", - "bitOffset": "2", - "bitWidth": "1" - } - } - }, - "cause": { - "description": "PMU Wakeup Cause Register", - "addressOffset": "0x0044", - "fields": { - "wakeupcause": { - "description": "Wakeup cause", - "bitOffset": "0", - "bitWidth": "2", - "access": "r", - "enumerations": { - "wakeupcause-enum": { - "description": "Wakeup Cause Values Enumeration", - "values": { - "0": { - "displayName": "reset", - "description": "Reset Wakeup" - }, - "1": { - "displayName": "rtc", - "description": "RTC Wakeup" - }, - "2": { - "displayName": "dwakeup", - "description": "Digital input Wakeup" - }, - "*": { - "displayName": "undefined" - } - } - } - } - }, - "resetcause": { - "description": "Reset cause", - "bitOffset": "8", - "bitWidth": "2", - "access": "r", - "enumerations": { - "resetcause-enum": { - "description": "Reset Cause Values Enumeration", - "values": { - "1": { - "displayName": "external", - "description": "External reset" - }, - "2": { - "displayName": "watchdog", - "description": "Watchdog timer reset" - }, - "*": { - "displayName": "undefined" - } - } - } - } - } - } - }, - "sleep": { - "description": "PMU Initiate Sleep Sequence Register", - "addressOffset": "0x0048" - }, - "key": { - "description": "PMU Key Register", - "addressOffset": "0x004C" - } - } - }, - "aon": { - "description": "Always-On (AON) Domain", - "baseAddress": "0x10000070", - "size": "0x0090", - "resetMask": "none", - "registers": { - "lfrosccfg": { - "description": "Internal Programmable Low-Frequency Ring Oscillator Register", - "addressOffset": "0x0000", - "fields": { - "div": { - "description": "LFROSC divider", - "bitOffset": "0", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x04" - }, - "trim": { - "description": "LFROSC trim value", - "bitOffset": "16", - "bitWidth": "5", - "resetMask": "all", - "resetValue": "0x10" - }, - "en": { - "description": "LFROSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "LFROSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "backup": { - "description": "Backup Registers", - "addressOffset": "0x0010", - "arraySize": "32" - } - } - }, - "prci": { - "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral", - "baseAddress": "0x10008000", - "size": "0x8000", - "registers": { - "hfrosccfg": { - "description": "Internal Trimmable Programmable 72 MHz Oscillator Register", - "addressOffset": "0x0000", - "fields": { - "div": { - "description": "HFROSC divider", - "bitOffset": "0", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x04" - }, - "trim": { - "description": "HFROSC trim value", - "bitOffset": "16", - "bitWidth": "5", - "resetMask": "all", - "resetValue": "0x10" - }, - "en": { - "description": "HFROSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "HFROSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "hfxosccfg": { - "description": "External 16 MHz Crystal Oscillator Register", - "addressOffset": "0x0004", - "fields": { - "en": { - "description": "HFXOSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "HFXOSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "pllcfg": { - "description": "Internal High-Frequency PLL (HFPLL) Register", - "addressOffset": "0x0008", - "fields": { - "r": { - "description": "PLL R input divider value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "pllr-enum": { - "description": "Reference Clock R Divide Ratio Enumeration", - "values": { - "0": { - "displayName": "/1", - "headerName": "div1", - "description": "Unchanged" - }, - "1": { - "displayName": "/2", - "headerName": "div2", - "description": "Divided by 2" - }, - "2": { - "displayName": "/3", - "headerName": "div3", - "description": "Divided by 3" - }, - "3": { - "displayName": "/4", - "headerName": "div4", - "description": "Divided by 4" - } - } - } - } - }, - "f": { - "description": "PLL F multiplier value", - "bitOffset": "4", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x1F", - "enumerations": { - "pllf-enum": { - "description": "Reference Clock F Multiplier Ratio Enumeration", - "values": { - "0": { - "displayName": "*2", - "headerName": "mul2", - "description": "Multiplied by 2" - }, - "1": { - "displayName": "*4", - "headerName": "mul4", - "description": "Multiplied by 4" - }, - "2": { - "displayName": "*6", - "headerName": "mul6", - "description": "Multiplied by 6" - }, - "3": { - "displayName": "*8", - "headerName": "mul8", - "description": "Multiplied by 8" - }, - "4": { - "displayName": "*10", - "headerName": "mul10", - "description": "Multiplied by 10" - }, - "5": { - "displayName": "*12", - "headerName": "mul12", - "description": "Multiplied by 12" - }, - "6": { - "displayName": "*14", - "headerName": "mul14", - "description": "Multiplied by 14" - }, - "7": { - "displayName": "*16", - "headerName": "mul16", - "description": "Multiplied by 16" - }, - "8": { - "displayName": "*18", - "headerName": "mul18", - "description": "Multiplied by 18" - }, - "9": { - "displayName": "*20", - "headerName": "mul20", - "description": "Multiplied by 20" - }, - "10": { - "displayName": "*22", - "headerName": "mul22", - "description": "Multiplied by 22" - }, - "11": { - "displayName": "*24", - "headerName": "mul24", - "description": "Multiplied by 24" - }, - "12": { - "displayName": "*26", - "headerName": "mul26", - "description": "Multiplied by 26" - }, - "13": { - "displayName": "*28", - "headerName": "mul28", - "description": "Multiplied by 28" - }, - "14": { - "displayName": "*30", - "headerName": "mul30", - "description": "Multiplied by 30" - }, - "15": { - "displayName": "*32", - "headerName": "mul32", - "description": "Multiplied by 32" - }, - "16": { - "displayName": "*34", - "headerName": "mul34", - "description": "Multiplied by 34" - }, - "17": { - "displayName": "*36", - "headerName": "mul36", - "description": "Multiplied by 36" - }, - "18": { - "displayName": "*38", - "headerName": "mul38", - "description": "Multiplied by 38" - }, - "19": { - "displayName": "*40", - "headerName": "mul40", - "description": "Multiplied by 40" - }, - "20": { - "displayName": "*42", - "headerName": "mul42", - "description": "Multiplied by 42" - }, - "21": { - "displayName": "*44", - "headerName": "mul44", - "description": "Multiplied by 44" - }, - "22": { - "displayName": "*46", - "headerName": "mul46", - "description": "Multiplied by 46" - }, - "23": { - "displayName": "*48", - "headerName": "mul48", - "description": "Multiplied by 48" - }, - "24": { - "displayName": "*50", - "headerName": "mul50", - "description": "Multiplied by 50" - }, - "25": { - "displayName": "*52", - "headerName": "mul52", - "description": "Multiplied by 52" - }, - "26": { - "displayName": "*54", - "headerName": "mul54", - "description": "Multiplied by 54" - }, - "27": { - "displayName": "*56", - "headerName": "mul56", - "description": "Multiplied by 56" - }, - "28": { - "displayName": "*58", - "headerName": "mul58", - "description": "Multiplied by 58" - }, - "29": { - "displayName": "*60", - "headerName": "mul60", - "description": "Multiplied by 60" - }, - "30": { - "displayName": "*62", - "headerName": "mul62", - "description": "Multiplied by 62" - }, - "31": { - "displayName": "*64", - "headerName": "mul64", - "description": "Multiplied by 64" - }, - "32": { - "displayName": "*66", - "headerName": "mul66", - "description": "Multiplied by 66" - }, - "33": { - "displayName": "*68", - "headerName": "mul68", - "description": "Multiplied by 68" - }, - "34": { - "displayName": "*70", - "headerName": "mul70", - "description": "Multiplied by 70" - }, - "35": { - "displayName": "*72", - "headerName": "mul72", - "description": "Multiplied by 72" - }, - "36": { - "displayName": "*74", - "headerName": "mul74", - "description": "Multiplied by 74" - }, - "37": { - "displayName": "*76", - "headerName": "mul76", - "description": "Multiplied by 76" - }, - "38": { - "displayName": "*78", - "headerName": "mul78", - "description": "Multiplied by 78" - }, - "39": { - "displayName": "*80", - "headerName": "mul80", - "description": "Multiplied by 80" - }, - "40": { - "displayName": "*82", - "headerName": "mul82", - "description": "Multiplied by 82" - }, - "41": { - "displayName": "*84", - "headerName": "mul84", - "description": "Multiplied by 84" - }, - "42": { - "displayName": "*86", - "headerName": "mul86", - "description": "Multiplied by 86" - }, - "43": { - "displayName": "*88", - "headerName": "mul88", - "description": "Multiplied by 88" - }, - "44": { - "displayName": "*90", - "headerName": "mul90", - "description": "Multiplied by 90" - }, - "45": { - "displayName": "*92", - "headerName": "mul92", - "description": "Multiplied by 92" - }, - "46": { - "displayName": "*94", - "headerName": "mul94", - "description": "Multiplied by 94" - }, - "47": { - "displayName": "*96", - "headerName": "mul96", - "description": "Multiplied by 96" - }, - "48": { - "displayName": "*98", - "headerName": "mul98", - "description": "Multiplied by 98" - }, - "49": { - "displayName": "*100", - "headerName": "mul100", - "description": "Multiplied by 100" - }, - "50": { - "displayName": "*102", - "headerName": "mul102", - "description": "Multiplied by 102" - }, - "51": { - "displayName": "*104", - "headerName": "mul104", - "description": "Multiplied by 104" - }, - "52": { - "displayName": "*106", - "headerName": "mul106", - "description": "Multiplied by 106" - }, - "53": { - "displayName": "*108", - "headerName": "mul108", - "description": "Multiplied by 108" - }, - "54": { - "displayName": "*110", - "headerName": "mul110", - "description": "Multiplied by 110" - }, - "55": { - "displayName": "*112", - "headerName": "mul112", - "description": "Multiplied by 112" - }, - "56": { - "displayName": "*114", - "headerName": "mul114", - "description": "Multiplied by 114" - }, - "57": { - "displayName": "*116", - "headerName": "mul116", - "description": "Multiplied by 116" - }, - "58": { - "displayName": "*118", - "headerName": "mul118", - "description": "Multiplied by 118" - }, - "59": { - "displayName": "*120", - "headerName": "mul120", - "description": "Multiplied by 120" - }, - "60": { - "displayName": "*122", - "headerName": "mul122", - "description": "Multiplied by 122" - }, - "61": { - "displayName": "*124", - "headerName": "mul124", - "description": "Multiplied by 124" - }, - "62": { - "displayName": "*126", - "headerName": "mul126", - "description": "Multiplied by 126" - }, - "63": { - "displayName": "*128", - "headerName": "mul128", - "description": "Multiplied by 128" - } - } - } - } - }, - "q": { - "description": "PLL Q output divider value", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x3", - "enumerations": { - "pllq-enum": { - "description": "Reference Clock Q Divide Ratio Enumeration", - "values": { - "*": { - "displayName": "n/a", - "description": "Not supported" - }, - "1": { - "displayName": "/2", - "headerName": "div2", - "description": "Divided by 2" - }, - "2": { - "displayName": "/4", - "headerName": "div4", - "description": "Divided by 4" - }, - "3": { - "displayName": "/8", - "headerName": "div8", - "description": "Divided by 8" - } - } - } - } - }, - "sel": { - "description": "PLL select", - "bitOffset": "16", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "refsel": { - "description": "PLL reference select", - "bitOffset": "17", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "bypass": { - "description": "PLL bypass", - "bitOffset": "18", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "lock": { - "description": "PLL lock indicator", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "plloutdiv": { - "description": "PLL Output Divider", - "addressOffset": "0x000C" - } - } - }, - "otp": { - "description": "One-Time Programmable Memory (OTP) Peripheral", - "baseAddress": "0x10010000", - "size": "0x1000", - "registers": { - "lock": { - "description": "Programmed-I/O Lock Register", - "addressOffset": "0x0000" - }, - "ck": { - "description": "Device Clock Signal Register", - "addressOffset": "0x0004" - }, - "oe": { - "description": "Device Output-Enable Signal Register", - "addressOffset": "0x0008" - }, - "sel": { - "description": "Device Chip-Select Signal Register", - "addressOffset": "0x000C" - }, - "we": { - "description": "Device Write-Enable Signal Register", - "addressOffset": "0x0010" - }, - "mr": { - "description": "Device Mode Register", - "addressOffset": "0x0014" - }, - "mrr": { - "description": "Read-Voltage Regulator Control Register", - "addressOffset": "0x0018" - }, - "mpp": { - "description": "Write-Voltage Charge Pump Control Register", - "addressOffset": "0x001C" - }, - "vrren": { - "description": "Read-Voltage Enable Register", - "addressOffset": "0x0020" - }, - "vppen": { - "description": "Write-Voltage Enable Register", - "addressOffset": "0x0024" - }, - "a": { - "description": "Device Address Register", - "addressOffset": "0x0028" - }, - "d": { - "description": "Device Data Input Register", - "addressOffset": "0x002C" - }, - "q": { - "description": "Device Data Output Register", - "addressOffset": "0x0030" - }, - "rsctrl": { - "description": "Read Sequencer Control Register", - "addressOffset": "0x0034", - "fields": { - "scale": { - "description": "OTP timescale", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x1" - }, - "tas": { - "description": "Address setup time", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "trp": { - "description": "Read pulse time", - "bitOffset": "4", - "bitWidth": "1" - }, - "tracc": { - "description": "Read access time", - "bitOffset": "5", - "bitWidth": "1" - } - } - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x10012000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "8" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "9" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "10" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "11" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "12" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "13" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "14" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "15" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "16" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "17" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "18" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "19" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "20" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "21" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "22" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "23" - }, - "gpio16": { - "description": "GPIO16 Interrupt", - "value": "24" - }, - "gpio17": { - "description": "GPIO17 Interrupt", - "value": "25" - }, - "gpio18": { - "description": "GPIO18 Interrupt", - "value": "26" - }, - "gpio19": { - "description": "GPIO19 Interrupt", - "value": "27" - }, - "gpio20": { - "description": "GPIO20 Interrupt", - "value": "28" - }, - "gpio21": { - "description": "GPIO21 Interrupt", - "value": "29" - }, - "gpio22": { - "description": "GPIO22 Interrupt", - "value": "30" - }, - "gpio23": { - "description": "GPIO23 Interrupt", - "value": "31" - }, - "gpio24": { - "description": "GPIO24 Interrupt", - "value": "32" - }, - "gpio25": { - "description": "GPIO25 Interrupt", - "value": "33" - }, - "gpio26": { - "description": "GPIO26 Interrupt", - "value": "34" - }, - "gpio27": { - "description": "GPIO27 Interrupt", - "value": "35" - }, - "gpio28": { - "description": "GPIO28 Interrupt", - "value": "36" - }, - "gpio29": { - "description": "GPIO29 Interrupt", - "value": "37" - }, - "gpio30": { - "description": "GPIO30 Interrupt", - "value": "38" - }, - "gpio31": { - "description": "GPIO31 Interrupt", - "value": "39" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x10013000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "3" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x10014000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "5" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10015000", - "size": "0x1000", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "40" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "41" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "42" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "43" - } - } - }, - "uart1": { - "baseAddress": "0x10023000", - "derivedFrom": "uart0", - "groupName": "uart", - "interrupts": { - "uart1": { - "description": "UART1 Interrupt", - "value": "4" - } - } - }, - "spi1": { - "baseAddress": "0x10024000", - "derivedFrom": "spi0", - "groupName": "spi", - "interrupts": { - "spi1": { - "description": "SPI1 Interrupt", - "value": "6" - } - } - }, - "pwm1": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10025000", - "groupName": "pwm", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - } - }, - "interrupts": { - "pwm1cmp0": { - "description": "PWM1 Compare 0 Interrupt", - "value": "44" - }, - "pwm1cmp1": { - "description": "PWM1 Compare 1 Interrupt", - "value": "45" - }, - "pwm1cmp2": { - "description": "PWM1 Compare 2 Interrupt", - "value": "46" - }, - "pwm1cmp3": { - "description": "PWM1 Compare 3 Interrupt", - "value": "47" - } - } - }, - "spi2": { - "baseAddress": "0x10034000", - "derivedFrom": "spi0", - "groupName": "spi", - "interrupts": { - "spi2": { - "description": "SPI2 Interrupt", - "value": "7" - } - } - }, - "pwm2": { - "baseAddress": "0x10035000", - "derivedFrom": "pwm1", - "groupName": "pwm", - "interrupts": { - "pwm2cmp0": { - "description": "PWM2 Compare 0 Interrupt", - "value": "48" - }, - "pwm2cmp1": { - "description": "PWM2 Compare 1 Interrupt", - "value": "49" - }, - "pwm2cmp2": { - "description": "PWM2 Compare 2 Interrupt", - "value": "50" - }, - "pwm2cmp3": { - "description": "PWM2 Compare 3 Interrupt", - "value": "51" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg deleted file mode 100644 index b0a8e26..0000000 --- a/FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg +++ /dev/null @@ -1,34 +0,0 @@ -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 - -#Reset Stretcher logic on FE310 is ~1 second long -#This doesn't apply if you use -# ftdi_set_signal, but still good to document -#adapter_nsrst_delay 1500 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME -init -#reset -- This type of reset is not implemented yet -if {[ info exists pulse_srst]} { - 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"description": "Multiplied by 6" - }, - "3": { - "displayName": "*8", - "headerName": "mul8", - "description": "Multiplied by 8" - }, - "4": { - "displayName": "*10", - "headerName": "mul10", - "description": "Multiplied by 10" - }, - "5": { - "displayName": "*12", - "headerName": "mul12", - "description": "Multiplied by 12" - }, - "6": { - "displayName": "*14", - "headerName": "mul14", - "description": "Multiplied by 14" - }, - "7": { - "displayName": "*16", - "headerName": "mul16", - "description": "Multiplied by 16" - }, - "8": { - "displayName": "*18", - "headerName": "mul18", - "description": "Multiplied by 18" - }, - "9": { - "displayName": "*20", - "headerName": "mul20", - "description": "Multiplied by 20" - }, - "10": { - "displayName": "*22", - "headerName": "mul22", - "description": "Multiplied by 22" - }, - "11": { - "displayName": "*24", - "headerName": "mul24", - "description": "Multiplied by 24" - }, - "12": { - "displayName": "*26", - "headerName": "mul26", - "description": "Multiplied by 26" - }, - "13": { - "displayName": "*28", - "headerName": "mul28", - "description": "Multiplied by 28" - }, - "14": { - "displayName": "*30", - "headerName": "mul30", - "description": "Multiplied by 30" - }, - "15": { - "displayName": "*32", - "headerName": "mul32", - "description": "Multiplied by 32" - }, - "16": { - "displayName": "*34", - "headerName": "mul34", - "description": "Multiplied by 34" - }, - "17": { - "displayName": "*36", - "headerName": "mul36", - "description": "Multiplied by 36" - }, - "18": { - "displayName": "*38", - "headerName": "mul38", - "description": "Multiplied by 38" - }, - "19": { - "displayName": "*40", - "headerName": "mul40", - "description": "Multiplied by 40" - }, - "20": { - "displayName": "*42", - "headerName": "mul42", - "description": "Multiplied by 42" - }, - "21": { - "displayName": "*44", - "headerName": "mul44", - "description": "Multiplied by 44" - }, - "22": { - "displayName": "*46", - "headerName": "mul46", - "description": "Multiplied by 46" - }, - "23": { - "displayName": "*48", - "headerName": "mul48", - "description": "Multiplied by 48" - }, - "24": { - "displayName": "*50", - "headerName": "mul50", - "description": "Multiplied by 50" - }, - "25": { - "displayName": "*52", - "headerName": "mul52", - "description": "Multiplied by 52" - }, - "26": { - "displayName": "*54", - "headerName": "mul54", - "description": "Multiplied by 54" - }, - "27": { - "displayName": "*56", - "headerName": "mul56", - "description": "Multiplied by 56" - }, - "28": { - "displayName": "*58", - "headerName": "mul58", - "description": "Multiplied by 58" - }, - "29": { - "displayName": "*60", - "headerName": "mul60", - "description": "Multiplied by 60" - }, - "30": { - "displayName": "*62", - "headerName": "mul62", - "description": "Multiplied by 62" - }, - "31": { - "displayName": "*64", - "headerName": "mul64", - "description": "Multiplied by 64" - }, - "32": { - "displayName": "*66", - "headerName": "mul66", - "description": "Multiplied by 66" - }, - "33": { - "displayName": "*68", - "headerName": "mul68", - "description": "Multiplied by 68" - }, - "34": { - "displayName": "*70", - "headerName": "mul70", - "description": "Multiplied by 70" - }, - "35": { - "displayName": "*72", - "headerName": "mul72", - "description": "Multiplied by 72" - }, - "36": { - "displayName": "*74", - "headerName": "mul74", - "description": "Multiplied by 74" - }, - "37": { - "displayName": "*76", - "headerName": "mul76", - "description": "Multiplied by 76" - }, - "38": { - "displayName": "*78", - "headerName": "mul78", - "description": "Multiplied by 78" - }, - "39": { - "displayName": "*80", - "headerName": "mul80", - "description": "Multiplied by 80" - }, - "40": { - "displayName": "*82", - "headerName": "mul82", - "description": "Multiplied by 82" - }, - "41": { - "displayName": "*84", - "headerName": "mul84", - "description": "Multiplied by 84" - }, - "42": { - "displayName": "*86", - "headerName": "mul86", - "description": "Multiplied by 86" - }, - "43": { - "displayName": "*88", - "headerName": "mul88", - "description": "Multiplied by 88" - }, - "44": { - "displayName": "*90", - "headerName": "mul90", - "description": "Multiplied by 90" - }, - "45": { - "displayName": "*92", - "headerName": "mul92", - "description": "Multiplied by 92" - }, - "46": { - "displayName": "*94", - "headerName": "mul94", - "description": "Multiplied by 94" - }, - "47": { - "displayName": "*96", - "headerName": "mul96", - "description": "Multiplied by 96" - }, - "48": { - "displayName": "*98", - "headerName": "mul98", - "description": "Multiplied by 98" - }, - "49": { - "displayName": "*100", - "headerName": "mul100", - "description": "Multiplied by 100" - }, - "50": { - "displayName": "*102", - "headerName": "mul102", - "description": "Multiplied by 102" - }, - "51": { - "displayName": "*104", - "headerName": "mul104", - "description": "Multiplied by 104" - }, - "52": { - "displayName": "*106", - "headerName": "mul106", - "description": "Multiplied by 106" - }, - "53": { - "displayName": "*108", - "headerName": "mul108", - "description": "Multiplied by 108" - }, - "54": { - "displayName": "*110", - "headerName": "mul110", - "description": "Multiplied by 110" - }, - "55": { - "displayName": "*112", - "headerName": "mul112", - "description": "Multiplied by 112" - }, - "56": { - "displayName": "*114", - "headerName": "mul114", - "description": "Multiplied by 114" - }, - "57": { - "displayName": "*116", - "headerName": "mul116", - "description": "Multiplied by 116" - }, - "58": { - "displayName": "*118", - "headerName": "mul118", - "description": "Multiplied by 118" - }, - "59": { - "displayName": "*120", - "headerName": "mul120", - "description": "Multiplied by 120" - }, - "60": { - "displayName": "*122", - "headerName": "mul122", - "description": "Multiplied by 122" - }, - "61": { - "displayName": "*124", - "headerName": "mul124", - "description": "Multiplied by 124" - }, - "62": { - "displayName": "*126", - "headerName": "mul126", - "description": "Multiplied by 126" - }, - "63": { - "displayName": "*128", - "headerName": "mul128", - "description": "Multiplied by 128" - } - } - } - } - }, - "q": { - "description": "PLL Q output divider value", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x3", - "enumerations": { - "pllq-enum": { - "description": "Reference Clock Q Divide Ratio Enumeration", - "values": { - "*": { - "displayName": "n/a", - "description": "Not supported" - }, - "1": { - "displayName": "/2", - "headerName": "div2", - "description": "Divided by 2" - }, - "2": { - "displayName": "/4", - "headerName": "div4", - "description": "Divided by 4" - }, - "3": { - "displayName": "/8", - "headerName": "div8", - "description": "Divided by 8" - } - } - } - } - }, - "sel": { - "description": "PLL select", - "bitOffset": "16", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "refsel": { - "description": "PLL reference select", - "bitOffset": "17", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "bypass": { - "description": "PLL bypass", - "bitOffset": "18", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "lock": { - "description": "PLL lock indicator", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "plloutdiv": { - "description": "PLL Output Divider", - "addressOffset": "0x000C" - } - } - }, - "otp": { - "description": "One-Time Programmable Memory (OTP) Peripheral", - "baseAddress": "0x10010000", - "size": "0x1000", - "registers": { - "lock": { - "description": "Programmed-I/O Lock Register", - "addressOffset": "0x0000" - }, - "ck": { - "description": "Device Clock Signal Register", - "addressOffset": "0x0004" - }, - "oe": { - "description": "Device Output-Enable Signal Register", - "addressOffset": "0x0008" - }, - "sel": { - "description": "Device Chip-Select Signal Register", - "addressOffset": "0x000C" - }, - "we": { - "description": "Device Write-Enable Signal Register", - "addressOffset": "0x0010" - }, - "mr": { - "description": "Device Mode Register", - "addressOffset": "0x0014" - }, - "mrr": { - "description": "Read-Voltage Regulator Control Register", - "addressOffset": "0x0018" - }, - "mpp": { - "description": "Write-Voltage Charge Pump Control Register", - "addressOffset": "0x001C" - }, - "vrren": { - "description": "Read-Voltage Enable Register", - "addressOffset": "0x0020" - }, - "vppen": { - "description": "Write-Voltage Enable Register", - "addressOffset": "0x0024" - }, - "a": { - "description": "Device Address Register", - "addressOffset": "0x0028" - }, - "d": { - "description": "Device Data Input Register", - "addressOffset": "0x002C" - }, - "q": { - "description": "Device Data Output Register", - "addressOffset": "0x0030" - }, - "rsctrl": { - "description": "Read Sequencer Control Register", - "addressOffset": "0x0034", - "fields": { - "scale": { - "description": "OTP timescale", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x1" - }, - "tas": { - "description": "Address setup time", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "trp": { - "description": "Read pulse time", - "bitOffset": "4", - "bitWidth": "1" - }, - "tracc": { - "description": "Read access time", - "bitOffset": "5", - "bitWidth": "1" - } - } - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x10012000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "8" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "9" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "10" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "11" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "12" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "13" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "14" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "15" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "16" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "17" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "18" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "19" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "20" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "21" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "22" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "23" - }, - "gpio16": { - "description": "GPIO16 Interrupt", - "value": "24" - }, - "gpio17": { - "description": "GPIO17 Interrupt", - "value": "25" - }, - "gpio18": { - "description": "GPIO18 Interrupt", - "value": "26" - }, - "gpio19": { - "description": "GPIO19 Interrupt", - "value": "27" - }, - "gpio20": { - "description": "GPIO20 Interrupt", - "value": "28" - }, - "gpio21": { - "description": "GPIO21 Interrupt", - "value": "29" - }, - "gpio22": { - "description": "GPIO22 Interrupt", - "value": "30" - }, - "gpio23": { - "description": "GPIO23 Interrupt", - "value": "31" - }, - "gpio24": { - "description": "GPIO24 Interrupt", - "value": "32" - }, - "gpio25": { - "description": "GPIO25 Interrupt", - "value": "33" - }, - "gpio26": { - "description": "GPIO26 Interrupt", - "value": "34" - }, - "gpio27": { - "description": "GPIO27 Interrupt", - "value": "35" - }, - "gpio28": { - "description": "GPIO28 Interrupt", - "value": "36" - }, - "gpio29": { - "description": "GPIO29 Interrupt", - "value": "37" - }, - "gpio30": { - "description": "GPIO30 Interrupt", - "value": "38" - }, - "gpio31": { - "description": "GPIO31 Interrupt", - "value": "39" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x10013000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "3" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x10014000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "5" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10015000", - "size": "0x1000", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "40" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "41" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "42" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "43" - } - } - }, - "uart1": { - "baseAddress": "0x10023000", - "derivedFrom": "uart0", - "groupName": "uart", - "interrupts": { - "uart1": { - "description": "UART1 Interrupt", - "value": "4" - } - } - }, - "spi1": { - "baseAddress": "0x10024000", - "derivedFrom": "spi0", - "groupName": "spi", - "interrupts": { - "spi1": { - "description": "SPI1 Interrupt", - "value": "6" - } - } - }, - "pwm1": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10025000", - "groupName": "pwm", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - } - }, - "interrupts": { - "pwm1cmp0": { - "description": "PWM1 Compare 0 Interrupt", - "value": "44" - }, - "pwm1cmp1": { - "description": "PWM1 Compare 1 Interrupt", - "value": "45" - }, - "pwm1cmp2": { - "description": "PWM1 Compare 2 Interrupt", - "value": "46" - }, - "pwm1cmp3": { - "description": "PWM1 Compare 3 Interrupt", - "value": "47" - } - } - }, - "spi2": { - "baseAddress": "0x10034000", - "derivedFrom": "spi0", - "groupName": "spi", - "interrupts": { - "spi2": { - "description": "SPI2 Interrupt", - "value": "7" - } - } - }, - "pwm2": { - "baseAddress": "0x10035000", - "derivedFrom": "pwm1", - "groupName": "pwm", - "interrupts": { - "pwm2cmp0": { - "description": "PWM2 Compare 0 Interrupt", - "value": "48" - }, - "pwm2cmp1": { - "description": "PWM2 Compare 1 Interrupt", - "value": "49" - }, - "pwm2cmp2": { - "description": "PWM2 Compare 2 Interrupt", - "value": "50" - }, - "pwm2cmp3": { - "description": "PWM2 Compare 3 Interrupt", - "value": "51" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/HiFive1/hello/hello OpenOCD.launch b/FreedomStudio/HiFive1/hello/hello OpenOCD.launch deleted file mode 100644 index 55bd731..0000000 --- a/FreedomStudio/HiFive1/hello/hello OpenOCD.launch +++ /dev/null @@ -1,60 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/> -<booleanAttribute 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-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"/> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/hello"/> -</listAttribute> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> -<listEntry value="4"/> -</listAttribute> -<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> -<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> -</launchConfiguration> diff --git a/FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg deleted file mode 100644 index b0a8e26..0000000 --- a/FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg +++ /dev/null @@ -1,34 +0,0 @@ -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 - -#Reset Stretcher logic on FE310 is ~1 second long -#This doesn't apply if you use -# ftdi_set_signal, but still good to document -#adapter_nsrst_delay 1500 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME -init -#reset -- This type of reset is not implemented yet -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z - #Wait for the reset stretcher - #It will work without this, but - #will incur lots of delays for later commands. - sleep 1500 -} -halt -flash protect 0 64 last off diff --git a/FreedomStudio/HiFive1/led_fade/.cproject b/FreedomStudio/HiFive1/led_fade/.cproject deleted file mode 100644 index e0d1e09..0000000 --- a/FreedomStudio/HiFive1/led_fade/.cproject +++ /dev/null @@ -1,210 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> - <storageModule moduleId="org.eclipse.cdt.core.settings"> - <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"> - <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870" moduleId="org.eclipse.cdt.core.settings" name="Debug"> - <externalSettings/> - <extensions> - <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> - <extension 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100644 index 1722e54..0000000 --- a/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json +++ /dev/null @@ -1,2325 +0,0 @@ -{ - "schemaVersion": "0.2.4", - "contentVersion": "0.2.0", - "headerVersion": "0.2.0", - "device": { - "fe310": { - "displayName": "Freedom E310-G000", - "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.", - "supplier": { - "name": "sifive", - "id": "1", - "displayName": "SiFive", - "fullName": "SiFive, Inc.", - "contact": "info@sifive.com" - }, - "busWidth": "32", - "resetMask": "all", - "resetValue": "0x00000000", - "access": "rw", - "headerGuardPrefix": "SIFIVE_DEVICES_FE310_", - "headerTypePrefix": "sifive_fe310_", - "headerInterruptPrefix": "sifive_fe310_interrupt_global_", - "headerInterruptEnumPrefix": "riscv_interrupts_global_", - "revision": "r0p0", - "numInterrupts": "51", - "priorityBits": "3", - "regWidth": "32", - "cores": { - "e31": { - "harts": "1", - "isa": "RV32IMAC", - "isaVersion": "2.2", - "mpu": "pmp", - "mmu": "none", - "localInterrupts": { - "machine_software": { - "description": "Machine Software Interrupt", - "value": "3" - }, - "machine_timer": { - "description": "Machine Timer Interrupt", - "value": "7" - }, - "machine_ext": { - "description": "Machine External Interrupt", - "value": "11" - } - }, - "numLocalInterrupts": "0" - } - }, - "peripherals": { - "clint": { - "description": "Core Complex Local Interruptor (CLINT) Peripheral", - "baseAddress": "0x02000000", - "size": "0x10000", - "registers": { - "msip": { - "description": "MSIP (Machine-mode Software Interrupts) Register per Hart", - "addressOffset": "0x0000", - "arraySize": "1" - } - }, - "clusters": { - "mtimecmp": { - "description": "Machine Time Compare Registers per Hart", - "addressOffset": "0x4000", - "arraySize": "1", - "registers": { - "low": { - "description": "Machine Compare Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Compare Register High", - "addressOffset": "0x0004" - } - } - }, - "mtime": { - "description": "Machine Time Register", - "addressOffset": "0xBFF8", - "access": "r", - "registers": { - "low": { - "description": "Machine Time Register Low", - "addressOffset": "0x0000" - }, - "high": { - "description": "Machine Time Register High", - "addressOffset": "0x0004" - } - } - } - } - }, - "plic": { - "description": "Platform-Level Interrupt Controller (PLIC) Peripheral", - "baseAddress": "0x0C000000", - "size": "0x4000000", - "registers": { - "priorities": { - "arraySize": "52", - "description": "Interrupt Priorities Registers; 0 is reserved.", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority for a given global interrupt", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "pendings": { - "arraySize": "2", - "description": "Interrupt Pending Bits Registers", - "addressOffset": "0x1000", - "access": "r" - } - }, - "clusters": { - "enablestarget0": { - "description": "Hart 0 Interrupt Enable Bits", - "addressOffset": "0x00002000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-mode Interrupt Enable Bits", - "registers": { - "enables": { - "arraySize": "2", - "description": "Interrupt Enable Bits Registers", - "addressOffset": "0x0000" - } - } - } - } - }, - "target0": { - "description": "Hart 0 Interrupt Thresholds", - "addressOffset": "0x00200000", - "clusters": { - "m": { - "addressOffset": "0x0000", - "description": "Hart 0 M-Mode Interrupt Threshold", - "registers": { - "threshold": { - "description": "The Priority Threshold Register", - "addressOffset": "0x0000", - "fields": { - "value": { - "description": "The priority threshold value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "claimcomplete": { - "description": "The Interrupt Claim/Completion Register", - "addressOffset": "0x0004" - } - } - } - } - } - } - }, - "wdog": { - "description": "Watchdog Timer (WDT), part of Always-On Domain", - "baseAddress": "0x10000000", - "size": "0x0040", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Watchdog Configuration Register", - "addressOffset": "0x0000", - "fields": { - "scale": { - "description": "Watchdog counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "rsten": { - "description": "Watchdog full reset enable", - "bitOffset": "8", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "zerocmp": { - "description": "Watchdog zero on comparator", - "bitOffset": "9", - "bitWidth": "1" - }, - "enalways": { - "description": "Watchdog enable counter always", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "encoreawake": { - "description": "Watchdog counter only when awake", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmpip": { - "description": "Watchdog interrupt pending", - "bitOffset": "28", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Watchdog Count Register", - "addressOffset": "0x0008" - }, - "scale": { - "description": "Watchdog Scale Register", - "addressOffset": "0x0010", - "fields": { - "value": { - "description": "Watchdog scale value", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "feed": { - "description": "Watchdog Feed Address Register", - "addressOffset": "0x0018" - }, - "key": { - "description": "Watchdog Key Register", - "addressOffset": "0x001C" - }, - "cmp": { - "description": "Watchdog Compare Register", - "addressOffset": "0x0020", - "fields": { - "value": { - "description": "Watchdog compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - } - }, - "interrupts": { - "wdogcmp": { - "description": "Watchdog Compare Interrupt", - "value": "1" - } - } - }, - "rtc": { - "description": "Real-Time Clock (RTC), part of Always-On Domain", - "baseAddress": "0x10000040", - "size": "0x0030", - "resetMask": "none", - "registers": { - "cfg": { - "description": "RTC Configuration Register", - "addressOffset": "0x0000", - "fields": { - "scale": { - "description": "RTC clock rate scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "enalways": { - "description": "RTC counter enable", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmpip": { - "description": "RTC comparator interrupt pending", - "bitOffset": "28", - "bitWidth": "1", - "access": "r" - } - } - }, - "low": { - "description": "RTC Counter Register Low", - "addressOffset": "0x0008" - }, - "high": { - "description": "RTC Counter Register High", - "addressOffset": "0x000C", - "fields": { - "value": { - "description": "RTC counter register, high bits", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "scale": { - "description": "RTC Scale Register", - "addressOffset": "0x0010" - }, - "cmp": { - "description": "RTC Compare Register", - "addressOffset": "0x0020" - } - }, - "interrupts": { - "rtccmp": { - "description": "RTC Compare Interrupt", - "value": "2" - } - } - }, - "pmu": { - "description": "Power-Management Unit (PMU), part of Always-On Domain", - "baseAddress": "0x10000100", - "size": "0x0050", - "resetMask": "none", - "registers": { - "wakeupi": { - "description": "Wakeup program instruction Registers", - "addressOffset": "0x0000", - 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"bitOffset": "0", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x04" - }, - "trim": { - "description": "LFROSC trim value", - "bitOffset": "16", - "bitWidth": "5", - "resetMask": "all", - "resetValue": "0x10" - }, - "en": { - "description": "LFROSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "LFROSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "backup": { - "description": "Backup Registers", - "addressOffset": "0x0010", - "arraySize": "32" - } - } - }, - "prci": { - "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral", - "baseAddress": "0x10008000", - "size": "0x8000", - "registers": { - "hfrosccfg": { - "description": "Internal Trimmable Programmable 72 MHz Oscillator Register", - "addressOffset": "0x0000", - "fields": { - "div": { - "description": "HFROSC divider", - "bitOffset": "0", - "bitWidth": "6", - "resetMask": "all", - "resetValue": "0x04" - }, - "trim": { - "description": "HFROSC trim value", - "bitOffset": "16", - "bitWidth": "5", - "resetMask": "all", - "resetValue": "0x10" - }, - "en": { - "description": "HFROSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "HFROSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "hfxosccfg": { - "description": "External 16 MHz Crystal Oscillator Register", - "addressOffset": "0x0004", - "fields": { - "en": { - "description": "HFXOSC enable", - "bitOffset": "30", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "rdy": { - "description": "HFXOSC ready", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "pllcfg": { - "description": "Internal High-Frequency PLL (HFPLL) Register", - "addressOffset": "0x0008", - "fields": { - "r": { - "description": "PLL R input divider value", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1", - 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}, - "43": { - "displayName": "*88", - "headerName": "mul88", - "description": "Multiplied by 88" - }, - "44": { - "displayName": "*90", - "headerName": "mul90", - "description": "Multiplied by 90" - }, - "45": { - "displayName": "*92", - "headerName": "mul92", - "description": "Multiplied by 92" - }, - "46": { - "displayName": "*94", - "headerName": "mul94", - "description": "Multiplied by 94" - }, - "47": { - "displayName": "*96", - "headerName": "mul96", - "description": "Multiplied by 96" - }, - "48": { - "displayName": "*98", - "headerName": "mul98", - "description": "Multiplied by 98" - }, - "49": { - "displayName": "*100", - "headerName": "mul100", - "description": "Multiplied by 100" - }, - "50": { - "displayName": "*102", - "headerName": "mul102", - "description": "Multiplied by 102" - }, - "51": { - "displayName": "*104", - "headerName": "mul104", - "description": "Multiplied by 104" - }, - "52": { - "displayName": "*106", - "headerName": "mul106", - "description": "Multiplied by 106" - }, - "53": { - "displayName": "*108", - "headerName": "mul108", - "description": "Multiplied by 108" - }, - "54": { - "displayName": "*110", - "headerName": "mul110", - "description": "Multiplied by 110" - }, - "55": { - "displayName": "*112", - "headerName": "mul112", - "description": "Multiplied by 112" - }, - "56": { - "displayName": "*114", - "headerName": "mul114", - "description": "Multiplied by 114" - }, - "57": { - "displayName": "*116", - "headerName": "mul116", - "description": "Multiplied by 116" - }, - "58": { - "displayName": "*118", - "headerName": "mul118", - "description": "Multiplied by 118" - }, - "59": { - "displayName": "*120", - "headerName": "mul120", - "description": "Multiplied by 120" - }, - "60": { - "displayName": "*122", - "headerName": "mul122", - "description": "Multiplied by 122" - }, - "61": { - "displayName": "*124", - "headerName": "mul124", - "description": "Multiplied by 124" - }, - "62": { - "displayName": "*126", - "headerName": "mul126", - "description": "Multiplied by 126" - }, - "63": { - "displayName": "*128", - "headerName": "mul128", - "description": "Multiplied by 128" - } - } - } - } - }, - "q": { - "description": "PLL Q output divider value", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x3", - "enumerations": { - "pllq-enum": { - "description": "Reference Clock Q Divide Ratio Enumeration", - "values": { - "*": { - "displayName": "n/a", - "description": "Not supported" - }, - "1": { - "displayName": "/2", - "headerName": "div2", - "description": "Divided by 2" - }, - "2": { - "displayName": "/4", - "headerName": "div4", - "description": "Divided by 4" - }, - "3": { - "displayName": "/8", - "headerName": "div8", - "description": "Divided by 8" - } - } - } - } - }, - "sel": { - "description": "PLL select", - "bitOffset": "16", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "refsel": { - "description": "PLL reference select", - "bitOffset": "17", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "bypass": { - "description": "PLL bypass", - "bitOffset": "18", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "lock": { - "description": "PLL lock indicator", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "plloutdiv": { - "description": "PLL Output Divider", - "addressOffset": "0x000C" - } - } - }, - "otp": { - "description": "One-Time Programmable Memory (OTP) Peripheral", - "baseAddress": "0x10010000", - "size": "0x1000", - "registers": { - "lock": { - "description": "Programmed-I/O Lock Register", - "addressOffset": "0x0000" - }, - "ck": { - "description": "Device Clock Signal Register", - "addressOffset": "0x0004" - }, - "oe": { - "description": "Device Output-Enable Signal Register", - "addressOffset": "0x0008" - }, - "sel": { - "description": "Device Chip-Select Signal Register", - "addressOffset": "0x000C" - }, - "we": { - "description": "Device Write-Enable Signal Register", - "addressOffset": "0x0010" - }, - "mr": { - "description": "Device Mode Register", - "addressOffset": "0x0014" - }, - "mrr": { - "description": "Read-Voltage Regulator Control Register", - "addressOffset": "0x0018" - }, - "mpp": { - "description": "Write-Voltage Charge Pump Control Register", - "addressOffset": "0x001C" - }, - "vrren": { - "description": "Read-Voltage Enable Register", - "addressOffset": "0x0020" - }, - "vppen": { - "description": "Write-Voltage Enable Register", - "addressOffset": "0x0024" - }, - "a": { - "description": "Device Address Register", - "addressOffset": "0x0028" - }, - "d": { - "description": "Device Data Input Register", - "addressOffset": "0x002C" - }, - "q": { - "description": "Device Data Output Register", - "addressOffset": "0x0030" - }, - "rsctrl": { - "description": "Read Sequencer Control Register", - "addressOffset": "0x0034", - "fields": { - "scale": { - "description": "OTP timescale", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x1" - }, - "tas": { - "description": "Address setup time", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "trp": { - "description": "Read pulse time", - "bitOffset": "4", - "bitWidth": "1" - }, - "tracc": { - "description": "Read access time", - "bitOffset": "5", - "bitWidth": "1" - } - } - } - } - }, - "gpio": { - "description": "General Purpose Input/Output Controller (GPIO) Peripheral", - "baseAddress": "0x10012000", - "size": "0x1000", - "registers": { - "value": { - "description": "Pin Value Register", - "addressOffset": "0x000", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "inputen": { - "description": "Pin Input Enable Register", - "addressOffset": "0x004", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Input Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outputen": { - "description": "Pin Output Enable Register", - "addressOffset": "0x008", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Output Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "port": { - "description": "Output Port Value Register", - "addressOffset": "0x00C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output Port Value Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "pue": { - "description": "Internal Pull-up Enable Register", - "addressOffset": "0x010", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Internal Pull-up Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "ds": { - "description": "Pin Drive Strength Register", - "addressOffset": "0x014", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Pin Drive Strength Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseie": { - "description": "Rise Interrupt Enable Register", - "addressOffset": "0x018", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "riseip": { - "description": "Rise Interrupt Pending Register", - "addressOffset": "0x01C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Rise Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallie": { - "description": "Fall Interrupt Enable Register", - "addressOffset": "0x020", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "fallip": { - "description": "Fall Interrupt Pending Register", - "addressOffset": "0x024", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Fall Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highie": { - "description": "High Interrupt Enable Register", - "addressOffset": "0x028", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "highip": { - "description": "High Interrupt Pending Register", - "addressOffset": "0x02C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "High Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowie": { - "description": "Low Interrupt Enable Register", - "addressOffset": "0x030", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "lowip": { - "description": "Low Interrupt Pending Register", - "addressOffset": "0x034", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Low Interrupt Pending Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofen": { - "description": "HW I/O Function Enable Register", - "addressOffset": "0x038", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Enable Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "iofsel": { - "description": "HW I/O Function Select Register", - "addressOffset": "0x03C", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "HW I/O Function Select Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - }, - "outxor": { - "description": "Output XOR (invert) Register", - "addressOffset": "0x040", - "fields": { - "bit": { - "repeatGenerator": "0-31", - "description": "Output XOR Bit Field", - "bitOffset": "0", - "bitWidth": "1", - "headerName": "" - } - } - } - }, - "interrupts": { - "gpio0": { - "description": "GPIO0 Interrupt", - "value": "8" - }, - "gpio1": { - "description": "GPIO1 Interrupt", - "value": "9" - }, - "gpio2": { - "description": "GPIO2 Interrupt", - "value": "10" - }, - "gpio3": { - "description": "GPIO3 Interrupt", - "value": "11" - }, - "gpio4": { - "description": "GPIO4 Interrupt", - "value": "12" - }, - "gpio5": { - "description": "GPIO5 Interrupt", - "value": "13" - }, - "gpio6": { - "description": "GPIO6 Interrupt", - "value": "14" - }, - "gpio7": { - "description": "GPIO7 Interrupt", - "value": "15" - }, - "gpio8": { - "description": "GPIO8 Interrupt", - "value": "16" - }, - "gpio9": { - "description": "GPIO9 Interrupt", - "value": "17" - }, - "gpio10": { - "description": "GPIO10 Interrupt", - "value": "18" - }, - "gpio11": { - "description": "GPIO11 Interrupt", - "value": "19" - }, - "gpio12": { - "description": "GPIO12 Interrupt", - "value": "20" - }, - "gpio13": { - "description": "GPIO13 Interrupt", - "value": "21" - }, - "gpio14": { - "description": "GPIO14 Interrupt", - "value": "22" - }, - "gpio15": { - "description": "GPIO15 Interrupt", - "value": "23" - }, - "gpio16": { - "description": "GPIO16 Interrupt", - "value": "24" - }, - "gpio17": { - "description": "GPIO17 Interrupt", - "value": "25" - }, - "gpio18": { - "description": "GPIO18 Interrupt", - "value": "26" - }, - "gpio19": { - "description": "GPIO19 Interrupt", - "value": "27" - }, - "gpio20": { - "description": "GPIO20 Interrupt", - "value": "28" - }, - "gpio21": { - "description": "GPIO21 Interrupt", - "value": "29" - }, - "gpio22": { - "description": "GPIO22 Interrupt", - "value": "30" - }, - "gpio23": { - "description": "GPIO23 Interrupt", - "value": "31" - }, - "gpio24": { - "description": "GPIO24 Interrupt", - "value": "32" - }, - "gpio25": { - "description": "GPIO25 Interrupt", - "value": "33" - }, - "gpio26": { - "description": "GPIO26 Interrupt", - "value": "34" - }, - "gpio27": { - "description": "GPIO27 Interrupt", - "value": "35" - }, - "gpio28": { - "description": "GPIO28 Interrupt", - "value": "36" - }, - "gpio29": { - "description": "GPIO29 Interrupt", - "value": "37" - }, - "gpio30": { - "description": "GPIO30 Interrupt", - "value": "38" - }, - "gpio31": { - "description": "GPIO31 Interrupt", - "value": "39" - } - } - }, - "uart0": { - "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral", - "baseAddress": "0x10013000", - "size": "0x1000", - "resetMask": "none", - "groupName": "uart", - "registers": { - "txdata": { - "description": "Transmit Data Register", - "addressOffset": "0x000", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8" - }, - "full": { - "description": "Transmit FIFO full", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "rxdata": { - "description": "Receive Data Register", - "addressOffset": "0x004", - "resetMask": "none", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8", - "access": "r" - }, - "empty": { - "description": "Receive FIFO empty", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txctrl": { - "description": "Transmit Control Register ", - "addressOffset": "0x008", - "fields": { - "txen": { - "description": "Transmit enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "nstop": { - "description": "Number of stop bits", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "txcnt": { - "description": "Transmit watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "rxctrl": { - "description": "Receive Control Register", - "addressOffset": "0x00C", - "fields": { - "rxen": { - "description": "Receive enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxcnt": { - "description": "Receive watermark level", - "bitOffset": "16", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x010", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt enable", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark interrupt enable", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x014", - "access": "r", - "fields": { - "txwm": { - "description": "Transmit watermark interrupt pending", - "bitOffset": "0", - "bitWidth": "1" - }, - "rxwm": { - "description": "Receive watermark interrupt pending", - "bitOffset": "1", - "bitWidth": "1" - } - } - }, - "div": { - "description": "Baud Rate Divisor Register", - "addressOffset": "0x018", - "fields": { - "value": { - "description": "Baud rate divisor", - "bitOffset": "0", - "bitWidth": "16", - "resetMask": "all", - "resetValue": "0x0000FFFF" - } - } - } - }, - "interrupts": { - "uart0": { - "description": "UART0 Interrupt", - "value": "3" - } - } - }, - "spi0": { - "description": "Serial Peripheral Interface (SPI) Peripheral", - "baseAddress": "0x10014000", - "size": "0x1000", - "resetMask": "none", - "groupName": "spi", - "registers": { - "sckdiv": { - "description": "Serial clock divisor Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Divisor for serial clock", - "bitOffset": "0", - "bitWidth": "12", - "resetMask": "all", - "resetValue": "0x003" - } - } - }, - "sckmode": { - "description": "Serial Clock Mode Register", - "addressOffset": "0x004", - "fields": { - "pha": { - "description": "Serial clock phase", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "pol": { - "description": "Serial clock polarity", - "bitOffset": "1", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "csid": { - "description": "Chip Select ID Register", - "addressOffset": "0x010", - "resetMask": "all", - "resetValue": "0x00000000" - }, - "csdef": { - "description": "Chip Select Default Register", - "addressOffset": "0x014", - "resetMask": "all", - "resetValue": "0x00000001" - }, - "csmode": { - "description": "Chip Select Mode Register", - "addressOffset": "0x018", - "fields": { - "mode": { - "description": "Chip select mode", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "csmode-enum": { - "description": "Chip Select Modes Enumeration", - "values": { - "0": { - "displayName": "auto", - "description": "Assert/de-assert CS at the beginning/end of each frame" - }, - "*": { - "displayName": "reserved" - }, - "2": { - "displayName": "hold", - "description": "Keep CS continuously asserted after the initial frame" - }, - "3": { - "displayName": "off", - "description": "Disable hardware control of the CS pin" - } - } - } - } - } - } - }, - "delay0": { - "description": "Delay Control 0 Register", - "addressOffset": "0x028", - "fields": { - "cssck": { - "description": "CS to SCK Delay", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "sckcs": { - "description": "SCK to CS Delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "delay1": { - "description": "Delay Control 1 Register", - "addressOffset": "0x02C", - "fields": { - "intercs": { - "description": "Minimum CS inactive time", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - }, - "interxfr": { - "description": "Maximum interframe delay", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x01" - } - } - }, - "fmt": { - "description": "Frame Format Register", - "addressOffset": "0x040", - "fields": { - "proto": { - "description": "SPI Protocol", - "bitOffset": "0", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "proto-enum": { - "description": "SPI Protocol Enumeration", - "values": { - "0": { - "displayName": "single", - "description": "DQ0 (MOSI), DQ1 (MISO)" - }, - "1": { - "displayName": "dual", - "description": "DQ0, DQ1" - }, - "2": { - "displayName": "quad", - "description": "DQ0, DQ1, DQ2, DQ3" - }, - "*": { - "displayName": "reserved" - } - } - } - } - }, - "endian": { - "description": "SPI endianness", - "bitOffset": "2", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0", - "enumerations": { - "endian-enum": { - "description": "SPI Endianness Enumeration", - "values": { - "0": { - "displayName": "msb", - "description": "Transmit most-significant bit (MSB) first" - }, - "1": { - "displayName": "lsb", - "description": "Transmit least-significant bit (LSB) first" - } - } - } - } - }, - "dir": { - "description": "SPI I/O Direction", - "bitOffset": "3", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1", - "enumerations": { - "dir-enum": { - "description": "SPI I/O Direction Enumeration", - "values": { - "0": { - "displayName": "rx", - "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal." - }, - "1": { - "displayName": "tx", - "description": "The receive FIFO is not populated." - } - } - } - } - }, - "len": { - "description": "Number of bits per frame", - "bitOffset": "16", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x8" - } - } - }, - "txdata": { - "description": "Tx FIFO Data Register", - "addressOffset": "0x048", - "fields": { - "data": { - "description": "Transmit data", - "bitOffset": "0", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x00" - }, - "full": { - "description": "FIFO full flag", - "bitOffset": "31", - "bitWidth": "1", - "access": "r" - } - } - }, - "rxdata": { - "description": "Rx FIFO Data Register", - "addressOffset": "0x04C", - "resetMask": "none", - "access": "r", - "fields": { - "data": { - "description": "Received data", - "bitOffset": "0", - "bitWidth": "8" - }, - "empty": { - "description": "FIFO empty flag", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "txmark": { - "description": "Tx FIFO Watermark Register", - "addressOffset": "0x050", - "fields": { - "value": { - "description": "Transmit watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "rxmark": { - "description": "Rx FIFO Watermark Register", - "addressOffset": "0x054", - "fields": { - "value": { - "description": "Receive watermark", - "bitOffset": "0", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "fctrl": { - "description": "Flash Interface Control Register", - "addressOffset": "0x060", - "fields": { - "en": { - "description": "SPI Flash Mode Select", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - } - } - }, - "ffmt": { - "description": "Flash Instruction Format Register", - "addressOffset": "0x064", - "fields": { - "cmden": { - "description": "Enable sending of command", - "bitOffset": "0", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x1" - }, - "addrlen": { - "description": "Number of address bytes(0 to 4)", - "bitOffset": "1", - "bitWidth": "3", - "resetMask": "all", - "resetValue": "0x3" - }, - "padcnt": { - "description": "Number of dummy cycles", - "bitOffset": "4", - "bitWidth": "4", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdproto": { - "description": "Protocol for transmitting command", - "bitOffset": "8", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "addrproto": { - "description": "Protocol for transmitting address and padding", - "bitOffset": "10", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "dataproto": { - "description": "Protocol for receiving data bytes", - "bitOffset": "12", - "bitWidth": "2", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmdcode": { - "description": "Value of command byte", - "bitOffset": "16", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x03" - }, - "padcode": { - "description": "First 8 bits to transmit during dummy cycles", - "bitOffset": "24", - "bitWidth": "8", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ie": { - "description": "Interrupt Enable Register", - "addressOffset": "0x070", - "fields": { - "txwm": { - "description": "Transmit watermark enable", - "bitOffset": "0", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - }, - "rxwm": { - "description": "Receive watermark enable", - "bitOffset": "1", - "bitWidth": "1", - "access": "r", - "resetMask": "all", - "resetValue": "0x0" - } - } - }, - "ip": { - "description": "Interrupt Pending Register", - "addressOffset": "0x074", - "fields": { - "txwm": { - "description": "Transmit watermark pending", - "bitOffset": "0", - "bitWidth": "1", - "access": "r" - }, - "rxwm": { - "description": "Receive watermark pending", - "bitOffset": "1", - "bitWidth": "1", - "access": "r" - } - } - } - }, - "interrupts": { - "spi0": { - "description": "SPI0 Interrupt", - "value": "5" - } - } - }, - "pwm0": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10015000", - "size": "0x1000", - "resetMask": "none", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "8" - } - } - } - }, - "interrupts": { - "pwm0cmp0": { - "description": "PWM0 Compare 0 Interrupt", - "value": "40" - }, - "pwm0cmp1": { - "description": "PWM0 Compare 1 Interrupt", - "value": "41" - }, - "pwm0cmp2": { - "description": "PWM0 Compare 2 Interrupt", - "value": "42" - }, - "pwm0cmp3": { - "description": "PWM0 Compare 3 Interrupt", - "value": "43" - } - } - }, - "uart1": { - "baseAddress": "0x10023000", - "derivedFrom": "uart0", - "groupName": "uart", - "interrupts": { - "uart1": { - "description": "UART1 Interrupt", - "value": "4" - } - } - }, - "spi1": { - "baseAddress": "0x10024000", - "derivedFrom": "spi0", - "groupName": "spi", - "interrupts": { - "spi1": { - "description": "SPI1 Interrupt", - "value": "6" - } - } - }, - "pwm1": { - "description": "Pulse-Width Modulation (PWM) Peripheral", - "baseAddress": "0x10025000", - "groupName": "pwm", - "size": "0x1000", - "resetMask": "none", - "groupName": "pwm", - "registers": { - "cfg": { - "description": "Configuration Register", - "addressOffset": "0x000", - "fields": { - "scale": { - "description": "Counter scale", - "bitOffset": "0", - "bitWidth": "4" - }, - "sticky": { - "description": "Sticky - disallow clearing pwmcmpXip bits", - "bitOffset": "8", - "bitWidth": "1" - }, - "zerocmp": { - "description": "Zero - counter resets to zero after match", - "bitOffset": "9", - "bitWidth": "1" - }, - "deglitch": { - "description": "Deglitch - latch pwmcmpXip within same cycle", - "bitOffset": "10", - "bitWidth": "1" - }, - "enalways": { - "description": "Enable always - run continuously", - "bitOffset": "12", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "enoneshot": { - "description": "enable one shot - run one cycle", - "bitOffset": "13", - "bitWidth": "1", - "resetMask": "all", - "resetValue": "0x0" - }, - "cmp0center": { - "description": "PWM0 Compare Center", - "bitOffset": "16", - "bitWidth": "1" - }, - "cmp1center": { - "description": "PWM1 Compare Center", - "bitOffset": "17", - "bitWidth": "1" - }, - "cmp2center": { - "description": "PWM2 Compare Center", - "bitOffset": "18", - "bitWidth": "1" - }, - "cmp3center": { - "description": "PWM3 Compare Center", - "bitOffset": "19", - "bitWidth": "1" - }, - "cmp0gang": { - "description": "PWM0/PWM1 Compare Gang", - "bitOffset": "24", - "bitWidth": "1" - }, - "cmp1gang": { - "description": "PWM1/PWM2 Compare Gang", - "bitOffset": "25", - "bitWidth": "1" - }, - "cmp2gang": { - "description": "PWM2/PWM3 Compare Gang", - "bitOffset": "26", - "bitWidth": "1" - }, - "cmp3gang": { - "description": "PWM3/PWM0 Compare Gang", - "bitOffset": "27", - "bitWidth": "1" - }, - "cmp0ip": { - "description": "PWM0 Interrupt Pending", - "bitOffset": "28", - "bitWidth": "1" - }, - "cmp1ip": { - "description": "PWM1 Interrupt Pending", - "bitOffset": "29", - "bitWidth": "1" - }, - "cmp2ip": { - "description": "PWM2 Interrupt Pending", - "bitOffset": "30", - "bitWidth": "1" - }, - "cmp3ip": { - "description": "PWM3 Interrupt Pending", - "bitOffset": "31", - "bitWidth": "1" - } - } - }, - "count": { - "description": "Configuration Register", - "addressOffset": "0x008" - }, - "scale": { - "description": "Scale Register", - "addressOffset": "0x010", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - }, - "cmp": { - "arraySize": "4", - "description": "Compare Registers", - "addressOffset": "0x020", - "fields": { - "value": { - "description": "Compare value", - "bitOffset": "0", - "bitWidth": "16" - } - } - } - }, - "interrupts": { - "pwm1cmp0": { - "description": "PWM1 Compare 0 Interrupt", - "value": "44" - }, - "pwm1cmp1": { - "description": "PWM1 Compare 1 Interrupt", - "value": "45" - }, - "pwm1cmp2": { - "description": "PWM1 Compare 2 Interrupt", - "value": "46" - }, - "pwm1cmp3": { - "description": "PWM1 Compare 3 Interrupt", - "value": "47" - } - } - }, - "spi2": { - "baseAddress": "0x10034000", - "derivedFrom": "spi0", - "groupName": "spi", - "interrupts": { - "spi2": { - "description": "SPI2 Interrupt", - "value": "7" - } - } - }, - "pwm2": { - "baseAddress": "0x10035000", - "derivedFrom": "pwm1", - "groupName": "pwm", - "interrupts": { - "pwm2cmp0": { - "description": "PWM2 Compare 0 Interrupt", - "value": "48" - }, - "pwm2cmp1": { - "description": "PWM2 Compare 1 Interrupt", - "value": "49" - }, - "pwm2cmp2": { - "description": "PWM2 Compare 2 Interrupt", - "value": "50" - }, - "pwm2cmp3": { - "description": "PWM2 Compare 3 Interrupt", - "value": "51" - } - } - } - } - } - } -}
\ No newline at end of file diff --git a/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch b/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch deleted file mode 100644 index abe9c3e..0000000 --- a/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch +++ /dev/null @@ -1,60 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?> -<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/> -<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off set arch riscv:rv32 set remotetimeout 250"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/> -<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-freedom-e300-hifive1.cfg"/> -<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/> -<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> -<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> -<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> -<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> -<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/> -<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/> -<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> -<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> -<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> -<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/led_fade.elf"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="led_fade"/> -<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> -<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"/> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> -<listEntry value="/led_fade"/> -</listAttribute> -<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> -<listEntry value="4"/> -</listAttribute> -<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> -<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> -</launchConfiguration> diff --git a/FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg deleted file mode 100644 index b0a8e26..0000000 --- a/FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg +++ /dev/null @@ -1,34 +0,0 @@ -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 - -#Reset Stretcher logic on FE310 is ~1 second long -#This doesn't apply if you use -# ftdi_set_signal, but still good to document -#adapter_nsrst_delay 1500 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME -init -#reset -- This type of reset is not implemented yet -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z - #Wait for the reset stretcher - #It will work without this, but - #will incur lots of delays for later commands. - sleep 1500 -} -halt -flash protect 0 64 last off @@ -2,9 +2,6 @@ # Configuration ############################################################# -# Allow users to select a different cross compiler. -CROSS_COMPILE ?= riscv64-unknown-elf - # Allows users to create Makefile.local or ../Makefile.project with # configuration variables, so they don't have to be set on the command-line # every time. @@ -14,9 +11,8 @@ $(info Obtaining additional make variables from $(extra_configs)) include $(extra_configs) endif -# Default target - -# legacy for old e-sdk or mee +# Select Legacy BSP or Freedom Metal BSP +# Allowed values are 'legacy' and 'mee' BSP ?= legacy ifeq ($(BSP),legacy) @@ -27,6 +23,7 @@ LINK_TARGET ?= flash GDB_PORT ?= 3333 else # MEE +BSP = mee BSP_SUBDIR ?= PROGRAM ?= hello BOARD ?= sifive-hifive1 @@ -36,52 +33,38 @@ endif # $(BSP) BOARD_ROOT ?= $(abspath .) PROGRAM_ROOT ?= $(abspath .) -# Variables the user probably shouldn't override. +SRC_DIR = $(PROGRAM_ROOT)/software/$(PROGRAM) + +PROGRAM_ELF = $(SRC_DIR)/$(PROGRAM) +PROGRAM_HEX = $(SRC_DIR)/$(PROGRAM).hex + ############################################################# # BSP Loading ############################################################# # Finds the directory in which this BSP is located, ensuring that there is # exactly one. -board_dir := $(wildcard $(BOARD_ROOT)/bsp/$(BSP_SUBDIR)/$(BOARD)) -ifeq ($(words $(board_dir)),0) +BSP_DIR := $(wildcard $(BOARD_ROOT)/bsp/$(BSP_SUBDIR)/$(BOARD)) +ifeq ($(words $(BSP_DIR)),0) $(error Unable to find BSP for $(BOARD), expected to find either "bsp/$(BOARD)" or "bsp-addons/$(BOARD)") endif -ifneq ($(words $(board_dir)),1) -$(error Found multiple BSPs for $(BOARD): "$(board_dir)") -endif - -ifeq ($(BSP), mee) - -include $(board_dir)/settings.mk - -else - -# There must be a settings makefile fragment in the BSP's board directory. -ifeq ($(wildcard $(board_dir)/settings.mk),) -$(error Unable to find BSP for $(BOARD), expected to find $(board_dir)/settings.mk) +ifneq ($(words $(BSP_DIR)),1) +$(error Found multiple BSPs for $(BOARD): "$(BSP_DIR)") endif -include $(board_dir)/settings.mk - -ifeq ($(RISCV_ARCH),) -$(error $(board_dir)/board.mk must set RISCV_ARCH, the RISC-V ISA string to target) -endif +############################################################# +# Standalone Script Include +############################################################# -ifeq ($(RISCV_ABI),) -$(error $(board_dir)/board.mk must set RISCV_ABI, the ABI to target) -endif +# The standalone script is included here because it needs $(SRC_DIR) and +# $(BSP_DIR) to be set. +# +# The standalone Makefile handles the following tasks: +# - Including $(BSP_DIR)/settings.mk and validating RISCV_ARCH, RISCV_ABI +# - Setting the toolchain path with CROSS_COMPILE and RISCV_PATH +# - Providing the software and $(PROGRAM_ELF) Make targets for the MEE -endif - -# Determines the XLEN from the toolchain tuple -ifeq ($(patsubst rv32%,rv32,$(RISCV_ARCH)),rv32) -RISCV_XLEN := 32 -else ifeq ($(patsubst rv64%,rv64,$(RISCV_ARCH)),rv64) -RISCV_XLEN := 64 -else -$(error Unable to determine XLEN from $(RISCV_ARCH)) -endif +include scripts/standalone.mk ############################################################# # Prints help message @@ -109,36 +92,32 @@ help: @echo " debug BSP=mee [PROGRAM=$(PROGRAM) BOARD=$(BOARD)]:" @echo " Launch OpenOCD and attach GDB to the running program." @echo "" + @echo " standalone BSP=mee STANDALONE_DEST=/path/to/desired/location" + @echo " [PROGRAM=$(PROGRAM) BOARD=$(BOARD)]:" + @echo " Export a program for a single target into a standalone" + @echo " project directory at STANDALONE_DEST." + @echo "" @echo " For more information, read the accompanying README.md" .PHONY: clean clean: ############################################################# -# This section is for tool configuration +# Enumerate MEE BSPs and Programs ############################################################# -# If users don't specify RISCV_PATH then assume that the tools will just be in -# their path. -ifeq ($(RISCV_PATH),) -RISCV_GCC := $(CROSS_COMPILE)-gcc -RISCV_GXX := $(CROSS_COMPILE)-g++ -RISCV_OBJDUMP := $(CROSS_COMPILE)-objdump -RISCV_GDB := $(CROSS_COMPILE)-gdb -RISCV_AR := $(CROSS_COMPILE)-ar -else -RISCV_GCC := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-gcc) -RISCV_GXX := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-g++) -RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-objdump) -RISCV_GDB := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-gdb) -RISCV_AR := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-ar) -PATH := $(abspath $(RISCV_PATH)/bin):$(PATH) -endif +ifeq ($(BSP),mee) + +# MEE boards are any folders that aren't the Legacy BSP or update-targets.sh +EXCLUDE_BOARD_DIRS = drivers env include libwrap update-targets.sh +list-boards: + @echo $(sort $(filter-out $(EXCLUDE_BOARD_DIRS),$(notdir $(wildcard bsp/*)))) + + +# MEE programs are any submodules in the software folder +list-programs: + @echo $(shell grep -o '= software/.*$$' .gitmodules | sed -r 's/.*\///') -ifeq ($(RISCV_OPENOCD_PATH),) -RISCV_OPENOCD := openocd -else -RISCV_OPENOCD := $(abspath $(RISCV_OPENOCD_PATH)/bin/openocd) endif ############################################################# @@ -146,21 +125,20 @@ endif ############################################################# ifeq ($(BSP),mee) MEE_SOURCE_PATH ?= freedom-mee -MEE_BSP_PATH = $(BOARD_ROOT)/bsp/$(BOARD) -MEE_LDSCRIPT = $(MEE_BSP_PATH)/mee.lds -MEE_HEADER = $(MEE_BSP_PATH)/mee.h +MEE_LDSCRIPT = $(BSP_DIR)/mee.lds +MEE_HEADER = $(BSP_DIR)/mee.h .PHONY: mee -mee: $(MEE_BSP_PATH)/install/stamp +mee: $(BSP_DIR)/install/stamp -$(MEE_BSP_PATH)/build/Makefile: +$(BSP_DIR)/build/Makefile: @rm -rf $(dir $@) @mkdir -p $(dir $@) cd $(dir $@) && \ CFLAGS="-march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany" \ $(abspath $(MEE_SOURCE_PATH)/configure) \ --host=$(CROSS_COMPILE) \ - --prefix=$(abspath $(MEE_BSP_PATH)/install) \ + --prefix=$(abspath $(BSP_DIR)/install) \ --with-preconfigured \ --with-machine-name=$(BOARD) \ --with-machine-header=$(abspath $(MEE_HEADER)) \ @@ -168,22 +146,22 @@ $(MEE_BSP_PATH)/build/Makefile: --with-builtin-libgloss touch -c $@ -$(MEE_BSP_PATH)/install/stamp: $(MEE_BSP_PATH)/build/Makefile - $(MAKE) -C $(abspath $(MEE_BSP_PATH)/build) install +$(BSP_DIR)/install/stamp: $(BSP_DIR)/build/Makefile + $(MAKE) -C $(abspath $(BSP_DIR)/build) install date > $@ -$(MEE_BSP_PATH)/install/lib/libriscv%.a: $(MEE_BSP_PATH)/install/stamp ;@: +$(BSP_DIR)/install/lib/libriscv%.a: $(BSP_DIR)/install/stamp ;@: -$(MEE_BSP_PATH)/install/lib/libmee.a: $(MEE_BSP_PATH)/install/lib/libriscv__mmachine__$(BOARD).a +$(BSP_DIR)/install/lib/libmee.a: $(BSP_DIR)/install/lib/libriscv__mmachine__$(BOARD).a cp $< $@ -$(MEE_BSP_PATH)/install/lib/libmee-gloss.a: $(MEE_BSP_PATH)/install/lib/libriscv__menv__mee.a +$(BSP_DIR)/install/lib/libmee-gloss.a: $(BSP_DIR)/install/lib/libriscv__menv__mee.a cp $< $@ .PHONY: clean-mee clean-mee: - rm -rf $(MEE_BSP_PATH)/install - rm -rf $(MEE_BSP_PATH)/build + rm -rf $(BSP_DIR)/install + rm -rf $(BSP_DIR)/build clean: clean-mee endif @@ -191,7 +169,7 @@ mee_install: mee $(MAKE) -C $(MEE_SOURCE_PATH) install ############################################################# -# This Section is for elf2hex Compliation +# elf2hex ############################################################# scripts/elf2hex/build/Makefile: scripts/elf2hex/configure @rm -rf $(dir $@) @@ -211,45 +189,59 @@ clean-elf2hex: clean: clean-elf2hex ############################################################# -# This Section is for Software Compilation +# Standalone Project Export ############################################################# -PROGRAM_ELF = $(PROGRAM_ROOT)/software/$(PROGRAM)/$(PROGRAM) -PROGRAM_HEX = $(PROGRAM_ROOT)/software/$(PROGRAM)/$(PROGRAM).hex ifeq ($(BSP),mee) -.PHONY: software -software: $(PROGRAM_ELF) +ifeq ($(STANDALONE_DEST),) +standalone: + $(error Please provide STANDALONE_DEST to create a standalone project) +else -ifneq ($(COREIP_MEM_WIDTH),) -software: $(PROGRAM_HEX) +$(STANDALONE_DEST): +$(STANDALONE_DEST)/%: + mkdir -p $@ + +standalone: \ + $(STANDALONE_DEST) \ + $(STANDALONE_DEST)/bsp \ + $(STANDALONE_DEST)/src \ + $(BSP_DIR)/install/lib/libmee.a \ + $(BSP_DIR)/install/lib/libmee-gloss.a \ + $(SRC_DIR) \ + scripts/standalone.mk + # We have to use $(shell ls ...) here instead of $(wildcard) so that we + # pick up $(BSP_DIR)/install + cp -r $(addprefix $(BSP_DIR)/,$(filter-out build,$(shell ls $(BSP_DIR)))) $</bsp/ + + $(MAKE) -C $(SRC_DIR) clean + cp -r $(SRC_DIR)/* $</src/ + + echo "PROGRAM = $(PROGRAM)" > $</Makefile + cat scripts/standalone.mk >> $</Makefile +endif endif -$(PROGRAM_ELF): \ - $(addprefix $(PROGRAM_ROOT)/software/$(PROGRAM)/,$(shell git -C $(PROGRAM_ROOT)/software/$(PROGRAM) ls-files)) \ - $(MEE_BSP_PATH)/install/lib/libmee.a \ - $(MEE_BSP_PATH)/install/lib/libmee-gloss.a \ - $(MEE_BSP_PATH)/mee.lds - $(MAKE) -C $(dir $@) $(notdir $@) \ - AR=$(RISCV_AR) \ - CC=$(RISCV_GCC) \ - CXX=$(RISCV_GXX) \ - CFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany -g -I$(abspath $(MEE_BSP_PATH)/install/include/)" \ - CXXFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(MEE_BSP_PATH)/install/include/)" \ - LDFLAGS="-nostartfiles -nostdlib -L$(sort $(dir $(abspath $(filter %.a,$^)))) -T$(abspath $(filter %.lds,$^))" \ - LDLIBS="-Wl,--start-group -lc -lgcc -lmee -lmee-gloss -Wl,--end-group" - touch -c $@ +############################################################# +# MEE Software Compilation +############################################################# + +# Generation of $(PROGRAM_ELF) is handled by scripts/standalone.mk +# In this top level Makefile, just describe how to turn the elf into +# $(PROGRAM_HEX) +ifeq ($(BSP),mee) $(PROGRAM_HEX): \ scripts/elf2hex/install/bin/$(CROSS_COMPILE)-elf2hex \ $(PROGRAM_ELF) $< --output $@ --input $(PROGRAM_ELF) --bit-width $(COREIP_MEM_WIDTH) +endif -.PHONY: clean-software -clean-software: - $(MAKE) -C $(dir $(PROGRAM_ELF)) clean -clean: clean-software +############################################################# +# Legacy Software Compilation +############################################################# -else +ifeq ($(BSP),legacy) PROGRAM_DIR=$(dir $(PROGRAM_ELF)) .PHONY: software_clean @@ -266,15 +258,18 @@ dasm: software $(RISCV_OBJDUMP) endif ############################################################# -# This Section is for uploading a program to SPI Flash +# Upload and Debug ############################################################# ifeq ($(BSP),mee) + upload: $(PROGRAM_ELF) scripts/upload --elf $(PROGRAM_ELF) --openocd $(RISCV_OPENOCD) --gdb $(RISCV_GDB) --openocd-config bsp/$(BOARD)/openocd.cfg debug: $(PROGRAM_ELF) scripts/debug --elf $(PROGRAM_ELF) --openocd $(RISCV_OPENOCD) --gdb $(RISCV_GDB) --openocd-config bsp/$(BOARD)/openocd.cfg -else + +else # BSP != mee + OPENOCDCFG ?= bsp/env/$(BOARD)/openocd.cfg OPENOCDARGS += -f $(OPENOCDCFG) @@ -293,7 +288,6 @@ upload: $(RISCV_OPENOCD) $(OPENOCDARGS) & \ $(RISCV_GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDB_UPLOAD_ARGS) $(GDB_UPLOAD_CMDS) && \ echo "Successfully uploaded '$(PROGRAM)' to $(BOARD)." -endif ############################################################# # This Section is for launching the debugger @@ -307,3 +301,5 @@ GDBCMDS += -ex "target extended-remote localhost:$(GDB_PORT)" run_gdb: $(RISCV_GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS) $(GDBCMDS) + +endif # BSP == mee @@ -235,6 +235,19 @@ make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] debug make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] clean ``` +#### Create a Standalone Project #### + +You can export a program to a standalone project directory using the `standalone` +target. The resulting project will be locked to a specific target `BOARD`. Note +that this functionality is only supported for Freedom Metal programs, not the +Legacy Freedom E SDK. + +`STANDALONE_DEST` is a required argument to provide the desired project location. + +``` +make BSP=mee [PROGRAM=hello] [BOARD=sifive-hifive1] STANDALONE_DEST=/path/to/desired/location standalone +``` + Run `make help` for more commands. ### Benchmarking ### diff --git a/scripts/standalone.mk b/scripts/standalone.mk new file mode 100644 index 0000000..244bb7c --- /dev/null +++ b/scripts/standalone.mk @@ -0,0 +1,105 @@ +############################################################# +# Makefile Arguments +############################################################# + +# BSP_DIR sets the path to the target-specific board support package. +BSP_DIR ?= $(abspath bsp) +# SRC_DIR sets the path to the program source directory +SRC_DIR ?= $(abspath src) + +############################################################# +# BSP loading +############################################################# + +# There must be a settings makefile fragment in the BSP's board directory. +ifeq ($(wildcard $(BSP_DIR)/settings.mk),) +$(error Unable to find BSP for $(BOARD), expected to find $(BSP_DIR)/settings.mk) +endif + +# Include the BSP settings +include $(BSP_DIR)/settings.mk + +# Check that settings.mk sets RISCV_ARCH and RISCV_ABI +ifeq ($(RISCV_ARCH),) +$(error $(BSP_DIR)/board.mk must set RISCV_ARCH, the RISC-V ISA string to target) +endif + +ifeq ($(RISCV_ABI),) +$(error $(BSP_DIR)/board.mk must set RISCV_ABI, the ABI to target) +endif + +# Determines the XLEN from the toolchain tuple +ifeq ($(patsubst rv32%,rv32,$(RISCV_ARCH)),rv32) +RISCV_XLEN := 32 +else ifeq ($(patsubst rv64%,rv64,$(RISCV_ARCH)),rv64) +RISCV_XLEN := 64 +else +$(error Unable to determine XLEN from $(RISCV_ARCH)) +endif + +############################################################# +# Toolchain +############################################################# + +# Allow users to select a different cross compiler. +CROSS_COMPILE ?= riscv64-unknown-elf + +# If users don't specify RISCV_PATH then assume that the tools will just be in +# their path. +ifeq ($(RISCV_PATH),) +RISCV_GCC := $(CROSS_COMPILE)-gcc +RISCV_GXX := $(CROSS_COMPILE)-g++ +RISCV_OBJDUMP := $(CROSS_COMPILE)-objdump +RISCV_GDB := $(CROSS_COMPILE)-gdb +RISCV_AR := $(CROSS_COMPILE)-ar +else +RISCV_GCC := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-gcc) +RISCV_GXX := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-g++) +RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-objdump) +RISCV_GDB := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-gdb) +RISCV_AR := $(abspath $(RISCV_PATH)/bin/$(CROSS_COMPILE)-ar) +PATH := $(abspath $(RISCV_PATH)/bin):$(PATH) +endif + +############################################################# +# Software +############################################################# + +ifneq ($(BSP),legacy) + +PROGRAM_ELF ?= $(SRC_DIR)/$(PROGRAM) + +.PHONY: all +all: software + +.PHONY: software +software: $(PROGRAM_ELF) + +ifneq ($(COREIP_MEM_WIDTH),) +software: $(PROGRAM_HEX) +endif + +PROGRAM_SRCS = $(wildcard $(SRC_DIR)/*.c) $(wildcard $(SRC_DIR)/*.h) $(wildcard $(SRC_DIR)/*.S) + +$(PROGRAM_ELF): \ + $(PROGRAM_SRCS) \ + $(BSP_DIR)/install/lib/libmee.a \ + $(BSP_DIR)/install/lib/libmee-gloss.a \ + $(BSP_DIR)/mee.lds + $(MAKE) -C $(dir $@) $(notdir $@) \ + AR=$(RISCV_AR) \ + CC=$(RISCV_GCC) \ + CXX=$(RISCV_GXX) \ + CFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ + CXXFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ + LDFLAGS="-nostartfiles -nostdlib -L$(sort $(dir $(abspath $(filter %.a,$^)))) -T$(abspath $(filter %.lds,$^))" \ + LDLIBS="-Wl,--start-group -lc -lgcc -lmee -lmee-gloss -Wl,--end-group" + touch -c $@ + +.PHONY: clean-software +clean-software: + $(MAKE) -C $(SRC_DIR) clean +clean: clean-software + +endif # BSP != legacy + |